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2019-03-19Reintroduce Cactus-MM and SPM-MM testsv2.1-rc0Antonio Nino Diaz
The code has been taken from commit 99f4fd283b6f ("cactus: Use UART2 instead of UART0") and modified slightly to be integrated in the current master. There are three tests that are failing in the CI. They have been disabled for the time being: - mem_attr_changes_tests() in cactus_main() in the file spm/cactus_mm/cactus_mm_main.c. - Two tests in the file tftf/tests/tests-spm-mm.xml. Change-Id: I6332cbff1cefeb82b9447fae1b613879e65186a1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-03-18Check arguments when building manual testsPaul Beesley
Manual tests require setting USE_NVM=1 and NEW_TEST_SESSION=0 otherwise they will not function properly (as test results will not be preserved across reboots). We should check that these variables have the required values during the build. Change-Id: I72fc8a4badf107fe2ebd6bfb88631828e14a77b3 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-03-18Remove tests-fwu.mk from tests-standard.mkPaul Beesley
The FWU test components are being built as part of the tests-standard.mk configuration but tests-standard does not actually run any FWU tests (see tests-standard.xml). These FWU test components do not need to be built. Change-Id: I11a9012fcf79f4066947b0b2801c64d053f38d42 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-03-18Remove manual tests from tests-standard.mkPaul Beesley
These tests require build variables to be set to non-default values (USE_NVM=1 and NEW_TEST_SESSION=0). This conflicts with other tests that are part of tests-standard (the default set of tests) and so the proposed solution is to remove them from this set. Change-Id: Id54148aab9410002dace33ad595ac1b0cf4678ca Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-03-05Merge "el3_payload: Add initial platform support for RD-N1-Edge"Sandrine Bailleux
2019-03-05readme: Add support for RD-N1-Edge platform in readme.rstChandni Cherukuri
FVP_RD_N1Edge is the Fixed Virtual Platform on which the Trusted Firmware-A Tests are executed for RD-N1-Edge Change-Id: If6ffaa5430b9d41caf6d0697896bc92114e9a87c Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2019-03-05Merge "plat/arm/rdinfra: Add initial platform support for RD-N1-Edge"Sandrine Bailleux
2019-03-04libc: Update makefilesAmbroise Vincent
Added includes and sources of libc to the makefiles. Change-Id: I8e84db9634e0df7d51caa5c5858311672dd3a8d1 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-04libc: Update includesAmbroise Vincent
Reflect the changes in the structure of libc. NB: the include of stdarg.h in nvm_results_helpers.c is not in alphabetical order because it needs to be included before stdio.h. Fixing this would require further changes. Change-Id: I07f62a3450802833408ff3e1f950fd3b643e5e33 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-04libc: Adapt to TFTFAmbroise Vincent
Add support for functions used in TFTF but not in TF-A. Replaced calls to plat_panic_handler with calls to panic, since there is no implementation of the former in TFTF. Change-Id: Ic10de2c6e749db97b932cd7ffbb6067b5befe914 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-04libc: Delete stdlib filesAmbroise Vincent
Keep uuid, rand and strncpy for compatibility reasons Change-Id: Iefd82a5c9df48f6159732027e40a58f7d6afc09f Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-04libc: Import from TF-AAmbroise Vincent
Based on arm-trusted-firware commit 873e394b3bf93214a441f9f98237b58fbbea55aa Change-Id: I510e092f2b9ff333e9461bdde8d80ed1fab1460c Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-27el3_payload: Add initial platform support for RD-N1-EdgeChandni Cherukuri
RD-N1-Edge platform consists of two clusters of four CPUs each. CPU0 of the first cluster is the primary CPU. SoC UART0 is used for the console log. Change-Id: I724c772f95d590154536e7bc1544976e55b983cf Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2019-02-27plat/arm/rdinfra: Add initial platform support for RD-N1-EdgeChandni Cherukuri
RD-N1-Edge platform consists of two clusters of four CPU's each. The FVP for this platform does not support system suspend and resume functionality as there is no wakeup source supported. So all the system suspend and resume related tests are skipped. Change-Id: I33649c7c67023127e736c760bf0ec4193c95ed1a Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2019-02-25Fix header pathsJohn Tsichritzis
Change-Id: Iee1998b9b039dfd21a3ef38c5afeae3fc65569c2 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-12Merge "Update user guide on manual tests"Sandrine Bailleux
2019-02-11Synchronize files with TF-A repositoryAntonio Nino Diaz
Change-Id: Ieb56d0639efd29c2695751b2b36cc98ce2c90dab Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-08Update user guide on manual testsJoel Hutton
Manual tests now rely on passing a flag to dump the flash to a file, then passing that flash file back in when relaunching the model to continue the tests. Change-Id: I77d226b9a1d50f16fd3b13e1254f5152293b23bf Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-01-30Remove SMCCC 2.0 supportAntonio Nino Diaz
SMCCC v2.0 is no longer required for SPM, and won't be needed in the future. The SPM implementation based on SPCI and SPRT was using it, but it has been adapted to SMCCC v1.0. Change-Id: I624b32f9547274b50add4ea81b485cc9f5121e53 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-28Merge changes from topic "sb/exception-dump"Sandrine Bailleux
* changes: Dump some registers when hitting an unexpected exception Improve readability of TFTF exceptions code
2019-01-25Sanitise includes of include/drivers across codebaseAntonio Nino Diaz
Enforce full include path for includes. The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them with the same name). Change-Id: I45e912b16c9fff81f50840dad7e7f90ed6637b2a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-24Dump some registers when hitting an unexpected exceptionSandrine Bailleux
At the moment, no information is printed on the UART whenever we hit an unexpected exception, not even an error message. This is not great from the user's perspective, who has got no idea of what is going on. Now we print an error message, as well as the state of some of the registers. This includes general-purpose registers, as well as some system registers. This is implemented for TFTF running: - in AArch64 state, at EL2; - in AArch64 state, at NS-EL1; - in AArch32 state. We might want to dump more registers in the future but this patch at least provides a basis we can build upon. Also, the SP_EL0 has been removed from the list of registers saved in the CPU context because TFTF always uses SP_ELx and does not touch SP_EL0 at all. Change-Id: I56e4afa917b53b5ccccff1d5d09ac8ccfaa6ae49 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-24Improve readability of TFTF exceptions codeSandrine Bailleux
The only exceptions that TFTF expects are IRQs from the current exception level. All other exceptions are unhandled and put the TFTF into an irrecoverable state. Introduce an unhandled_exception macro that makes it clearer. Change-Id: Ia64600d540007a648c14d8663c91c60c8591eae6 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-23Merge changes from topic "jh/hikey960"Sandrine Bailleux
* changes: hikey960: Fake only 1 core hikey960: Enable SGI hikey960: Enable MMU Hikey960 port: initial commit
2019-01-18Use lock-less printf() in assert macroSandrine Bailleux
This allows to use assertions in interrupt context (which we do in some places currently). Before this patch, a CPU could dead lock itself by: 1. acquiring the printf lock in the normal execution context; 2. taking an interrupt while still holding the lock; 3. inside the interrupt handler, executing an assertion check that fails and thus tries to print an error message on the UART. In a situation where several CPUs might be executing assert() at the same time, we will now get interleaved messages but that should be pretty rare. Change-Id: I6d1603300f6a3ea5756a46338cb950b7ca3e7956 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-15Always print file and line number in panic/unreachable macrosSandrine Bailleux
Release builds used to have a special variant of these macros without the source code location information. This kind of mechanism is useful when writing software that needs both a development and production version so that the source code information is not leaked when the device is in the field. However, in the context of TF-A Tests, it makes little sense, as it's unlikely somebody would ever ship a device with TF-A Tests installed on it. Change-Id: Ic14ad87c2756762807ee71142f21d6973233144e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-15Merge changes from topic "sb/exceptions"Sandrine Bailleux
* changes: Rework IRQ vector code Add CFI debug info to vector entries Improve readability of exceptions stubs code Fix comments in AArch64 exceptions code
2019-01-15Move unstable tests to a separate pool of testsSandrine Bailleux
Some tests have proven unreliable over time. They often time out and the root cause of the problem is unknown as of today. This root cause needs to be investigated and fixed but until then, this patch isolates these tests in their own pool. This allows us to set different trust levels in our CI: - The stable tests are trusted to call out the validity of a patch. - The unstable tests are only informative. Change-Id: Ia8ebb5a29a523ef3a1f324dbd3ddddac02254fd8 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-14Rework IRQ vector codeSandrine Bailleux
Jump straight to a function so that we are not constrained in the 32-instruction limit. Turn the code saving and restoring general-purpose registers into a macro (as opposed to a function), thus removing the need to save the link register before anything else. Overall, this makes the code more straight-forward as we can more clearly see that registers are saved from x0 to x30 (in this order) without any magic twist. Change-Id: Ic70ceee62bec5efc6f6b6a23a7bd4c1d6c2f8a97 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-14Add CFI debug info to vector entriesSandrine Bailleux
This is based on TF-A commit 31823b6961d35a5d53e81d3bf4977ad7b2be81dd. Add Call Frame Information assembler directives to vector entries so that debuggers display the backtrace of functions that triggered a synchronous exception. For example, a function triggering a data abort will be easier to debug if the backtrace can be displayed from a breakpoint at the beginning of the synchronous exception vector. DS-5 needs CFI otherwise it will not attempt to display the backtrace. Other debuggers might have other needs. These debug information are stored in the ELF file but not in the final binary. Change-Id: I1129419f318465049f53b5e41c304ea61fa44483 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-14Improve readability of exceptions stubs codeSandrine Bailleux
Change-Id: Ic9b90d7284b0bbde85fe3e31a025aab40360de03 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-14Fix comments in AArch64 exceptions codeSandrine Bailleux
Change-Id: I88216c14056bee4405233b3e47b59cd3ea355322 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-11hikey960: Fake only 1 coreJohn Tsichritzis
hikey960 has an unresolved power management bug, so for now we can only run single core tests. The bug report can be found here: https://bugs.96boards.org/show_bug.cgi?id=783 Change-Id: I206fafd7677428f81f48d1c7c1d419402149bd37 Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com> Co-authored-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-01-11hikey960: Enable SGIJohn Tsichritzis
Change-Id: I728dcf1121317b52418519421cd12929b00dfac0 Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com> Co-authored-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-01-11hikey960: Enable MMUJohn Tsichritzis
defines and memory mapping for hikey960 Change-Id: I35c57ab0d17553d4f9e1d1b027c4a2308722a870 Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com> Co-authored-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-01-11Hikey960 port: initial commitJohn Tsichritzis
Initial commit to allow building hikey960 as a target Change-Id: Ifaae59b06aaa4065668f05e17eac1a7e2a19ca14 Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com> Co-authored-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2019-01-11xlat v2: Dynamically detect need for CnP bitAntonio Nino Diaz
ARMv8.2-TTCNP is mandatory from ARMv8.2 onwards, but it can be implemented in CPUs that don't implement all mandatory 8.2 features (and so have to claim to be a lower version). This patch removes usage of the ARM_ARCH_AT_LEAST() macro and uses system ID registers to detect whether it is needed to set the bit or not. Change-Id: Ie818c1b91fc319f194d17e21da922798a2a76ec6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-11Partial sync of architectural headers with TF repositoryAntonio Nino Diaz
Change-Id: Ia4850f58f4519a71a049290839027ea7a0521415 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-07Explain why we set HCR.TGE bitSandrine Bailleux
Change-Id: Id55a62e8610f0b162a26a0eeb8f69e4a87910ed7 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-07Merge changes from topic "sb/smc-tests-tos"Sandrine Bailleux
* changes: Relax SMC tests when Trusted OS is present Make UUID buffer optional for is_trusted_os_present()
2019-01-07Merge changes from topic "an/spm"Sandrine Bailleux
* changes: SPM: Test interrupt preemption SPM: Test blocking requests while busy
2019-01-07Relax SMC tests when Trusted OS is presentSandrine Bailleux
When receiving an invalid SMC function ID, the Trusted OS is free to return any error code in x0 but it should at least preserve the values of x1-x3. The SMC tests expected the Trusted OS to return -1 in x0, which is too strong of an assumption. This patch relaxes them to check x1-x3 but ignore x0. Change-Id: I6d516319afeaee9af6aa3674a48c13dba6f7af69 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-07Make UUID buffer optional for is_trusted_os_present()Sandrine Bailleux
The caller might simply want to know whether there is a Trusted OS, without the need to identify it. Change-Id: I97eef8b6e6c4cb948d48735cd7170fced98aee9a Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-04Merge changes from topic "sb/init-code"Sandrine Bailleux
* changes: Share AArch32 arch. init code between cold/warm boot code Rework TFTF AArch64 entry point code
2019-01-04Share AArch32 arch. init code between cold/warm boot codeSandrine Bailleux
Change-Id: I3062f88a09b481f7cb8d03210ea99e33a6a98774 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-03Add some tests for all types of SMCsSandrine Bailleux
Exercise all combinations of SMCs: fast or yielding, SMC32 or SMC64 calling convention, from a 32-bit caller or a 64-bit one. Change-Id: I6d23549818db7f1b3fd0cb4b46e5a592b04b5289 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-03Rename SMC first argumentSandrine Bailleux
'fid' (short for 'function ID') makes for a more explicit name. Change-Id: I41d90c39979162142b0377a68f4be90dc31de253 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-12-21Merge changes from topic "sb/terse-output"Sandrine Bailleux
* changes: Remove redundant error message in tftf_initialise_timer() Remove prints from VExpress NOR flash driver Remove prints in get_overall_test_result() Remove SHELL_COLOR build flag Do not print CPU MPID in mp_printf() Use vprintf() inside mp_printf() Add vprintf() in standard C library
2018-12-20Fix waitus()Sandrine Bailleux
waitus() was missing an instruction barrier before reading the system counter value. As a result, the CPU could speculatively read it and we would potentially base our delay loop on stale values. waitus() now uses the syscounter_read() helper function introduced in the previous patch, which has the required ISB. Change-Id: Ic37254485a9cdc4d4d2c86d245aa3273454e82ff Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-12-20Introduce syscounter_read() helper functionSandrine Bailleux
syscounter_read() reads the system counter value. It encapsulates the instruction barrier required to get an accurate timestamp for any time-sensitive related operation. Change-Id: Ib2cfe7789ee1471e614140d425d29ab5c8d306ea Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>