diff options
Diffstat (limited to 'include/lib/aarch64/arch.h')
-rw-r--r-- | include/lib/aarch64/arch.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index daab0d862..d9bc33c22 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -282,6 +282,9 @@ #define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */ #define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */ +#define ID_AA64PFR1_EL1_SME_SHIFT U(24) +#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) + /* ID_PFR1_EL1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT U(12) #define ID_PFR1_VIRTEXT_MASK U(0xf) @@ -437,6 +440,7 @@ #define TCPAC_BIT (U(1) << 31) #define TAM_BIT (U(1) << 30) #define TTA_BIT (U(1) << 20) +#define ESM_BIT (U(1) << 12) #define TFP_BIT (U(1) << 10) #define CPTR_EZ_BIT (U(1) << 8) #define CPTR_EL3_RESET_VAL U(0x0) @@ -445,7 +449,10 @@ #define CPTR_EL2_RES1 ((ULL(3) << 12) | (ULL(1) << 9) | (ULL(0xff))) #define CPTR_EL2_TCPAC_BIT (ULL(1) << 31) #define CPTR_EL2_TAM_BIT (ULL(1) << 30) +#define CPTR_EL2_SMEN_MASK ULL(0x3) +#define CPTR_EL2_SMEN_SHIFT U(24) #define CPTR_EL2_TTA_BIT (ULL(1) << 20) +#define CPTR_EL2_TSM_BIT (ULL(1) << 12) #define CPTR_EL2_TFP_BIT (ULL(1) << 10) #define CPTR_EL2_TZ_BIT (ULL(1) << 8) #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 @@ -772,6 +779,35 @@ #define ZCR_EL2_LEN_MASK U(0xf) /******************************************************************************* + * Definitions for system register interface to SME + ******************************************************************************/ +#define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 +#define SVCR S3_3_C4_C2_2 +#define TPIDR2_EL0 S3_3_C13_C0_5 +#define SMCR_EL2 S3_4_C1_C2_6 + +/* ID_AA64SMFR0_EL1 definitions */ +#define ID_AA64SMFR0_EL1_FA64_BIT (UL(1) << 63) + +/* SVCR definitions */ +#define SVCR_ZA_BIT (U(1) << 1) +#define SVCR_SM_BIT (U(1) << 0) + +/* SMPRI_EL1 definitions */ +#define SMPRI_EL1_PRIORITY_SHIFT U(0) +#define SMPRI_EL1_PRIORITY_MASK U(0xf) + +/* SMPRIMAP_EL2 definitions */ +/* Register is composed of 16 priority map fields of 4 bits numbered 0-15. */ +#define SMPRIMAP_EL2_MAP_SHIFT(pri) U((pri) * 4) +#define SMPRIMAP_EL2_MAP_MASK U(0xf) + +/* SMCR_ELx definitions */ +#define SMCR_ELX_LEN_SHIFT U(0) +#define SMCR_ELX_LEN_MASK U(0x1ff) +#define SMCR_ELX_FA64_BIT (U(1) << 31) + +/******************************************************************************* * Definitions of MAIR encodings for device and normal memory ******************************************************************************/ /* |