diff options
-rw-r--r-- | el3_payload/plat/hikey960/platform.h | 10 | ||||
-rw-r--r-- | el3_payload/plat/hikey960/platform.mk | 10 | ||||
-rw-r--r-- | plat/hisilicon/hikey960/aarch64/plat_helpers.S | 73 | ||||
-rw-r--r-- | plat/hisilicon/hikey960/hikey960_pwr_state.c | 61 | ||||
-rw-r--r-- | plat/hisilicon/hikey960/hikey960_setup.c | 79 | ||||
-rw-r--r-- | plat/hisilicon/hikey960/include/hikey960_def.h | 11 | ||||
-rw-r--r-- | plat/hisilicon/hikey960/include/platform_def.h | 100 | ||||
-rw-r--r-- | plat/hisilicon/hikey960/platform.mk | 27 | ||||
-rw-r--r-- | plat/hisilicon/hikey960/tests.xml | 19 |
9 files changed, 390 insertions, 0 deletions
diff --git a/el3_payload/plat/hikey960/platform.h b/el3_payload/plat/hikey960/platform.h new file mode 100644 index 000000000..e85163b19 --- /dev/null +++ b/el3_payload/plat/hikey960/platform.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2018, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +#endif /* __PLATFORM_H__ */ diff --git a/el3_payload/plat/hikey960/platform.mk b/el3_payload/plat/hikey960/platform.mk new file mode 100644 index 000000000..bdd521639 --- /dev/null +++ b/el3_payload/plat/hikey960/platform.mk @@ -0,0 +1,10 @@ +# +# Copyright (c) 2018, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +DRAM_BASE := 0x0 +DRAM_SIZE := 0xE0000000 + + diff --git a/plat/hisilicon/hikey960/aarch64/plat_helpers.S b/plat/hisilicon/hikey960/aarch64/plat_helpers.S new file mode 100644 index 000000000..ee59ef907 --- /dev/null +++ b/plat/hisilicon/hikey960/aarch64/plat_helpers.S @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2018, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <platform_def.h> + + .global platform_get_core_pos + .global plat_crash_console_init + .global plat_crash_console_flush + .global plat_crash_console_putc + +/*---------------------------------------------------------------------- + * unsigned int platform_get_core_pos(u_register_t mpid) + * + * Function to calculate the core position on Hikey960. Since Hikey960 + * doesn't feature multithreaded cores, we ignore the MT bit. + * clobbers: x0 - x3 + * --------------------------------------------------------------------- + */ +func platform_get_core_pos + /* x1 = core-id inside cluster */ + ubfx x1, x0, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS + /* x2 = cluster-id */ + ubfx x2, x0, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS + + /* core-position = cluster-id * cores per cluster + core-id */ + mov x3, #PLATFORM_CORE_COUNT_PER_CLUSTER + madd x0, x2, x3, x1 + ret +endfunc platform_get_core_pos + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0 - x4 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, CRASH_CONSOLE_BASE + mov_imm x1, PL011_UART_CLK_IN_HZ + mov_imm x2, PL011_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, CRASH_CONSOLE_BASE + b console_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush() + * Function to force a write of all buffered + * data that hasn't been output. + * Out : return -1 on error else return 0. + * Clobber list : r0 - r1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x1, CRASH_CONSOLE_BASE + b console_core_flush +endfunc plat_crash_console_flush diff --git a/plat/hisilicon/hikey960/hikey960_pwr_state.c b/plat/hisilicon/hikey960/hikey960_pwr_state.c new file mode 100644 index 000000000..5750345de --- /dev/null +++ b/plat/hisilicon/hikey960/hikey960_pwr_state.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2018, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <platform.h> +#include <psci.h> +#include <stddef.h> + +/* + * State IDs for local power states on the HIKEY960. + */ +#define HIKEY960_RUN_STATE_ID 0 /* Valid for CPUs and Clusters */ +#define HIKEY960_RETENTION_STATE_ID 1 /* Valid for only CPUs */ +#define HIKEY960_OFF_STATE_ID 2 /* Valid for CPUs and Clusters */ + +/* + * Suspend depth definitions for each power state + */ +typedef enum { + HIKEY960_RUN_DEPTH = 0, + HIKEY960_RETENTION_DEPTH, + HIKEY960_OFF_DEPTH, +} suspend_depth_t; + +/* The state property array with details of idle state possible for the core */ +static const plat_state_prop_t core_state_prop[] = { + {HIKEY960_RETENTION_DEPTH, HIKEY960_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY}, + {HIKEY960_OFF_DEPTH, HIKEY960_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN}, + {0}, +}; + +/* The state property array with details of idle state possible + for the cluster */ +static const plat_state_prop_t cluster_state_prop[] = { + {HIKEY960_OFF_DEPTH, HIKEY960_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN}, + {0}, +}; + +/* The state property array with details of idle state possible + for the system level */ +static const plat_state_prop_t system_state_prop[] = { + {HIKEY960_OFF_DEPTH, HIKEY960_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN}, + {0}, +}; + +const plat_state_prop_t *plat_get_state_prop(unsigned int level) +{ + switch (level) { + case MPIDR_AFFLVL0: + return core_state_prop; + case MPIDR_AFFLVL1: + return cluster_state_prop; + case MPIDR_AFFLVL2: + return system_state_prop; + default: + return NULL; + } +} diff --git a/plat/hisilicon/hikey960/hikey960_setup.c b/plat/hisilicon/hikey960/hikey960_setup.c new file mode 100644 index 000000000..aaf4db93c --- /dev/null +++ b/plat/hisilicon/hikey960/hikey960_setup.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2018, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <assert.h> +#include <console.h> +#include <gic_v2.h> +#include <platform.h> +#include <platform_def.h> + + +static const mmap_region_t mmap[] = { + {0} +}; + +/* Power Domain Tree Descriptor array */ +const unsigned char hikey960_power_domain_tree_desc[] = { + /* Number of root nodes */ + 1, + /* Number of clusters */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, + /* Number of children for the second cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, +}; + + +const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void) +{ + return hikey960_power_domain_tree_desc; +} + +/* + * Generate the MPID from the core position. + */ +uint64_t tftf_plat_get_mpidr(unsigned int core_pos) +{ + uint64_t mpid; + unsigned int coreid, clusterid; + + assert(core_pos < PLATFORM_CORE_COUNT); + + coreid = core_pos % PLATFORM_CORE_COUNT_PER_CLUSTER; + clusterid = core_pos / PLATFORM_CORE_COUNT_PER_CLUSTER; + + if (clusterid >= PLATFORM_CLUSTER_COUNT) + return INVALID_MPID; + + mpid = (coreid << MPIDR_AFF0_SHIFT) | (clusterid << MPIDR_AFF1_SHIFT); + + return mpid; +} + +void tftf_plat_arch_setup(void) +{ + tftf_plat_configure_mmu(); +} + +void tftf_early_platform_setup(void) +{ + console_init(CRASH_CONSOLE_BASE, PL011_UART_CLK_IN_HZ, + PL011_BAUDRATE); +} + +void tftf_platform_setup(void) +{ + gicv2_init(GICC_REG_BASE, GICD_REG_BASE); + gicv2_probe_gic_cpu_id(); + gicv2_setup_cpuif(); +} + +const mmap_region_t *tftf_platform_get_mmap(void) +{ + return mmap; +} diff --git a/plat/hisilicon/hikey960/include/hikey960_def.h b/plat/hisilicon/hikey960/include/hikey960_def.h new file mode 100644 index 000000000..5caa06cd3 --- /dev/null +++ b/plat/hisilicon/hikey960/include/hikey960_def.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef HIKEY960_DEF_H +#define HIKEY960_DEF_H + +#endif /* HIKEY960_DEF_H */ diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h new file mode 100644 index 000000000..959cac4ab --- /dev/null +++ b/plat/hisilicon/hikey960/include/platform_def.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2018, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define TFTF_BASE 0x1AC98000 + + +#define CACHE_WRITEBACK_GRANULE 0x40 + + +#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_CORE_COUNT_PER_CLUSTER 4 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ + PLATFORM_CORE_COUNT_PER_CLUSTER) +#define PLATFORM_NUM_AFFS (PLATFORM_CORE_COUNT + \ + PLATFORM_CLUSTER_COUNT + 1) +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 +#define PLAT_MAX_PWR_LEVEL MPIDR_AFFLVL2 +#define PLAT_MAX_PWR_STATES_PER_LVL 2 + + +#define PLATFORM_STACK_SIZE 0x2000 +#define PCPU_DV_MEM_STACK_SIZE 0x100 + + +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define MAX_XLAT_TABLES 3 +#define MAX_MMAP_REGIONS 16 + +#define DRAM_BASE 0x0 +#define DRAM_SIZE 0xE0000000 + +#define FLASH_BASE 0x0 +#define FLASH_SIZE 0xC0000000 + +/* + * TFTF_NVM_OFFSET/SIZE correspond to the NVM partition in the partition table + */ +#define TFTF_NVM_SIZE 0x600000 +#define TFTF_NVM_OFFSET 0xBFA00000 + +/* Local state bit width for each level in the state-ID field of power state */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 + +/* GIC-400 related addresses from datasheet */ +#define GICD_REG_BASE 0xE82B1000 +#define GICC_REG_BASE 0xE82B2000 + +/******************************************************************************* + * Non-Secure Software Generated Interupts IDs + ******************************************************************************/ +#define IRQ_NS_SGI_0 0 +#define IRQ_NS_SGI_1 1 +#define IRQ_NS_SGI_2 2 +#define IRQ_NS_SGI_3 3 +#define IRQ_NS_SGI_4 4 +#define IRQ_NS_SGI_5 5 +#define IRQ_NS_SGI_6 6 +#define IRQ_NS_SGI_7 7 + +/* Per-CPU Hypervisor Timer Interrupt ID */ +#define IRQ_PCPU_HP_TIMER 26 +/* Datasheet: TIME00 event*/ +#define IRQ_CNTPSIRQ1 80 + +#define PLAT_MAX_SPI_OFFSET_ID 343 +#define SYS_CNT_BASE1 0xfff14000 +#define SP805_WDOG_BASE 0xE8A06000 + +/* ARM PL011 UART */ +#define CRASH_CONSOLE_BASE 0xFFF32000 +#define PL011_BAUDRATE 115200 +#define PL011_UART_CLK_IN_HZ 19200000 + +/* + * Times(in ms) used by test code for completion of different events. Kept the + * same as in FVP. + */ +#define PLAT_SUSPEND_ENTRY_TIME 15 +#define PLAT_SUSPEND_ENTRY_EXIT_TIME 30 + +/* + * Dummy definitions that we need just to compile... + */ +#define ARM_SECURE_SERVICE_BUFFER_BASE 0 +#define ARM_SECURE_SERVICE_BUFFER_SIZE 100 + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk new file mode 100644 index 000000000..9765a9fff --- /dev/null +++ b/plat/hisilicon/hikey960/platform.mk @@ -0,0 +1,27 @@ +# +# Copyright (c) 2018, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +HIKEY960_PATH := plat/hisilicon/hikey960 + +PLAT_INCLUDES := -I${HIKEY960_PATH}/include/ + +PLAT_SOURCES := ${HIKEY960_PATH}/hikey960_setup.c \ + ${HIKEY960_PATH}/hikey960_pwr_state.c \ + ${HIKEY960_PATH}/aarch64/plat_helpers.S \ + drivers/arm/pl011/${ARCH}/pl011_console.S \ + drivers/arm/gic/gic_common.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/arm_gic_v2.c \ + drivers/arm/timer/system_timer.c \ + drivers/arm/timer/private_timer.c \ + plat/arm/common/arm_timers.c + +ifeq ($(USE_NVM),1) +$(error "Hikey960 port of TFTF doesn't currently support USE_NVM=1") +endif +ifneq ($(TESTS),tftf-validation) +$(error "Hikey960 port currently only supports tftf-validation") +endif diff --git a/plat/hisilicon/hikey960/tests.xml b/plat/hisilicon/hikey960/tests.xml new file mode 100644 index 000000000..c72b7834c --- /dev/null +++ b/plat/hisilicon/hikey960/tests.xml @@ -0,0 +1,19 @@ +<?xml version="1.0" encoding="utf-8"?> + +<!-- + Copyright (c) 2018, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-3-Clause +--> + + +<!-- External references to all individual tests files. --> +<!DOCTYPE testsuites [ + <!ENTITY tests-tftf-validation SYSTEM "../../../tftf/tests/tests-tftf-validation.xml"> +]> + +<testsuites> + + &tests-tftf-validation; + +</testsuites> |