diff options
author | Petre-Ionut Tudor <petre-ionut.tudor@arm.com> | 2019-10-08 16:51:45 +0100 |
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committer | Petre-Ionut Tudor <petre-ionut.tudor@arm.com> | 2019-10-30 15:10:59 +0000 |
commit | f1a45f767ad6dc31ebde044884f157a1deddbf3c (patch) | |
tree | 3e9e306ba52936ca52fa73454eaa133335c5ba46 /tftf | |
parent | 2957ff7660eb3b14ed1ee7ade14218332410e3c0 (diff) | |
download | tf-a-tests-f1a45f767ad6dc31ebde044884f157a1deddbf3c.tar.gz |
Aarch32: Secure PMU counter leak tests
This patch adds Aarch32 support to the PMU counter leak tests.
These tests attempt to profile the Secure world by configuring
EL0 system registers such that the PMU is told to increment
counters at Secure EL1, Secure EL2 and EL3. The tests fail if
useful information was leaked.
The Secure world defends against this type of attack with a
combination of configuring EL3 system registers and saving/restoring
EL0 PMU registers. Exactly which defense is employed depends on the
architecture version.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: I2dcc9e786a18d9859ac089f8008b060d277bee3a
Diffstat (limited to 'tftf')
-rw-r--r-- | tftf/tests/misc_tests/test_pmu_leakage.c | 69 |
1 files changed, 35 insertions, 34 deletions
diff --git a/tftf/tests/misc_tests/test_pmu_leakage.c b/tftf/tests/misc_tests/test_pmu_leakage.c index 09f4d510a..da289992f 100644 --- a/tftf/tests/misc_tests/test_pmu_leakage.c +++ b/tftf/tests/misc_tests/test_pmu_leakage.c @@ -37,6 +37,11 @@ * -v8.5 implemented: * |-- Prohibit general event counters: as in v8.2 Debug. * |-- Prohibit cycle counter: MDCR_EL3.SCCD == 1 + * + * In Aarch32 state the PMU registers have identical names (apart from the + * '_EL0' suffix) and bit fields. As far as the PMU is concerned, the Aarch32 + * counterpart of MDCR_EL3 is the SDCR register, which has both the SCCD and + * SPME bits. */ #include <drivers/arm/arm_gic.h> @@ -47,7 +52,6 @@ #include <string.h> #include <test_helpers.h> -#ifdef AARCH64 #define ITERATIONS_CNT 1000 /* @@ -71,6 +75,12 @@ struct pmu_event_info { unsigned long long avg; }; +#ifdef AARCH64 +#define V8_2_DEBUG_ARCH_SUPPORTED ID_AA64DFR0_V8_2_DEBUG_ARCH_SUPPORTED +#else +#define V8_2_DEBUG_ARCH_SUPPORTED DBGDIDR_V8_2_DEBUG_ARCH_SUPPORTED +#endif + static inline void configure_pmu_cntr0(const uint32_t event) { /* @@ -270,10 +280,13 @@ static bool results_within_allowed_margin(unsigned long long baseline_cnt, */ test_result_t smc_psci_suspend_pc_write_retired(void) { +#if ARM_ARCH_MAJOR < 8 + INFO("%s skipped on ARMv7 and earlier\n", __func__); + return TEST_RESULT_SKIPPED; +#else struct pmu_event_info baseline, cpu_suspend; - SKIP_TEST_IF_ARCH_DEBUG_VERSION_LESS_THAN( - ID_AA64DFR0_V8_2_DEBUG_ARCH_SUPPORTED); + SKIP_TEST_IF_ARCH_DEBUG_VERSION_LESS_THAN(V8_2_DEBUG_ARCH_SUPPORTED); configure_pmu_cntr0(PMU_EV_PC_WRITE_RETIRED); pmu_enable_counting(); @@ -286,6 +299,7 @@ test_result_t smc_psci_suspend_pc_write_retired(void) if (!results_within_allowed_margin(baseline.avg, cpu_suspend.avg)) return TEST_RESULT_FAIL; return TEST_RESULT_SUCCESS; +#endif } /* @@ -295,10 +309,13 @@ test_result_t smc_psci_suspend_pc_write_retired(void) */ test_result_t smc_psci_suspend_cycles(void) { +#if ARM_ARCH_MAJOR < 8 + INFO("%s skipped on ARMv7 and earlier\n", __func__); + return TEST_RESULT_SKIPPED; +#else struct pmu_event_info baseline, cpu_suspend; - SKIP_TEST_IF_ARCH_DEBUG_VERSION_LESS_THAN( - ID_AA64DFR0_V8_2_DEBUG_ARCH_SUPPORTED); + SKIP_TEST_IF_ARCH_DEBUG_VERSION_LESS_THAN(V8_2_DEBUG_ARCH_SUPPORTED); configure_pmu_cycle_cntr(); pmu_enable_counting(); @@ -311,6 +328,7 @@ test_result_t smc_psci_suspend_cycles(void) if (!results_within_allowed_margin(baseline.avg, cpu_suspend.avg)) return TEST_RESULT_FAIL; return TEST_RESULT_SUCCESS; +#endif } /* @@ -320,10 +338,13 @@ test_result_t smc_psci_suspend_cycles(void) */ test_result_t fast_smc_add_pc_write_retired(void) { +#if ARM_ARCH_MAJOR < 8 + INFO("%s skipped on ARMv7 and earlier\n", __func__); + return TEST_RESULT_SKIPPED; +#else struct pmu_event_info baseline, fast_smc_add; - SKIP_TEST_IF_ARCH_DEBUG_VERSION_LESS_THAN( - ID_AA64DFR0_V8_2_DEBUG_ARCH_SUPPORTED); + SKIP_TEST_IF_ARCH_DEBUG_VERSION_LESS_THAN(V8_2_DEBUG_ARCH_SUPPORTED); SKIP_TEST_IF_TSP_NOT_PRESENT(); @@ -338,6 +359,7 @@ test_result_t fast_smc_add_pc_write_retired(void) if (!results_within_allowed_margin(baseline.avg, fast_smc_add.avg)) return TEST_RESULT_FAIL; return TEST_RESULT_SUCCESS; +#endif } /* @@ -347,10 +369,13 @@ test_result_t fast_smc_add_pc_write_retired(void) */ test_result_t fast_smc_add_cycles(void) { +#if ARM_ARCH_MAJOR < 8 + INFO("%s skipped on ARMv7 and earlier\n", __func__); + return TEST_RESULT_SKIPPED; +#else struct pmu_event_info baseline, fast_smc_add; - SKIP_TEST_IF_ARCH_DEBUG_VERSION_LESS_THAN( - ID_AA64DFR0_V8_2_DEBUG_ARCH_SUPPORTED); + SKIP_TEST_IF_ARCH_DEBUG_VERSION_LESS_THAN(V8_2_DEBUG_ARCH_SUPPORTED); SKIP_TEST_IF_TSP_NOT_PRESENT(); @@ -365,29 +390,5 @@ test_result_t fast_smc_add_cycles(void) if (!results_within_allowed_margin(baseline.avg, fast_smc_add.avg)) return TEST_RESULT_FAIL; return TEST_RESULT_SUCCESS; -} -#else -test_result_t smc_psci_suspend_pc_write_retired(void) -{ - INFO("%s skipped on AArch32\n", __func__); - return TEST_RESULT_SKIPPED; -} - -test_result_t smc_psci_suspend_cycles(void) -{ - INFO("%s skipped on AArch32\n", __func__); - return TEST_RESULT_SKIPPED; -} - -test_result_t fast_smc_add_pc_write_retired(void) -{ - INFO("%s skipped on AArch32\n", __func__); - return TEST_RESULT_SKIPPED; -} - -test_result_t fast_smc_add_cycles(void) -{ - INFO("%s skipped on AArch32\n", __func__); - return TEST_RESULT_SKIPPED; -} #endif +} |