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authorManish Pandey <manish.pandey2@arm.com>2020-06-03 20:46:29 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2020-06-03 20:46:29 +0000
commit9060e3e68241a3fc1ad8588c20a97218c34c6c68 (patch)
tree1ef0aaf51b7a762d72ccf11a35f5b08764ca1c69 /tftf
parent0825704538540fa183851de902f83f7e22f69f0f (diff)
parent945095ad9a97bc9469ca095f8dd057a4021297dd (diff)
downloadtf-a-tests-9060e3e68241a3fc1ad8588c20a97218c34c6c68.tar.gz
Merge changes from topic "jb/8.6-features"
* changes: Test that TF-A supports ARMv8.6-ECV Test that TF-A supports ARMv8.6-FGT
Diffstat (limited to 'tftf')
-rw-r--r--tftf/tests/extensions/ecv/test_ecv.c27
-rw-r--r--tftf/tests/extensions/fgt/test_fgt.c32
-rw-r--r--tftf/tests/tests-cpu-extensions.mk2
-rw-r--r--tftf/tests/tests-cpu-extensions.xml2
4 files changed, 63 insertions, 0 deletions
diff --git a/tftf/tests/extensions/ecv/test_ecv.c b/tftf/tests/extensions/ecv/test_ecv.c
new file mode 100644
index 00000000..463353b6
--- /dev/null
+++ b/tftf/tests/extensions/ecv/test_ecv.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <test_helpers.h>
+#include <tftf.h>
+#include <tftf_lib.h>
+#include <string.h>
+
+/*
+ * TF-A is expected to allow access to CNTPOFF_EL2 register from EL2.
+ * Reading this register will trap to EL3 and crash when TF-A has not
+ * allowed access.
+ */
+test_result_t test_ecv_enabled(void)
+{
+ SKIP_TEST_IF_AARCH32();
+
+#ifdef __aarch64__
+ SKIP_TEST_IF_ECV_NOT_SELF_SYNC();
+ read_cntpoff_el2();
+
+ return TEST_RESULT_SUCCESS;
+#endif /* __aarch64__ */
+}
diff --git a/tftf/tests/extensions/fgt/test_fgt.c b/tftf/tests/extensions/fgt/test_fgt.c
new file mode 100644
index 00000000..6213d4bf
--- /dev/null
+++ b/tftf/tests/extensions/fgt/test_fgt.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <test_helpers.h>
+#include <tftf_lib.h>
+#include <tftf.h>
+#include <string.h>
+#include <arch_helpers.h>
+
+/*
+ * TF-A is expected to allow access to ARMv8.6-FGT system registers from EL2.
+ * Reading these registers causes a trap to EL3 and crash when TF-A has not
+ * allowed access.
+ */
+test_result_t test_fgt_enabled(void)
+{
+ SKIP_TEST_IF_AARCH32();
+
+#ifdef __aarch64__
+ SKIP_TEST_IF_FGT_NOT_SUPPORTED();
+ read_hfgrtr_el2();
+ read_hfgwtr_el2();
+ read_hfgitr_el2();
+ read_hdfgrtr_el2();
+ read_hdfgwtr_el2();
+
+ return TEST_RESULT_SUCCESS;
+#endif /* __aarch64__ */
+}
diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk
index 1b7743e1..fedf7837 100644
--- a/tftf/tests/tests-cpu-extensions.mk
+++ b/tftf/tests/tests-cpu-extensions.mk
@@ -9,6 +9,8 @@ TESTS_SOURCES += $(addprefix tftf/tests/, \
extensions/mte/test_mte.c \
extensions/sve/sve_operations.S \
extensions/sve/test_sve.c \
+ extensions/fgt/test_fgt.c \
+ extensions/ecv/test_ecv.c \
runtime_services/arm_arch_svc/smccc_arch_workaround_1.c \
runtime_services/arm_arch_svc/smccc_arch_workaround_2.c \
runtime_services/arm_arch_svc/smccc_arch_soc_id.c \
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index aff6b61e..08a65c7f 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -18,6 +18,8 @@
<testcase name="Check for Pointer Authentication key leakage from TSP" function="test_pauth_leakage_tsp" />
<testcase name="Use MTE Instructions" function="test_mte_instructions" />
<testcase name="Check for MTE register leakage" function="test_mte_leakage" />
+ <testcase name="Use FGT Registers" function="test_fgt_enabled" />
+ <testcase name="Use ECV Registers" function="test_ecv_enabled" />
</testsuite>
<testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">