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authorOlivier Deprez <olivier.deprez@arm.com>2020-12-01 15:34:34 +0100
committerMax Shvetsov <maksims.svecovs@arm.com>2021-02-10 11:56:54 +0000
commit881b1997a0554180db3bd379bf5ff0ce0aa2ce33 (patch)
tree808e9d4af186c39386f70a38b9d4f4c4855c6d13 /tftf
parent103e056ba016d10809948657f6b4f0de93779bc4 (diff)
downloadtf-a-tests-881b1997a0554180db3bd379bf5ff0ce0aa2ce33.tar.gz
[SPM] checks if SIMD vectors are preserved
Populates the SIMD registers in the normal world, then modifies those in the secure world. Upon return to the normal world checks that vectors are restored to the original values. Note: Does not check if SIMD vectors are preserved when returning back to the secure world. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I3ae223af64597f83afa6624122109db2cf0077f7
Diffstat (limited to 'tftf')
-rw-r--r--tftf/tests/runtime_services/secure_service/spm_common.c56
-rw-r--r--tftf/tests/runtime_services/secure_service/test_spm_cpu_features.c70
-rw-r--r--tftf/tests/tests-spm.mk1
-rw-r--r--tftf/tests/tests-spm.xml8
4 files changed, 134 insertions, 1 deletions
diff --git a/tftf/tests/runtime_services/secure_service/spm_common.c b/tftf/tests/runtime_services/secure_service/spm_common.c
index 74a19a6a..cc3ed5df 100644
--- a/tftf/tests/runtime_services/secure_service/spm_common.c
+++ b/tftf/tests/runtime_services/secure_service/spm_common.c
@@ -7,6 +7,62 @@
#include <ffa_endpoints.h>
#include <spm_common.h>
+#define __STR(x) #x
+#define STR(x) __STR(x)
+#define SIMD_TWO_VECTORS_BYTES_STR (2 * SIMD_VECTOR_LEN_BYTES)
+
+void fill_simd_vector_regs(const simd_vector_t v[SIMD_NUM_VECTORS])
+{
+#ifdef __aarch64__
+ __asm__ volatile(
+ "ldp q0, q1, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q2, q3, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q4, q5, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q6, q7, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q8, q9, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q10, q11, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q12, q13, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q14, q15, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q16, q17, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q18, q19, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q20, q21, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q22, q23, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q24, q25, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q26, q27, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q28, q29, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "ldp q30, q31, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "sub %0, %0, #" STR(SIMD_NUM_VECTORS * SIMD_VECTOR_LEN_BYTES) ";"
+ : : "r" (v));
+#endif
+}
+
+void read_simd_vector_regs(simd_vector_t v[SIMD_NUM_VECTORS])
+{
+#ifdef __aarch64__
+ memset(v, 0, sizeof(simd_vector_t) * SIMD_NUM_VECTORS);
+
+ __asm__ volatile(
+ "stp q0, q1, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q2, q3, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q4, q5, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q6, q7, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q8, q9, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q10, q11, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q12, q13, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q14, q15, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q16, q17, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q18, q19, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q20, q21, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q22, q23, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q24, q25, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q26, q27, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q28, q29, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "stp q30, q31, [%0], #" STR(SIMD_TWO_VECTORS_BYTES_STR) ";"
+ "sub %0, %0, #" STR(SIMD_NUM_VECTORS * SIMD_VECTOR_LEN_BYTES) ";"
+ : : "r" (v));
+#endif
+}
+
/*
* check_spmc_execution_level
*
diff --git a/tftf/tests/runtime_services/secure_service/test_spm_cpu_features.c b/tftf/tests/runtime_services/secure_service/test_spm_cpu_features.c
new file mode 100644
index 00000000..3b3edba8
--- /dev/null
+++ b/tftf/tests/runtime_services/secure_service/test_spm_cpu_features.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cactus_test_cmds.h>
+#include <ffa_endpoints.h>
+#include <ffa_helpers.h>
+#include <test_helpers.h>
+
+#define SENDER HYP_ID
+#define RECEIVER SP_ID(1)
+
+static const struct ffa_uuid expected_sp_uuids[] = { {PRIMARY_UUID} };
+
+static test_result_t simd_vector_compare(simd_vector_t a[SIMD_NUM_VECTORS],
+ simd_vector_t b[SIMD_NUM_VECTORS])
+{
+ for (unsigned int num = 0U; num < SIMD_NUM_VECTORS; num++) {
+ if (memcmp(a[num], b[num], sizeof(simd_vector_t)) != 0) {
+ ERROR("Vectors not equal: a:0x%llx b:0x%llx\n",
+ (uint64_t)a[num][0], (uint64_t)b[num][0]);
+ return TEST_RESULT_FAIL;
+ }
+ }
+ return TEST_RESULT_SUCCESS;
+}
+
+/*
+ * Tests that SIMD vectors are preserved during the context switches between
+ * normal world and the secure world.
+ * Fills the SIMD vectors with known values, requests SP to fill the vectors
+ * with a different values, checks that the context is restored on return.
+ */
+test_result_t test_simd_vectors_preserved(void)
+{
+ SKIP_TEST_IF_AARCH32();
+
+ /**********************************************************************
+ * Verify that FFA is there and that it has the correct version.
+ **********************************************************************/
+ CHECK_SPMC_TESTING_SETUP(1, 0, expected_sp_uuids);
+
+ simd_vector_t simd_vectors_send[SIMD_NUM_VECTORS],
+ simd_vectors_receive[SIMD_NUM_VECTORS];
+
+ /* 0x11 is just a dummy value to be distinguished from the value in the
+ * secure world. */
+ for (unsigned int num = 0U; num < SIMD_NUM_VECTORS; num++) {
+ memset(simd_vectors_send[num], 0x11 * num, sizeof(simd_vector_t));
+ }
+
+ fill_simd_vector_regs(simd_vectors_send);
+
+ smc_ret_values ret = cactus_req_simd_fill_send_cmd(SENDER, RECEIVER);
+
+ if (ret.ret0 != FFA_MSG_SEND_DIRECT_RESP_SMC32) {
+ ERROR("Failed to send message. error: %lx\n", ret.ret2);
+ return TEST_RESULT_FAIL;
+ }
+
+ if (cactus_get_response(ret) == CACTUS_ERROR) {
+ return TEST_RESULT_FAIL;
+ }
+
+ read_simd_vector_regs(simd_vectors_receive);
+
+ return simd_vector_compare(simd_vectors_send, simd_vectors_receive);
+}
diff --git a/tftf/tests/tests-spm.mk b/tftf/tests/tests-spm.mk
index 2a949839..73d2baf3 100644
--- a/tftf/tests/tests-spm.mk
+++ b/tftf/tests/tests-spm.mk
@@ -13,4 +13,5 @@ TESTS_SOURCES += \
test_ffa_memory_sharing.c \
test_ffa_rxtx_map.c \
test_ffa_version.c \
+ test_spm_cpu_features.c \
)
diff --git a/tftf/tests/tests-spm.xml b/tftf/tests/tests-spm.xml
index 2637acde..5e809888 100644
--- a/tftf/tests/tests-spm.xml
+++ b/tftf/tests/tests-spm.xml
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="utf-8"?>
<!--
- Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+ Copyright (c) 2018-2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
-->
@@ -66,4 +66,10 @@
function="test_ffa_features" />
</testsuite>
+ <testsuite name="SIMD,SVE Registers context"
+ description="Validate context switch between NWd and SWd" >
+ <testcase name="Check that SIMD registers context is preserved"
+ function="test_simd_vectors_preserved" />
+ </testsuite>
+
</testsuites>