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author | Jimmy Brisson <jimmy.brisson@arm.com> | 2020-04-16 10:54:59 -0500 |
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committer | Jimmy Brisson <jimmy.brisson@arm.com> | 2020-06-03 13:30:29 -0500 |
commit | 945095ad9a97bc9469ca095f8dd057a4021297dd (patch) | |
tree | b0ef7e031939a3c397f5a4ab05cda9ff3bbc438f /tftf/tests | |
parent | 90f1d5caed95873e02071ef040191de52ee84a52 (diff) | |
download | tf-a-tests-945095ad9a97bc9469ca095f8dd057a4021297dd.tar.gz |
Test that TF-A supports ARMv8.6-ECV
Note: This test will cause an unhandled exception in the case that TF-A
is not doing its job and enabling ARMv8.6-ECV Self-Synch when the hardware
supports it.
Change-Id: Iee19963f31fa47b0010e77d7b56b05b71ec1b507
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Diffstat (limited to 'tftf/tests')
-rw-r--r-- | tftf/tests/extensions/ecv/test_ecv.c | 27 | ||||
-rw-r--r-- | tftf/tests/tests-cpu-extensions.mk | 1 | ||||
-rw-r--r-- | tftf/tests/tests-cpu-extensions.xml | 1 |
3 files changed, 29 insertions, 0 deletions
diff --git a/tftf/tests/extensions/ecv/test_ecv.c b/tftf/tests/extensions/ecv/test_ecv.c new file mode 100644 index 000000000..463353b6e --- /dev/null +++ b/tftf/tests/extensions/ecv/test_ecv.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <test_helpers.h> +#include <tftf.h> +#include <tftf_lib.h> +#include <string.h> + +/* + * TF-A is expected to allow access to CNTPOFF_EL2 register from EL2. + * Reading this register will trap to EL3 and crash when TF-A has not + * allowed access. + */ +test_result_t test_ecv_enabled(void) +{ + SKIP_TEST_IF_AARCH32(); + +#ifdef __aarch64__ + SKIP_TEST_IF_ECV_NOT_SELF_SYNC(); + read_cntpoff_el2(); + + return TEST_RESULT_SUCCESS; +#endif /* __aarch64__ */ +} diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk index c57390052..fedf7837d 100644 --- a/tftf/tests/tests-cpu-extensions.mk +++ b/tftf/tests/tests-cpu-extensions.mk @@ -10,6 +10,7 @@ TESTS_SOURCES += $(addprefix tftf/tests/, \ extensions/sve/sve_operations.S \ extensions/sve/test_sve.c \ extensions/fgt/test_fgt.c \ + extensions/ecv/test_ecv.c \ runtime_services/arm_arch_svc/smccc_arch_workaround_1.c \ runtime_services/arm_arch_svc/smccc_arch_workaround_2.c \ runtime_services/arm_arch_svc/smccc_arch_soc_id.c \ diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml index 8b06b5755..08a65c7fc 100644 --- a/tftf/tests/tests-cpu-extensions.xml +++ b/tftf/tests/tests-cpu-extensions.xml @@ -19,6 +19,7 @@ <testcase name="Use MTE Instructions" function="test_mte_instructions" /> <testcase name="Check for MTE register leakage" function="test_mte_leakage" /> <testcase name="Use FGT Registers" function="test_fgt_enabled" /> + <testcase name="Use ECV Registers" function="test_ecv_enabled" /> </testsuite> <testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests"> |