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author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2018-12-18 10:53:34 +0100 |
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committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2019-01-04 11:52:08 +0000 |
commit | 39caa2cfde26781c98b44f1696f684e58cd4a287 (patch) | |
tree | a30fbc9de8455665e14cb19e8fcaca249da2313e /tftf/framework | |
parent | a1948da02c0dbc90264d7664ef2799b3d2f87710 (diff) | |
download | tf-a-tests-39caa2cfde26781c98b44f1696f684e58cd4a287.tar.gz |
Share AArch32 arch. init code between cold/warm boot code
Change-Id: I3062f88a09b481f7cb8d03210ea99e33a6a98774
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Diffstat (limited to 'tftf/framework')
-rw-r--r-- | tftf/framework/aarch32/entrypoint.S | 51 |
1 files changed, 19 insertions, 32 deletions
diff --git a/tftf/framework/aarch32/entrypoint.S b/tftf/framework/aarch32/entrypoint.S index 5832dd741..1f302fa84 100644 --- a/tftf/framework/aarch32/entrypoint.S +++ b/tftf/framework/aarch32/entrypoint.S @@ -16,22 +16,7 @@ * ---------------------------------------------------------------------------- */ func tftf_entrypoint - /* -------------------------------------------------------------------- - * Set the exception vectors - * -------------------------------------------------------------------- - */ - ldr r0, =tftf_vector - stcopr r0, HVBAR - - /* -------------------------------------------------------------------- - * Enable the instruction cache. - * -------------------------------------------------------------------- - */ - ldcopr r0, HSCTLR - ldr r1, =HSCTLR_I_BIT - orr r0, r0, r1 - stcopr r0, HSCTLR - isb + bl arch_init /* -------------------------------------------------------------------- * This code is expected to be executed only by the primary CPU. @@ -95,22 +80,7 @@ func tftf_hotplug_entry */ mov r4, r0 - /* -------------------------------------------------------------------- - * Set the exception vectors - * -------------------------------------------------------------------- - */ - ldr r0, =tftf_vector - stcopr r0, HVBAR - - /* -------------------------------------------------------------------- - * Enable the instruction cache. - * -------------------------------------------------------------------- - */ - ldcopr r0, HSCTLR - ldr r1, =HSCTLR_I_BIT - orr r0, r0, r1 - stcopr r0, HSCTLR - isb + bl arch_init /* -------------------------------------------------------------------- * Give ourselves a small coherent stack to ease the pain of @@ -154,6 +124,23 @@ func tftf_hotplug_entry endfunc tftf_hotplug_entry /* ---------------------------------------------------------------------------- + * Initialize architectural state. + * ---------------------------------------------------------------------------- + */ +func arch_init + /* Set the exception vectors. */ + ldr r0, =tftf_vector + stcopr r0, HVBAR + + /* Enable the instruction cache. */ + ldr r0, =(HSCTLR_RES1 | HSCTLR_I_BIT) + stcopr r0, HSCTLR + + isb + bx lr +endfunc arch_init + +/* ---------------------------------------------------------------------------- * Saves the mpid of the primary core and if the primary core * is already saved then it loops infinitely. * ---------------------------------------------------------------------------- |