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authorDaniel Boulby <daniel.boulby@arm.com>2021-04-06 14:30:19 +0100
committerDaniel Boulby <daniel.boulby@arm.com>2021-06-18 16:34:56 +0100
commit08798acfce407339bc4433c095c6b3a5da31e12a (patch)
tree8d3eea3f3022762780dc1f5def7375a3669a8cb3 /tftf/framework
parente3cfd6df27e46c17f514baab275f0a6209aecb44 (diff)
downloadtf-a-tests-08798acfce407339bc4433c095c6b3a5da31e12a.tar.gz
Change vector_entry names to match tftf code style
Change the exception vector names from CamelCase to lowercase with underscores to better match the tftf code style. Change-Id: Ieffc54edc12cf960af8bca1de36848e7e607d4a2 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Diffstat (limited to 'tftf/framework')
-rw-r--r--tftf/framework/aarch64/exceptions.S34
1 files changed, 17 insertions, 17 deletions
diff --git a/tftf/framework/aarch64/exceptions.S b/tftf/framework/aarch64/exceptions.S
index 677b30fe..218cca3b 100644
--- a/tftf/framework/aarch64/exceptions.S
+++ b/tftf/framework/aarch64/exceptions.S
@@ -23,38 +23,38 @@ vector_base tftf_vector
/*
* Current EL with SP0 : 0x0 - 0x200.
*/
-unhandled_exception SynchronousExceptionSP0
-unhandled_exception IrqSP0
-unhandled_exception FiqSP0
-unhandled_exception SErrorSP0
+unhandled_exception sync_exception_sp_el0
+unhandled_exception irq_sp_el0
+unhandled_exception fiq_sp_el0
+unhandled_exception serror_sp_el0
/*
* Current EL with SPx : 0x200 - 0x400.
*/
-unhandled_exception SynchronousExceptionSPx
+unhandled_exception sync_exception_sp_elx
-vector_entry IrqSPx
+vector_entry irq_sp_elx
b irq_vector_entry
-end_vector_entry IrqSPx
+end_vector_entry irq_sp_elx
-unhandled_exception FiqSPx
-unhandled_exception SErrorSPx
+unhandled_exception fiq_sp_elx
+unhandled_exception serror_sp_elx
/*
* Lower EL using AArch64 : 0x400 - 0x600.
*/
-unhandled_exception SynchronousExceptionA64
-unhandled_exception IrqA64
-unhandled_exception FiqA64
-unhandled_exception SErrorA64
+unhandled_exception sync_exception_aarch64
+unhandled_exception irq_aarch64
+unhandled_exception fiq_aarch64
+unhandled_exception serror_aarch64
/*
* Lower EL using AArch32 : 0x600 - 0x800.
*/
-unhandled_exception SynchronousExceptionA32
-unhandled_exception IrqA32
-unhandled_exception FiqA32
-unhandled_exception SErrorA32
+unhandled_exception sync_exception_aarch32
+unhandled_exception irq_aarch32
+unhandled_exception fiq_aarch32
+unhandled_exception serror_aarch32
.macro save_gp_regs
stp x0, x1, [sp, #0x0]