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author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2019-04-04 11:18:32 +0100 |
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committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2019-04-04 11:19:19 +0100 |
commit | cc0239947d60902a114247277523943fcf537e1d (patch) | |
tree | 853a0aaf2182f0c563e4df8ef6266cc5462924e0 /include | |
parent | 372b675ac20e2addc1c13f36ce61e5f90749f40d (diff) | |
download | tf-a-tests-cc0239947d60902a114247277523943fcf537e1d.tar.gz |
Partial sync of architectural headers with TF-A
Change-Id: I0509065512907217dc17c0ec5ce474e2bb8d4e89
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/lib/aarch32/arch.h | 1 | ||||
-rw-r--r-- | include/lib/aarch64/arch.h | 52 | ||||
-rw-r--r-- | include/lib/aarch64/arch_helpers.h | 1 |
3 files changed, 45 insertions, 9 deletions
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 14b108008..3c2a517a4 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -153,6 +153,7 @@ #define SDCR_SPD_LEGACY U(0x0) #define SDCR_SPD_DISABLE U(0x2) #define SDCR_SPD_ENABLE U(0x3) +#define SDCR_SCCD_BIT (U(1) << 23) #define SDCR_RESET_VAL U(0x0) /* HSCTLR definitions */ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index fea256b19..511854d4d 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -251,6 +251,7 @@ #define SCTLR_NTWE_BIT (ULL(1) << 18) #define SCTLR_WXN_BIT (ULL(1) << 19) #define SCTLR_UWXN_BIT (ULL(1) << 20) +#define SCTLR_IESB_BIT (ULL(1) << 21) #define SCTLR_E0E_BIT (ULL(1) << 24) #define SCTLR_EE_BIT (ULL(1) << 25) #define SCTLR_UCI_BIT (ULL(1) << 26) @@ -285,16 +286,17 @@ /* MDCR_EL3 definitions */ #define MDCR_SPD32(x) ((x) << 14) -#define MDCR_SPD32_LEGACY U(0x0) -#define MDCR_SPD32_DISABLE U(0x2) -#define MDCR_SPD32_ENABLE U(0x3) -#define MDCR_SDD_BIT (U(1) << 16) +#define MDCR_SPD32_LEGACY ULL(0x0) +#define MDCR_SPD32_DISABLE ULL(0x2) +#define MDCR_SPD32_ENABLE ULL(0x3) +#define MDCR_SDD_BIT (ULL(1) << 16) #define MDCR_NSPB(x) ((x) << 12) -#define MDCR_NSPB_EL1 U(0x3) -#define MDCR_TDOSA_BIT (U(1) << 10) -#define MDCR_TDA_BIT (U(1) << 9) -#define MDCR_TPM_BIT (U(1) << 6) -#define MDCR_EL3_RESET_VAL U(0x0) +#define MDCR_NSPB_EL1 ULL(0x3) +#define MDCR_TDOSA_BIT (ULL(1) << 10) +#define MDCR_TDA_BIT (ULL(1) << 9) +#define MDCR_TPM_BIT (ULL(1) << 6) +#define MDCR_SCCD_BIT (ULL(1) << 23) +#define MDCR_EL3_RESET_VAL ULL(0x0) /* MDCR_EL2 definitions */ #define MDCR_EL2_TPMS (U(1) << 14) @@ -427,6 +429,9 @@ #define TCR_TxSZ_MAX ULL(39) #define TCR_TxSZ_MAX_TTST ULL(48) +#define TCR_T0SZ_SHIFT U(0) +#define TCR_T1SZ_SHIFT U(16) + /* (internal) physical address size bits in EL3/EL1 */ #define TCR_PS_BITS_4GB ULL(0x0) #define TCR_PS_BITS_64GB ULL(0x1) @@ -456,12 +461,32 @@ #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) +#define TCR_RGN1_INNER_NC (ULL(0x0) << 24) +#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) +#define TCR_RGN1_INNER_WT (ULL(0x2) << 24) +#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) + +#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) +#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) +#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) +#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) + +#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) +#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) +#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) + #define TCR_TG0_SHIFT U(14) #define TCR_TG0_MASK ULL(3) #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) +#define TCR_TG1_SHIFT U(30) +#define TCR_TG1_MASK ULL(3) +#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) +#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) +#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) + #define TCR_EPD0_BIT (ULL(1) << 7) #define TCR_EPD1_BIT (ULL(1) << 23) @@ -781,6 +806,10 @@ /* MPAM register definitions */ #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) +#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) + +#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) +#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) @@ -833,4 +862,9 @@ #define DIT S3_3_C4_C2_5 #define DIT_BIT BIT(24) +/******************************************************************************* + * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field + ******************************************************************************/ +#define SSBS S3_3_C4_C2_6 + #endif /* ARCH_H */ diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index cdb01f066..b6afdd21c 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -181,6 +181,7 @@ DEFINE_SYSREG_RW_FUNCS(par_el1) DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1) DEFINE_SYSREG_READ_FUNC(id_afr0_el1) DEFINE_SYSREG_READ_FUNC(CurrentEl) |