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author | Olivier Deprez <olivier.deprez@arm.com> | 2020-08-18 14:55:16 +0000 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-08-18 14:55:16 +0000 |
commit | 953ec59b3ed74380c690e550c85eefe19b07716f (patch) | |
tree | 2293a7fcfa63ed11dd88b4bb65e1249f9052c79b /include | |
parent | 56c3942b4eaa2ad85749b11d5895fad6bfb5b61c (diff) | |
parent | 7fac162cd9439783ef60aaf266d22ad454445ace (diff) | |
download | tf-a-tests-953ec59b3ed74380c690e550c85eefe19b07716f.tar.gz |
Merge changes from topic "af/add_branch_protection_makefiles"
* changes:
TFTF: Add ARMv8.5 BTI support in makefiles
TFTF: Add ARMv8.5 BTI support in xlat_tables_v2 library
TFTF: Add ARMv8.5 BTI support in assembler files
TFTF: Add ARMv8.5 BTI-related definitions
Diffstat (limited to 'include')
-rw-r--r-- | include/common/aarch64/asm_macros.S | 24 | ||||
-rw-r--r-- | include/common/asm_macros_common.S | 8 | ||||
-rw-r--r-- | include/lib/aarch64/arch.h | 5 | ||||
-rw-r--r-- | include/lib/aarch64/arch_features.h | 6 | ||||
-rw-r--r-- | include/lib/xlat_tables/xlat_tables_defs.h | 7 |
5 files changed, 47 insertions, 3 deletions
diff --git a/include/common/aarch64/asm_macros.S b/include/common/aarch64/asm_macros.S index 5298ae0cd..d829133f7 100644 --- a/include/common/aarch64/asm_macros.S +++ b/include/common/aarch64/asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -192,4 +192,26 @@ b \label_error .endm + /* + * Helper macro to read system register value into x0 + */ + .macro read reg:req +#if ENABLE_BTI + bti j +#endif + mrs x0, \reg + ret + .endm + + /* + * Helper macro to write value from x1 to system register + */ + .macro write reg:req +#if ENABLE_BTI + bti j +#endif + msr \reg, x1 + ret + .endm + #endif /* __ASM_MACROS_S__ */ diff --git a/include/common/asm_macros_common.S b/include/common/asm_macros_common.S index d38dcce71..1cf94f40e 100644 --- a/include/common/asm_macros_common.S +++ b/include/common/asm_macros_common.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,12 @@ #ifndef __ASM_MACROS_COMMON_S__ #define __ASM_MACROS_COMMON_S__ +#include <lib/utils_def.h> + +#if ENABLE_BTI && !ARM_ARCH_AT_LEAST(8, 5) +#error Branch Target Identification requires ARM_ARCH_MINOR >= 5 +#endif + /* * This macro is used to create a function label and place the * code into a separate text section based on the function name diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 718964e58..2d2a892a8 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -235,6 +235,11 @@ #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ +#define ID_AA64PFR1_EL1_BT_SHIFT U(0) +#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) + +#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ + #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h index fc9e8d439..15eb784a7 100644 --- a/include/lib/aarch64/arch_features.h +++ b/include/lib/aarch64/arch_features.h @@ -62,6 +62,12 @@ static inline bool is_armv8_4_ttst_present(void) ID_AA64MMFR2_EL1_ST_MASK) == 1U; } +static inline bool is_armv8_5_bti_present(void) +{ + return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) & + ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED; +} + static inline unsigned int get_armv8_5_mte_support(void) { return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) & diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index 8a5ce535d..1fd3c83fb 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,6 +62,11 @@ #define OSH (U(0x2) << 6) #define ISH (U(0x3) << 6) +#ifdef __aarch64__ +/* Guarded Page bit */ +#define GP (ULL(1) << 50) +#endif + #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000) /* |