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authorMadhukar Pappireddy <madhukar.pappireddy@arm.com>2020-06-08 16:59:38 -0500
committerMadhukar Pappireddy <madhukar.pappireddy@arm.com>2020-09-02 11:54:08 -0500
commit9473007967d34fede067dcb55849e0901da44688 (patch)
treee131a3f937af72a759d1afa4ce73cb913b6d6fa8 /include
parentaaca1c848767e2bb7935887dca3d540bdc9e6d77 (diff)
downloadtf-a-tests-9473007967d34fede067dcb55849e0901da44688.tar.gz
Minor bug fixes in multicore IRQ spurious test
Program the memory mapped GIC_ITARGETSR register with appropriate cpu mask and assert the expected value is returned upon reading the register. Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I356111d763569c229d7f4c9ea3cd4899305a4954
Diffstat (limited to 'include')
-rw-r--r--include/drivers/arm/gic_v2.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h
index 8432a3fc6..6e7b7646e 100644
--- a/include/drivers/arm/gic_v2.h
+++ b/include/drivers/arm/gic_v2.h
@@ -242,6 +242,11 @@ unsigned int gicv2_gicd_get_ispendr(unsigned int interrupt_id);
unsigned int gicv2_gicc_read_iar(void);
/*
+ * Read and return the target core mask of interrupt ID `num`.
+ */
+uint8_t gicv2_read_itargetsr_value(unsigned int num);
+
+/*
* Set the bit corresponding to `num` in the GICD ICENABLER register.
*/
void gicv2_gicd_set_icenabler(unsigned int num);