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authorAmbroise Vincent <ambroise.vincent@arm.com>2019-07-03 16:44:49 +0100
committerAmbroise Vincent <ambroise.vincent@arm.com>2019-08-01 11:34:18 +0100
commitee3e7cd720887077ad27f48f4c8e681926c16587 (patch)
treeb2be6933f915effc206f73faf1ce5a73118751c7 /fwu
parent6927d85a0429bd247cb76b7cb4201e330fc745a1 (diff)
downloadtf-a-tests-ee3e7cd720887077ad27f48f4c8e681926c16587.tar.gz
ld: Separate code and RO data sections
This prevents the execution of the read-only data. This is done in a similar way in TF-A when the build flag SEPARATE_CODE_AND_RODATA is enabled. The build flag is probably not needed in TF-A Tests. Change-Id: I2bdc0237c00377beb2febeb47207770c85036192 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Diffstat (limited to 'fwu')
-rw-r--r--fwu/ns_bl1u/ns_bl1u.ld.S19
-rw-r--r--fwu/ns_bl2u/ns_bl2u.ld.S17
2 files changed, 24 insertions, 12 deletions
diff --git a/fwu/ns_bl1u/ns_bl1u.ld.S b/fwu/ns_bl1u/ns_bl1u.ld.S
index 2ca5292c..52d80dea 100644
--- a/fwu/ns_bl1u/ns_bl1u.ld.S
+++ b/fwu/ns_bl1u/ns_bl1u.ld.S
@@ -12,22 +12,29 @@ OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
ENTRY(ns_bl1u_entrypoint)
MEMORY {
- ROM (rx): ORIGIN = NS_BL1U_RO_BASE, LENGTH = NS_BL1U_RO_LIMIT - NS_BL1U_RO_BASE
+ ROM (rx): ORIGIN = NS_BL1U_BASE, LENGTH = NS_BL1U_RO_LIMIT - NS_BL1U_BASE
RAM (rwx): ORIGIN = NS_BL1U_RW_BASE, LENGTH = NS_BL1U_RW_LIMIT - NS_BL1U_RW_BASE
}
SECTIONS
{
- . = NS_BL1U_RO_BASE;
+ . = NS_BL1U_BASE;
ASSERT(. == ALIGN(PAGE_SIZE),
- "NS_BL1U_RO_BASE address is not aligned on a page boundary.")
+ "NS_BL1U_BASE address is not aligned on a page boundary.")
- ro . : {
- __RO_START__ = .;
+ .text . : {
+ __TEXT_START__ = .;
*ns_bl1u_entrypoint.o(.text*)
*(.text*)
+ . = ALIGN(PAGE_SIZE);
+ __TEXT_END__ = .;
+ } >ROM
+
+ .rodata . : {
+ __RODATA_START__ = .;
*(.rodata*)
- __RO_END__ = .;
+ . = ALIGN(PAGE_SIZE);
+ __RODATA_END__ = .;
} >ROM
/*
diff --git a/fwu/ns_bl2u/ns_bl2u.ld.S b/fwu/ns_bl2u/ns_bl2u.ld.S
index 48af3036..a6c6d2e8 100644
--- a/fwu/ns_bl2u/ns_bl2u.ld.S
+++ b/fwu/ns_bl2u/ns_bl2u.ld.S
@@ -21,20 +21,25 @@ SECTIONS
ASSERT(. == ALIGN(PAGE_SIZE),
"NS_BL2U_BASE address is not aligned on a page boundary.")
- ro . : {
- __RO_START__ = .;
+ .text . : {
+ __TEXT_START__ = .;
*ns_bl2u_entrypoint.o(.text*)
*(.text*)
- *(.rodata*)
*(.vectors)
- __RO_END_UNALIGNED__ = .;
+ . = ALIGN(PAGE_SIZE);
+ __TEXT_END__ = .;
+ } >RAM
+
+ .rodata . : {
+ __RODATA_START__ = .;
+ *(.rodata*)
/*
* Memory page(s) mapped to this section will be marked as
- * read-only, executable. No RW data from the next section must
+ * read-only, non-executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
. = ALIGN(PAGE_SIZE);
- __RO_END__ = .;
+ __RODATA_END__ = .;
} >RAM
.data . : {