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authorSandrine Bailleux <sandrine.bailleux@arm.com>2018-10-25 12:47:55 +0200
committerSandrine Bailleux <sandrine.bailleux@arm.com>2018-10-25 16:28:51 +0200
commitaef556a8b784fe98fad89591e097b486ab92f6c8 (patch)
treed04505dcb5e8c74b9a69813185f15291bd2f6bda /fwu
parent7af6c6ddaa365891b6710bc5664584349f59c11f (diff)
downloadtf-a-tests-aef556a8b784fe98fad89591e097b486ab92f6c8.tar.gz
Disable hardware alignment checking
At the moment, alignment fault checking is always enabled in TF-A Tests (by setting the HSCTLR/SCTLR.A bit). Thus, for every instruction that loads or stores one or more registers, the hardware checks that the address being accessed is properly aligned to the size of the data element(s) being accessed. If this check fails it causes an alignment fault, which is taken as a data abort exception. However, the compiler is currently unaware that it must not emit load and store instructions resulting in unaligned accesses because we do not compile the source code with -mstrict-align (AArch64) / -mno-unaligned-access (AArch32). Because of this, we might get some unexpected alignment faults. We could request the compiler to align all data accesses but whether this gives us any performance benefit is dependent on the microarchitecture. Thus, it is simpler to just disable hardware alignment checking and let the compiler make the call. Change-Id: I6ef4afb09e0f87c8462a968da1ca2192ee075b40 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Diffstat (limited to 'fwu')
-rw-r--r--fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S4
-rw-r--r--fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S5
-rw-r--r--fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S4
-rw-r--r--fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S5
4 files changed, 8 insertions, 10 deletions
diff --git a/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S b/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
index 61f816f1..22b2f341 100644
--- a/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
+++ b/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
@@ -19,11 +19,11 @@ func ns_bl1u_entrypoint
stcopr r0, HVBAR
/* --------------------------------------------------------------------
- * Enable the instruction cache and data access alignment checks.
+ * Enable the instruction cache.
* --------------------------------------------------------------------
*/
ldcopr r0, HSCTLR
- ldr r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
+ ldr r1, =HSCTLR_I_BIT
orr r0, r0, r1
stcopr r0, HSCTLR
isb
diff --git a/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S b/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
index d83be3be..919ec272 100644
--- a/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
+++ b/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
@@ -19,11 +19,10 @@ func ns_bl1u_entrypoint
asm_write_vbar_el1_or_el2 x1
/* --------------------------------------------------------------------
- * Enable the instruction cache, stack pointer and data access
- * alignment checks.
+ * Enable the instruction cache and stack pointer alignment checks.
* --------------------------------------------------------------------
*/
- mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
+ mov x1, #(SCTLR_I_BIT | SCTLR_SA_BIT)
asm_read_sctlr_el1_or_el2
orr x0, x0, x1
asm_write_sctlr_el1_or_el2 x1
diff --git a/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S b/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
index dfe9e4a4..8ba35491 100644
--- a/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
+++ b/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
@@ -19,11 +19,11 @@ func ns_bl2u_entrypoint
stcopr r0, HVBAR
/* ---------------------------------------------------------------------
- * Enable the instruction cache and data access alignment checks.
+ * Enable the instruction cache.
* ---------------------------------------------------------------------
*/
ldcopr r0, HSCTLR
- ldr r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
+ ldr r1, =HSCTLR_I_BIT
orr r0, r0, r1
stcopr r0, HSCTLR
isb
diff --git a/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S b/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
index 902636e5..4e061b3e 100644
--- a/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
+++ b/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
@@ -19,11 +19,10 @@ func ns_bl2u_entrypoint
asm_write_vbar_el1_or_el2 x1
/* --------------------------------------------------------------------
- * Enable the instruction cache, stack pointer and data access
- * alignment checks.
+ * Enable the instruction cache and stack pointer alignment checks.
* --------------------------------------------------------------------
*/
- mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
+ mov x1, #(SCTLR_I_BIT | SCTLR_SA_BIT)
asm_read_sctlr_el1_or_el2
orr x0, x0, x1
asm_write_sctlr_el1_or_el2 x1