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authorJoel Hutton <Joel.Hutton@Arm.com>2019-04-08 15:46:36 +0100
committerJoel Hutton <Joel.Hutton@arm.com>2019-04-12 15:43:03 +0100
commit6a6f48338312f1b8e5637fa85d7942e6bb9d8bab (patch)
tree758dea2b85bfd8e97a5d86f65b73a81a7f93d15e /fwu
parent8790f025e12065ccccfe4d19fdcc672c80aa784b (diff)
downloadtf-a-tests-6a6f48338312f1b8e5637fa85d7942e6bb9d8bab.tar.gz
Makefile: Enable strict align arch minor version
Add -mstrict-align flag, and -march minor version. These are needed to prevent compilers generating unaligned accesses and enable architectural features respectively. Enable the SCTLR.A and SCTLR.SA alignment checks in all images. TF test has several cases of code which enable the alignment checks. Change-Id: I9a0413786caf94d0abf376aa1b4fb54fc7f2f355 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Diffstat (limited to 'fwu')
-rw-r--r--fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S6
-rw-r--r--fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S6
-rw-r--r--fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S6
-rw-r--r--fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S6
4 files changed, 12 insertions, 12 deletions
diff --git a/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S b/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
index 22b2f341..b9c0d871 100644
--- a/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
+++ b/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,11 +19,11 @@ func ns_bl1u_entrypoint
stcopr r0, HVBAR
/* --------------------------------------------------------------------
- * Enable the instruction cache.
+ * Enable the instruction cache and alignment checks.
* --------------------------------------------------------------------
*/
ldcopr r0, HSCTLR
- ldr r1, =HSCTLR_I_BIT
+ ldr r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
orr r0, r0, r1
stcopr r0, HSCTLR
isb
diff --git a/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S b/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
index 919ec272..a2e9027b 100644
--- a/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
+++ b/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,10 +19,10 @@ func ns_bl1u_entrypoint
asm_write_vbar_el1_or_el2 x1
/* --------------------------------------------------------------------
- * Enable the instruction cache and stack pointer alignment checks.
+ * Enable the instruction cache and alignment checks.
* --------------------------------------------------------------------
*/
- mov x1, #(SCTLR_I_BIT | SCTLR_SA_BIT)
+ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
asm_read_sctlr_el1_or_el2
orr x0, x0, x1
asm_write_sctlr_el1_or_el2 x1
diff --git a/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S b/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
index 8ba35491..28a45725 100644
--- a/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
+++ b/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,11 +19,11 @@ func ns_bl2u_entrypoint
stcopr r0, HVBAR
/* ---------------------------------------------------------------------
- * Enable the instruction cache.
+ * Enable the instruction cache and alignment checks.
* ---------------------------------------------------------------------
*/
ldcopr r0, HSCTLR
- ldr r1, =HSCTLR_I_BIT
+ ldr r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
orr r0, r0, r1
stcopr r0, HSCTLR
isb
diff --git a/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S b/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
index 4e061b3e..0828f5b9 100644
--- a/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
+++ b/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,10 +19,10 @@ func ns_bl2u_entrypoint
asm_write_vbar_el1_or_el2 x1
/* --------------------------------------------------------------------
- * Enable the instruction cache and stack pointer alignment checks.
+ * Enable the instruction cache and alignment checks.
* --------------------------------------------------------------------
*/
- mov x1, #(SCTLR_I_BIT | SCTLR_SA_BIT)
+ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
asm_read_sctlr_el1_or_el2
orr x0, x0, x1
asm_write_sctlr_el1_or_el2 x1