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authorSandrine Bailleux <sandrine.bailleux@arm.com>2018-10-09 11:12:55 +0200
committerSandrine Bailleux <sandrine.bailleux@arm.com>2018-10-10 12:34:34 +0200
commit3cd87d77947ec4fc04440268ed122b4ed81c7781 (patch)
tree78fdee12b026b931029e434f29b4fe09835fe4c9 /fwu
downloadtf-a-tests-2.0.tar.gz
Trusted Firmware-A Tests, version 2.0v2.0
This is the first public version of the tests for the Trusted Firmware-A project. Please see the documentation provided in the source tree for more details. Change-Id: I6f3452046a1351ac94a71b3525c30a4ca8db7867 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: amobal01 <amol.balasokamble@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Co-authored-by: Asha R <asha.r@arm.com> Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Co-authored-by: David Cunado <david.cunado@arm.com> Co-authored-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: dp-arm <dimitris.papastamos@arm.com> Co-authored-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Co-authored-by: Jonathan Wright <jonathan.wright@arm.com> Co-authored-by: Kévin Petit <kevin.petit@arm.com> Co-authored-by: Roberto Vargas <roberto.vargas@arm.com> Co-authored-by: Sathees Balya <sathees.balya@arm.com> Co-authored-by: Shawon Roy <Shawon.Roy@arm.com> Co-authored-by: Soby Mathew <soby.mathew@arm.com> Co-authored-by: Thomas Abraham <thomas.abraham@arm.com> Co-authored-by: Vikram Kanigiri <vikram.kanigiri@arm.com> Co-authored-by: Yatharth Kochar <yatharth.kochar@arm.com>
Diffstat (limited to 'fwu')
-rw-r--r--fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S73
-rw-r--r--fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S74
-rw-r--r--fwu/ns_bl1u/ns_bl1u.ld.S89
-rw-r--r--fwu/ns_bl1u/ns_bl1u.mk79
-rw-r--r--fwu/ns_bl1u/ns_bl1u_main.c226
-rw-r--r--fwu/ns_bl1u/ns_bl1u_tests.c261
-rw-r--r--fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S65
-rw-r--r--fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S66
-rw-r--r--fwu/ns_bl2u/ns_bl2u.ld.S77
-rw-r--r--fwu/ns_bl2u/ns_bl2u.mk75
-rw-r--r--fwu/ns_bl2u/ns_bl2u_main.c59
11 files changed, 1144 insertions, 0 deletions
diff --git a/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S b/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
new file mode 100644
index 00000000..61f816f1
--- /dev/null
+++ b/fwu/ns_bl1u/aarch32/ns_bl1u_entrypoint.S
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <tftf.h>
+
+ .globl ns_bl1u_entrypoint
+
+func ns_bl1u_entrypoint
+ /* --------------------------------------------------------------------
+ * Set the exception vectors.
+ * --------------------------------------------------------------------
+ */
+ ldr r0, =exception_stubs
+ stcopr r0, HVBAR
+
+ /* --------------------------------------------------------------------
+ * Enable the instruction cache and data access alignment checks.
+ * --------------------------------------------------------------------
+ */
+ ldcopr r0, HSCTLR
+ ldr r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
+ orr r0, r0, r1
+ stcopr r0, HSCTLR
+ isb
+
+ /* ---------------------------------------------------------------------
+ * Init C runtime environment.
+ * - Zero-initialise the .bss section;
+ * - Copy the data section from NS-BL1U image (stored in ROM) to the
+ * correct location in RAM.
+ * ---------------------------------------------------------------------
+ */
+ ldr r0, =__BSS_START__
+ ldr r1, =__BSS_SIZE__
+ bl zeromem
+
+ ldr r0, =__DATA_RAM_START__
+ ldr r1, =__DATA_ROM_START__
+ ldr r2, =__DATA_SIZE__
+ bl memcpy4
+
+ /* ---------------------------------------------------------------------
+ * Allocate a stack whose memory will be marked as Normal
+ * Inner-Shareable, Write-Back, Write-Allocate memory when the MMU is
+ * enabled.
+ * There is no risk of reading stale stack memory after enabling the MMU
+ * as only the primary CPU is running at the moment.
+ * ---------------------------------------------------------------------
+ */
+ ldcopr r0, MPIDR
+ bl platform_set_stack
+
+ /* ---------------------------------------------------------------------
+ * Perform early platform setup & platform specific early architectural
+ * setup, e.g. MMU setup.
+ * ---------------------------------------------------------------------
+ */
+ bl tftf_early_platform_setup
+ bl tftf_plat_arch_setup
+
+ /* ---------------------------------------------------------------------
+ * Jump to main function.
+ * ---------------------------------------------------------------------
+ */
+ bl ns_bl1u_main
+dead:
+ b dead
+endfunc ns_bl1u_entrypoint
diff --git a/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S b/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
new file mode 100644
index 00000000..d83be3be
--- /dev/null
+++ b/fwu/ns_bl1u/aarch64/ns_bl1u_entrypoint.S
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <tftf.h>
+
+ .globl ns_bl1u_entrypoint
+
+func ns_bl1u_entrypoint
+ /* --------------------------------------------------------------------
+ * Set the exception vectors.
+ * --------------------------------------------------------------------
+ */
+ adr x0, exception_stubs
+ asm_write_vbar_el1_or_el2 x1
+
+ /* --------------------------------------------------------------------
+ * Enable the instruction cache, stack pointer and data access
+ * alignment checks.
+ * --------------------------------------------------------------------
+ */
+ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
+ asm_read_sctlr_el1_or_el2
+ orr x0, x0, x1
+ asm_write_sctlr_el1_or_el2 x1
+ isb
+
+ /* ---------------------------------------------------------------------
+ * Init C runtime environment.
+ * - Zero-initialise the .bss section;
+ * - Copy the data section from NS-BL1U image (stored in ROM) to the
+ * correct location in RAM.
+ * ---------------------------------------------------------------------
+ */
+ ldr x0, =__BSS_START__
+ ldr x1, =__BSS_SIZE__
+ bl zeromem16
+
+ ldr x0, =__DATA_RAM_START__
+ ldr x1, =__DATA_ROM_START__
+ ldr x2, =__DATA_SIZE__
+ bl memcpy16
+
+ /* ---------------------------------------------------------------------
+ * Allocate a stack whose memory will be marked as Normal
+ * Inner-Shareable, Write-Back, Write-Allocate memory when the MMU is
+ * enabled.
+ * There is no risk of reading stale stack memory after enabling the MMU
+ * as only the primary CPU is running at the moment.
+ * ---------------------------------------------------------------------
+ */
+ mrs x0, mpidr_el1
+ bl platform_set_stack
+
+ /* ---------------------------------------------------------------------
+ * Perform early platform setup & platform specific early architectural
+ * setup, e.g. MMU setup.
+ * ---------------------------------------------------------------------
+ */
+ bl tftf_early_platform_setup
+ bl tftf_plat_arch_setup
+
+ /* ---------------------------------------------------------------------
+ * Jump to main function.
+ * ---------------------------------------------------------------------
+ */
+ bl ns_bl1u_main
+dead:
+ b dead
+endfunc ns_bl1u_entrypoint
diff --git a/fwu/ns_bl1u/ns_bl1u.ld.S b/fwu/ns_bl1u/ns_bl1u.ld.S
new file mode 100644
index 00000000..2ca5292c
--- /dev/null
+++ b/fwu/ns_bl1u/ns_bl1u.ld.S
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+#include <xlat_tables_defs.h>
+
+OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
+OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
+ENTRY(ns_bl1u_entrypoint)
+
+MEMORY {
+ ROM (rx): ORIGIN = NS_BL1U_RO_BASE, LENGTH = NS_BL1U_RO_LIMIT - NS_BL1U_RO_BASE
+ RAM (rwx): ORIGIN = NS_BL1U_RW_BASE, LENGTH = NS_BL1U_RW_LIMIT - NS_BL1U_RW_BASE
+}
+
+SECTIONS
+{
+ . = NS_BL1U_RO_BASE;
+ ASSERT(. == ALIGN(PAGE_SIZE),
+ "NS_BL1U_RO_BASE address is not aligned on a page boundary.")
+
+ ro . : {
+ __RO_START__ = .;
+ *ns_bl1u_entrypoint.o(.text*)
+ *(.text*)
+ *(.rodata*)
+ __RO_END__ = .;
+ } >ROM
+
+ /*
+ * The .data section gets copied from ROM to RAM at runtime.
+ * Its LMA must be 16-byte aligned.
+ * Its VMA must be page-aligned as it marks the first read/write page.
+ */
+ . = NS_BL1U_RW_BASE;
+ ASSERT(. == ALIGN(PAGE_SIZE),
+ "NS_BL1U_RW_BASE address is not aligned on a page boundary.")
+ .data . : ALIGN(16) {
+ __DATA_RAM_START__ = .;
+ *(.data*)
+ __DATA_RAM_END__ = .;
+ } >RAM AT>ROM
+
+ stacks . (NOLOAD) : {
+ __STACKS_START__ = .;
+ *(ns_bl_normal_stacks)
+ __STACKS_END__ = .;
+ } >RAM
+
+ /*
+ * The .bss section gets initialised to 0 at runtime.
+ * Its base address must be 16-byte aligned.
+ */
+ .bss : ALIGN(16) {
+ __BSS_START__ = .;
+ *(SORT_BY_ALIGNMENT(.bss*))
+ *(COMMON)
+ __BSS_END__ = .;
+ } >RAM
+
+ /*
+ * The xlat_table section is for full, aligned page tables (4K).
+ * Removing them from .bss avoids forcing 4K alignment on
+ * the .bss section and eliminates the unecessary zero init
+ */
+ xlat_table (NOLOAD) : {
+ *(xlat_table)
+ } >RAM
+
+ __NS_BL1U_RAM_START__ = ADDR(.data);
+ __NS_BL1U_RAM_END__ = .;
+
+ __DATA_ROM_START__ = LOADADDR(.data);
+ __DATA_SIZE__ = SIZEOF(.data);
+
+ /*
+ * The .data section is the last PROGBITS section so its end marks the end
+ * of the read-only part of NS_BL1U's binary.
+ */
+ ASSERT(__DATA_ROM_START__ + __DATA_SIZE__ <= NS_BL1U_RO_LIMIT,
+ "NS_BL1U's RO section has exceeded its limit.")
+
+ __BSS_SIZE__ = SIZEOF(.bss);
+
+ ASSERT(. <= NS_BL1U_RW_LIMIT, "NS_BL1U's RW section has exceeded its limit.")
+}
diff --git a/fwu/ns_bl1u/ns_bl1u.mk b/fwu/ns_bl1u/ns_bl1u.mk
new file mode 100644
index 00000000..430ff5e1
--- /dev/null
+++ b/fwu/ns_bl1u/ns_bl1u.mk
@@ -0,0 +1,79 @@
+#
+# Copyright (c) 2018, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include lib/xlat_tables_v2/xlat_tables.mk
+include lib/compiler-rt/compiler-rt.mk
+
+NS_BL1U_INCLUDES := \
+ -I${AUTOGEN_DIR} \
+ -Itftf/framework/include \
+ -Iinclude/common \
+ -Iinclude/common/${ARCH} \
+ -Iinclude/drivers \
+ -Iinclude/drivers/arm \
+ -Iinclude/drivers/io \
+ -Iinclude/lib \
+ -Iinclude/lib/${ARCH} \
+ -Iinclude/lib/stdlib \
+ -Iinclude/lib/stdlib/sys \
+ -Iinclude/lib/utils \
+ -Iinclude/lib/xlat_tables \
+ -Iinclude/plat/common \
+ -Iinclude/runtime_services
+
+# TODO: Remove dependency on TFTF files.
+NS_BL1U_SOURCES := $(addprefix tftf/framework/, \
+ ${ARCH}/arch.c \
+ ${ARCH}/asm_debug.S \
+ ${ARCH}/exceptions.S \
+ debug.c \
+)
+
+NS_BL1U_SOURCES += drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ fwu/ns_bl1u/${ARCH}/ns_bl1u_entrypoint.S \
+ fwu/ns_bl1u/ns_bl1u_main.c \
+ lib/${ARCH}/cache_helpers.S \
+ lib/${ARCH}/exception_stubs.S \
+ lib/${ARCH}/misc_helpers.S \
+ lib/locks/${ARCH}/spinlock.S \
+ lib/smc/${ARCH}/asm_smc.S \
+ lib/smc/${ARCH}/smc.c \
+ ${STD_LIB_SOURCES} \
+ lib/utils/mp_printf.c \
+ lib/utils/uuid.c \
+ ${XLAT_TABLES_LIB_SRCS} \
+ plat/arm/common/arm_fwu_io_storage.c \
+ plat/common/${ARCH}/platform_helpers.S \
+ plat/common/${ARCH}/platform_up_stack.S \
+ plat/common/image_loader.c \
+ plat/common/plat_common.c
+
+NS_BL1U_SOURCES += ${COMPILER_RT_SRCS}
+
+ifeq (${FWU_BL_TEST},1)
+ NS_BL1U_SOURCES += fwu/ns_bl1u/ns_bl1u_tests.c
+endif
+
+NS_BL1U_LINKERFILE := fwu/ns_bl1u/ns_bl1u.ld.S
+
+# NS_BL1U requires accessing the flash. Force-enable it.
+NS_BL1U_DEFINES := -DUSE_NVM=1
+
+$(eval $(call add_define,NS_BL1U_DEFINES,ARM_ARCH_MAJOR))
+$(eval $(call add_define,NS_BL1U_DEFINES,ARM_ARCH_MINOR))
+$(eval $(call add_define,NS_BL1U_DEFINES,DEBUG))
+$(eval $(call add_define,NS_BL1U_DEFINES,ENABLE_ASSERTIONS))
+$(eval $(call add_define,NS_BL1U_DEFINES,FWU_BL_TEST))
+$(eval $(call add_define,NS_BL1U_DEFINES,LOG_LEVEL))
+$(eval $(call add_define,NS_BL1U_DEFINES,PLAT_${PLAT}))
+ifeq (${ARCH},aarch32)
+ $(eval $(call add_define,NS_BL1U_DEFINES,AARCH32))
+else
+ $(eval $(call add_define,NS_BL1U_DEFINES,AARCH64))
+endif
+
+ns_bl1u: ${AUTOGEN_DIR}/tests_list.h
diff --git a/fwu/ns_bl1u/ns_bl1u_main.c b/fwu/ns_bl1u/ns_bl1u_main.c
new file mode 100644
index 00000000..46c22636
--- /dev/null
+++ b/fwu/ns_bl1u/ns_bl1u_main.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <assert.h>
+#include <debug.h>
+#include <errno.h>
+#include <image_loader.h>
+#include <io_fip.h>
+#include <io_storage.h>
+#include <mmio.h>
+#include <nvm.h>
+#include <platform.h>
+#include <platform_def.h>
+#include <smccc.h>
+#include <status.h>
+#include <string.h>
+#include <tftf.h>
+#include <tftf_lib.h>
+
+#define FWU_NON_SECURE (0x0)
+#define FWU_SECURE (0x1)
+
+#define FWU_NON_EXEC (0x0)
+#define FWU_EXEC (0x1)
+
+/* This size is used to exercise partial copy */
+#define FWU_COPY_PARTIAL_SIZE (0x10)
+
+extern const char version_string[];
+
+typedef void (*ns_bl2u_entrypoint_t)(unsigned long);
+
+void ns_bl1u_fwu_test_main(void);
+
+/*
+ * This structure will be used for:
+ * 1. Assigning unique image identifier.
+ * 2. Assigning attribute to FWU image.
+ * (FWU_NON_SECURE/FWU_SECURE)
+ * (FWU_NON_EXEC/FWU_EXEC)
+ */
+typedef struct fwu_image_load_desc {
+ unsigned int image_id;
+ unsigned int secure;
+ unsigned int execute;
+} fwu_image_load_desc_t;
+
+static const fwu_image_load_desc_t ns_bl1u_desc[] = {
+ [0] = {
+ /* Initialize FWU_CERT image params */
+ .image_id = FWU_CERT_ID,
+ .secure = FWU_SECURE,
+ },
+ [1] = {
+ /*
+ * Initialize SCP_BL2U image params
+ * Not needed for FVP platform.
+ */
+ .image_id = SCP_BL2U_IMAGE_ID,
+ .secure = FWU_SECURE,
+ },
+ [2] = {
+ /* Initialize BL2U image params */
+ .image_id = BL2U_IMAGE_ID,
+ .secure = FWU_SECURE,
+ .execute = FWU_EXEC
+ },
+ [3] = {
+ /* Initialize NS_BL2U image params */
+ .image_id = NS_BL2U_IMAGE_ID,
+ }
+};
+
+static long smc_result;
+
+#define CHECK_SMC_RESULT(_r) do { \
+ if (smc_result != _r) { \
+ ERROR("NS_BL1U: SMC call failed with result:%li\n", smc_result);\
+ panic(); \
+ } \
+ } while (0);
+
+static void ns_bl1u_fwu_smc_call(unsigned int smc_id,
+ unsigned long x1,
+ unsigned long x2,
+ unsigned long x3,
+ unsigned long x4)
+{
+ smc_ret_values fwu_result = {0};
+ smc_args fwu_params = {smc_id, x1, x2, x3, x4};
+ fwu_result = tftf_smc(&fwu_params);
+ smc_result = fwu_result.ret0;
+}
+
+
+/*******************************************************************************
+ * Following are the responsibilities of NS_BL1U image:
+ * Load FWU images from external NVM memory to NS RAM.
+ * Call SMC's to authenticate images.
+ * Jump to NS_BL2U which carries out next FWU steps.
+******************************************************************************/
+void ns_bl1u_main(void)
+{
+ int index;
+ unsigned int img_size;
+ int err;
+ unsigned long offset;
+ ns_bl2u_entrypoint_t ns_bl2u_entrypoint =
+ (ns_bl2u_entrypoint_t)NS_BL2U_BASE;
+ const fwu_image_load_desc_t *image_desc;
+
+ NOTICE("NS_BL1U: %s\n", version_string);
+ NOTICE("NS_BL1U: %s\n", build_message);
+
+ tftf_arch_setup();
+
+ plat_fwu_io_setup();
+
+#if FWU_BL_TEST
+ ns_bl1u_fwu_test_main();
+#endif
+
+ for (index = 0; index < ARRAY_SIZE(ns_bl1u_desc); index++) {
+
+ image_desc = &ns_bl1u_desc[index];
+
+#if PLAT_fvp
+ /* Skip SCP_BL2U loading for FVP */
+ if (image_desc->image_id == SCP_BL2U_IMAGE_ID)
+ continue;
+#endif
+
+ INFO("NS_BL1U: Loading image '%s' (ID:%u)\n",
+ get_image_name(image_desc->image_id),
+ image_desc->image_id);
+
+ img_size = get_image_size(image_desc->image_id);
+ INFO("NS_BL1U: Image size = %d\n", img_size);
+ if (img_size == 0) {
+ ERROR("NS_BL1U: Invalid image size\n");
+ panic();
+ }
+
+ if (image_desc->secure == FWU_SECURE) {
+
+ offset = get_image_offset(image_desc->image_id);
+
+ INFO("NS_BL1U: Calling COPY SMC for partial copy\n");
+ ns_bl1u_fwu_smc_call(FWU_SMC_IMAGE_COPY, image_desc->image_id,
+ offset, FWU_COPY_PARTIAL_SIZE, img_size);
+ CHECK_SMC_RESULT(0);
+
+ ns_bl1u_fwu_smc_call(FWU_SMC_IMAGE_COPY, image_desc->image_id,
+ (offset + FWU_COPY_PARTIAL_SIZE),
+ (img_size - FWU_COPY_PARTIAL_SIZE), img_size);
+ CHECK_SMC_RESULT(0);
+ } else {
+ /* The only non-secure image in ns_bl1u_desc[] should be NS_BL2U */
+ assert(image_desc->image_id == NS_BL2U_IMAGE_ID);
+
+ err = load_image(image_desc->image_id, NS_BL2U_BASE);
+ if (err) {
+ ERROR("NS_BL1U: Failed to load NS_BL2U\n");
+ panic();
+ }
+ offset = NS_BL2U_BASE;
+ }
+
+ INFO("NS_BL1U: Calling AUTH SMC\n");
+ ns_bl1u_fwu_smc_call(FWU_SMC_IMAGE_AUTH, image_desc->image_id,
+ offset, img_size, 0);
+ CHECK_SMC_RESULT(0);
+#if FWU_BL_TEST
+ /* Check if authenticating again the same image returns error. */
+ INFO("NS_BL1U: TEST Calling SMC to auth again\n");
+ ns_bl1u_fwu_smc_call(FWU_SMC_IMAGE_AUTH, ns_bl1u_desc[index].image_id,
+ offset, img_size, 0);
+ CHECK_SMC_RESULT(-EPERM);
+#endif
+ if (image_desc->execute == FWU_EXEC) {
+ INFO("NS_BL1U: Calling EXECUTE SMC\n");
+ ns_bl1u_fwu_smc_call(FWU_SMC_IMAGE_EXECUTE, image_desc->image_id,
+ 0, 0, 0);
+ CHECK_SMC_RESULT(0);
+
+#if FWU_BL_TEST
+ /* Check if executing again the same image returns error. */
+ INFO("NS_BL1U: TEST Calling SMC to execute again\n");
+ ns_bl1u_fwu_smc_call(FWU_SMC_IMAGE_EXECUTE,
+ ns_bl1u_desc[index].image_id, 0, 0, 0);
+ CHECK_SMC_RESULT(-EPERM);
+#endif
+ } else {
+ /*
+ * If the image is not executable, its internal state
+ * needs to be reset, unless it is for later consumption
+ * by another CPU (like for the SCP_BL2U firmware).
+ */
+ if (image_desc->image_id != SCP_BL2U_IMAGE_ID) {
+ INFO("NS_BL1U: Calling RESET SMC\n");
+ ns_bl1u_fwu_smc_call(FWU_SMC_IMAGE_RESET,
+ image_desc->image_id,
+ 0, 0, 0);
+ CHECK_SMC_RESULT(0);
+ }
+ }
+ }
+
+ /*
+ * Clean and invalidate the caches.
+ * And disable the MMU before jumping to NS_BL2U.
+ */
+ disable_mmu_icache();
+
+ /*
+ * The argument passed to NS_BL2U is not used currently.
+ * But keeping the argument passing mechanism for future use.
+ */
+ ns_bl2u_entrypoint(0);
+
+ panic();
+}
diff --git a/fwu/ns_bl1u/ns_bl1u_tests.c b/fwu/ns_bl1u/ns_bl1u_tests.c
new file mode 100644
index 00000000..082439a9
--- /dev/null
+++ b/fwu/ns_bl1u/ns_bl1u_tests.c
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*******************************************************************************
+ * Test the FWU SMC interface in Trusted Firmware-A, which is implemented in
+ * BL1.
+ ******************************************************************************/
+
+#include <debug.h>
+#include <errno.h>
+#include <io_fip.h>
+#include <platform_def.h>
+#include <smccc.h>
+#include <status.h>
+#include <tftf.h>
+#include <tftf_lib.h>
+
+/* Expected number of SMC calls supported in BL1 */
+#define BL1_NUM_SMC_CALLS 11
+
+/* Expected version of BL1 SMC implementation */
+#define BL1_SMC_VER_VALUE 1
+
+typedef struct {
+ /* Description to print before sending the SMC */
+ const char *description;
+ /* The arguments to pass to the SMC */
+ const smc_args args;
+ /* The expected SMC return value */
+ u_register_t expect;
+} ns_bl1u_test_t;
+
+/*
+ * The tests consist in sending a succession of SMCs to trigger FWU operations
+ * in BL1. The order of the SMCs is important because they internally change the
+ * FWU state machine in Trusted Firmware-A.
+ */
+static const ns_bl1u_test_t tests[] = {
+ /* Basic FWU SMC handler test cases. */
+ {
+ .description = "BL1_SMC_CALL_COUNT",
+ .args = { BL1_SMC_CALL_COUNT, 0, 0, 0, 0 },
+ .expect = BL1_NUM_SMC_CALLS,
+ },
+
+ {
+ .description = "BL1_SMC_VERSION",
+ .args = { BL1_SMC_VERSION, 0, 0, 0, 0 },
+ .expect = BL1_SMC_VER_VALUE,
+ },
+
+ {
+ .description = "Invalid SMC",
+ .args = { 0xdeadbeef, 0, 0, 0, 0 },
+ .expect = SMC_UNKNOWN,
+ },
+
+ /* FWU_SMC_IMAGE_COPY test cases. */
+ {
+ .description = "IMAGE_COPY with invalid image_id",
+ .args = { FWU_SMC_IMAGE_COPY, 0xdeadbeef, 0, 0, 0 },
+ .expect = -EPERM,
+ },
+
+ {
+ .description = "IMAGE_COPY with non-secure image_id",
+ .args = { FWU_SMC_IMAGE_COPY, NS_BL2U_IMAGE_ID, 0, 0, 0 },
+ .expect = -EPERM,
+ },
+
+ {
+ .description = "IMAGE_COPY with valid args",
+ .args = { FWU_SMC_IMAGE_COPY, FWU_CERT_ID, PLAT_ARM_FWU_FIP_BASE, 0x20, 0x20 },
+ .expect = STATUS_SUCCESS,
+ },
+
+ {
+ .description = "IMAGE_COPY to copy an image_id again",
+ .args = { FWU_SMC_IMAGE_COPY, FWU_CERT_ID, PLAT_ARM_FWU_FIP_BASE, 0x20, 0x20 },
+ .expect = -EPERM,
+ },
+
+ {
+ .description = "IMAGE_COPY with source address not mapped",
+ .args = { FWU_SMC_IMAGE_COPY, BL2U_IMAGE_ID, 0, 0, 0 },
+ .expect = -ENOMEM,
+ },
+
+ {
+ .description = "IMAGE_COPY with source size not mapped",
+ .args = { FWU_SMC_IMAGE_COPY, BL2U_IMAGE_ID, PLAT_ARM_FWU_FIP_BASE, 0xdeadbeef, 0xdeadbeef },
+ .expect = -ENOMEM,
+ },
+
+ {
+ .description = "IMAGE_COPY with image size more than secure mem",
+ .args = { FWU_SMC_IMAGE_COPY, BL2U_IMAGE_ID, PLAT_ARM_FWU_FIP_BASE, 0x40000, 0x40000 },
+ .expect = -ENOMEM,
+ },
+
+ {
+ .description = "IMAGE_COPY with image size 0",
+ .args = { FWU_SMC_IMAGE_COPY, BL2U_IMAGE_ID, PLAT_ARM_FWU_FIP_BASE, 0, 0 },
+ .expect = -ENOMEM,
+ },
+
+ /*
+ * At this point, the FWU Certificate Image has been copied by a
+ * previous test. Try to load the BL2U image over it at the same
+ * address.
+ */
+ {
+ .description = "IMAGE_COPY with an image that overlaps a different one",
+ .args = { FWU_SMC_IMAGE_COPY, BL2U_IMAGE_ID, PLAT_ARM_FWU_FIP_BASE, 0x20, 0x40 },
+ .expect = -EPERM,
+ },
+
+ /*
+ * The authentication of the FWU certificate will fail, which will set
+ * the state of this image to "RESET" for the following tests.
+ */
+ {
+ .description = "IMAGE_AUTH with an invalid image",
+ .args = { FWU_SMC_IMAGE_AUTH, FWU_CERT_ID, PLAT_ARM_FWU_FIP_BASE, 0x20, 0x20 },
+ .expect = -EAUTH,
+ },
+
+ {
+ .description = "IMAGE_COPY with 1st block size in partial copy",
+ .args = { FWU_SMC_IMAGE_COPY, BL2U_IMAGE_ID, PLAT_ARM_FWU_FIP_BASE, 0x20, 0x40 },
+ .expect = STATUS_SUCCESS,
+ },
+
+ {
+ .description = "IMAGE_AUTH while copying the image",
+ .args = { FWU_SMC_IMAGE_AUTH, BL2U_IMAGE_ID, PLAT_ARM_FWU_FIP_BASE, 0x40, 0 },
+ .expect = -EPERM,
+ },
+
+ {
+ .description = "IMAGE_COPY with last block with invalid source in partial copy",
+ .args = { FWU_SMC_IMAGE_COPY, BL2U_IMAGE_ID, 0, 0x21, 0x40 },
+ .expect = -ENOMEM,
+ },
+
+ {
+ .description = "IMAGE_COPY with last block size > total size in partial copy",
+ .args = { FWU_SMC_IMAGE_COPY, BL2U_IMAGE_ID, PLAT_ARM_FWU_FIP_BASE, 0x21, 0x40 },
+ .expect = STATUS_SUCCESS,
+ },
+
+ {
+ .description = "IMAGE_AUTH to RESET the image state",
+ .args = { FWU_SMC_IMAGE_AUTH, BL2U_IMAGE_ID, PLAT_ARM_FWU_FIP_BASE, 0x40, 0 },
+ .expect = -EAUTH,
+ },
+
+ {
+ .description = "IMAGE_COPY with block size > total size",
+ .args = { FWU_SMC_IMAGE_COPY, BL2U_IMAGE_ID, PLAT_ARM_FWU_FIP_BASE, 0x21, 0x20 },
+ .expect = STATUS_SUCCESS,
+ },
+
+ {
+ .description = "IMAGE_RESET to RESET the image state",
+ .args = { FWU_SMC_IMAGE_RESET, BL2U_IMAGE_ID, 0, 0, 0 },
+ .expect = STATUS_SUCCESS,
+ },
+
+
+ /* FWU_SMC_IMAGE_AUTH test cases. */
+ {
+ .description = "IMAGE_AUTH with invalid image_id",
+ .args = { FWU_SMC_IMAGE_AUTH, 0, 0, 0, 0 },
+ .expect = -EPERM,
+ },
+
+ {
+ .description = "IMAGE_AUTH with secure image not copied",
+ .args = { FWU_SMC_IMAGE_AUTH, BL2U_IMAGE_ID, 0, 0, 0 },
+ .expect = -EPERM,
+ },
+
+ {
+ .description = "IMAGE_AUTH with source address not mapped",
+ .args = { FWU_SMC_IMAGE_AUTH, NS_BL2U_IMAGE_ID, 0, 0, 0 },
+ .expect = -ENOMEM,
+ },
+
+ {
+ .description = "IMAGE_AUTH with source size not mapped",
+ .args = { FWU_SMC_IMAGE_AUTH, NS_BL2U_IMAGE_ID, PLAT_ARM_FWU_FIP_BASE, 0xdeadbeef, 0 },
+ .expect = -ENOMEM,
+ },
+
+ {
+ .description = "IMAGE_COPY to copy after auth failure",
+ .args = { FWU_SMC_IMAGE_COPY, FWU_CERT_ID, PLAT_ARM_FWU_FIP_BASE, 0x40, 0x40 },
+ .expect = STATUS_SUCCESS,
+ },
+
+ {
+ .description = "IMAGE_AUTH with valid args for copied image",
+ .args = { FWU_SMC_IMAGE_AUTH, FWU_CERT_ID, 0, 0, 0 },
+ .expect = -EAUTH,
+ },
+
+ /* FWU_SMC_IMAGE_EXECUTE test cases. */
+ {
+ .description = "IMAGE_EXECUTE with invalid image_id",
+ .args = { FWU_SMC_IMAGE_EXECUTE, 0, 0, 0, 0 },
+ .expect = -EPERM,
+ },
+
+ {
+ .description = "IMAGE_EXECUTE with non-executable image_id",
+ .args = { FWU_SMC_IMAGE_EXECUTE, FWU_CERT_ID, 0, 0, 0 },
+ .expect = -EPERM,
+ },
+
+ {
+ .description = "IMAGE_EXECUTE with un-authenticated image_id",
+ .args = { FWU_SMC_IMAGE_EXECUTE, BL2U_IMAGE_ID, 0, 0, 0 },
+ .expect = -EPERM,
+ },
+
+
+ /* FWU_SMC_IMAGE_RESUME test case. */
+ {
+ .description = "IMAGE_RESUME with invalid args",
+ .args = { FWU_SMC_IMAGE_RESUME, 0, 0, 0, 0 },
+ .expect = -EPERM,
+ },
+};
+
+
+void ns_bl1u_fwu_test_main(void)
+{
+ NOTICE("NS_BL1U: ***** Starting NS_BL1U FWU test *****\n");
+
+ for (int i = 0 ; i < ARRAY_SIZE(tests); ++i) {
+ u_register_t result;
+
+ INFO("NS_BL1U: %s\n", tests[i].description);
+
+ smc_ret_values smc_ret;
+ smc_ret = tftf_smc(&tests[i].args);
+ result = smc_ret.ret0;
+
+ if (result != tests[i].expect) {
+ ERROR("NS_BL1U: Unexpected SMC return value 0x%lX, "
+ "expected 0x%lX\n", result, tests[i].expect);
+ panic();
+ }
+ }
+
+ NOTICE("NS_BL1U: ***** All FWU test passed *****\n\n");
+}
diff --git a/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S b/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
new file mode 100644
index 00000000..dfe9e4a4
--- /dev/null
+++ b/fwu/ns_bl2u/aarch32/ns_bl2u_entrypoint.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <tftf.h>
+
+ .globl ns_bl2u_entrypoint
+
+func ns_bl2u_entrypoint
+ /* ---------------------------------------------------------------------
+ * Set the exception vectors.
+ * ---------------------------------------------------------------------
+ */
+ ldr r0, =exception_stubs
+ stcopr r0, HVBAR
+
+ /* ---------------------------------------------------------------------
+ * Enable the instruction cache and data access alignment checks.
+ * ---------------------------------------------------------------------
+ */
+ ldcopr r0, HSCTLR
+ ldr r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
+ orr r0, r0, r1
+ stcopr r0, HSCTLR
+ isb
+
+ /* ---------------------------------------------------------------------
+ * Zero-initialise the .bss section.
+ * ---------------------------------------------------------------------
+ */
+ ldr r0, =__BSS_START__
+ ldr r1, =__BSS_SIZE__
+ bl zeromem
+
+ /* ---------------------------------------------------------------------
+ * Allocate a stack whose memory will be marked as Normal
+ * Inner-Shareable, Write-Back, Write-Allocate memory when the MMU is
+ * enabled.
+ * There is no risk of reading stale stack memory after enabling the MMU
+ * as only the primary CPU is running at the moment.
+ * ---------------------------------------------------------------------
+ */
+ ldcopr r0, MPIDR
+ bl platform_set_stack
+
+ /* ---------------------------------------------------------------------
+ * Perform early platform setup.
+ * TODO: Investigate why tftf_plat_arch_setup() is not needed on
+ * AArch32, whereas it is on AArch64.
+ * ---------------------------------------------------------------------
+ */
+ bl tftf_early_platform_setup
+
+ /* ---------------------------------------------------------------------
+ * Jump to main function.
+ * ---------------------------------------------------------------------
+ */
+ bl ns_bl2u_main
+dead:
+ b dead
+endfunc ns_bl2u_entrypoint
diff --git a/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S b/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
new file mode 100644
index 00000000..902636e5
--- /dev/null
+++ b/fwu/ns_bl2u/aarch64/ns_bl2u_entrypoint.S
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <tftf.h>
+
+ .globl ns_bl2u_entrypoint
+
+func ns_bl2u_entrypoint
+ /* ---------------------------------------------------------------------
+ * Set the exception vectors.
+ * ---------------------------------------------------------------------
+ */
+ adr x0, exception_stubs
+ asm_write_vbar_el1_or_el2 x1
+
+ /* --------------------------------------------------------------------
+ * Enable the instruction cache, stack pointer and data access
+ * alignment checks.
+ * --------------------------------------------------------------------
+ */
+ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
+ asm_read_sctlr_el1_or_el2
+ orr x0, x0, x1
+ asm_write_sctlr_el1_or_el2 x1
+ isb
+
+ /* ---------------------------------------------------------------------
+ * Zero-initialise the .bss section.
+ * ---------------------------------------------------------------------
+ */
+ ldr x0, =__BSS_START__
+ ldr x1, =__BSS_SIZE__
+ bl zeromem16
+
+ /* ---------------------------------------------------------------------
+ * Allocate a stack whose memory will be marked as Normal
+ * Inner-Shareable, Write-Back, Write-Allocate memory when the MMU is
+ * enabled.
+ * There is no risk of reading stale stack memory after enabling the MMU
+ * as only the primary CPU is running at the moment.
+ * ---------------------------------------------------------------------
+ */
+ mrs x0, mpidr_el1
+ bl platform_set_stack
+
+ /* ---------------------------------------------------------------------
+ * Perform early platform setup & platforms specific early architectural
+ * setup, e.g. MMU setup.
+ * ----------------------------------------------------------------------
+ */
+ bl tftf_early_platform_setup
+ bl tftf_plat_arch_setup
+
+ /* ---------------------------------------------------------------------
+ * Jump to main function.
+ * ---------------------------------------------------------------------
+ */
+ bl ns_bl2u_main
+dead:
+ b dead
+endfunc ns_bl2u_entrypoint
diff --git a/fwu/ns_bl2u/ns_bl2u.ld.S b/fwu/ns_bl2u/ns_bl2u.ld.S
new file mode 100644
index 00000000..48af3036
--- /dev/null
+++ b/fwu/ns_bl2u/ns_bl2u.ld.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+#include <xlat_tables_defs.h>
+
+OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
+OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
+ENTRY(ns_bl2u_entrypoint)
+
+MEMORY {
+ RAM (rwx): ORIGIN = NS_BL2U_BASE, LENGTH = NS_BL2U_LIMIT - NS_BL2U_BASE
+}
+
+SECTIONS
+{
+ . = NS_BL2U_BASE;
+ ASSERT(. == ALIGN(PAGE_SIZE),
+ "NS_BL2U_BASE address is not aligned on a page boundary.")
+
+ ro . : {
+ __RO_START__ = .;
+ *ns_bl2u_entrypoint.o(.text*)
+ *(.text*)
+ *(.rodata*)
+ *(.vectors)
+ __RO_END_UNALIGNED__ = .;
+ /*
+ * Memory page(s) mapped to this section will be marked as
+ * read-only, executable. No RW data from the next section must
+ * creep in. Ensure the rest of the current memory page is unused.
+ */
+ . = ALIGN(PAGE_SIZE);
+ __RO_END__ = .;
+ } >RAM
+
+ .data . : {
+ __DATA_START__ = .;
+ *(.data*)
+ __DATA_END__ = .;
+ } >RAM
+
+ stacks (NOLOAD) : {
+ __STACKS_START__ = .;
+ *(ns_bl_normal_stacks)
+ __STACKS_END__ = .;
+ } >RAM
+
+ /*
+ * The .bss section gets initialised to 0 at runtime.
+ * Its base address must be 16-byte aligned.
+ */
+ .bss : ALIGN(16) {
+ __BSS_START__ = .;
+ *(SORT_BY_ALIGNMENT(.bss*))
+ *(COMMON)
+ __BSS_END__ = .;
+ } >RAM
+
+ /*
+ * The xlat_table section is for full, aligned page tables (4K).
+ * Removing them from .bss avoids forcing 4K alignment on
+ * the .bss section and eliminates the unecessary zero init
+ */
+ xlat_table (NOLOAD) : {
+ *(xlat_table)
+ } >RAM
+
+ __NS_BL2U_END__ = .;
+
+ __BSS_SIZE__ = SIZEOF(.bss);
+
+ ASSERT(. <= NS_BL2U_LIMIT, "NS_BL2U image has exceeded its limit.")
+}
diff --git a/fwu/ns_bl2u/ns_bl2u.mk b/fwu/ns_bl2u/ns_bl2u.mk
new file mode 100644
index 00000000..e4c93a1d
--- /dev/null
+++ b/fwu/ns_bl2u/ns_bl2u.mk
@@ -0,0 +1,75 @@
+#
+# Copyright (c) 2018, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include lib/xlat_tables_v2/xlat_tables.mk
+include lib/compiler-rt/compiler-rt.mk
+
+NS_BL2U_INCLUDES := \
+ -I${AUTOGEN_DIR} \
+ -Itftf/framework/include \
+ -Iinclude/common \
+ -Iinclude/common/${ARCH} \
+ -Iinclude/drivers \
+ -Iinclude/drivers/arm \
+ -Iinclude/drivers/io \
+ -Iinclude/lib \
+ -Iinclude/lib/${ARCH} \
+ -Iinclude/lib/stdlib \
+ -Iinclude/lib/stdlib/sys \
+ -Iinclude/lib/utils \
+ -Iinclude/lib/xlat_tables \
+ -Iinclude/plat/common \
+ -Iinclude/runtime_services
+
+# TODO: Remove dependency on TFTF files.
+NS_BL2U_SOURCES := $(addprefix tftf/framework/, \
+ ${ARCH}/arch.c \
+ ${ARCH}/asm_debug.S \
+ ${ARCH}/exceptions.S \
+ debug.c \
+)
+
+NS_BL2U_SOURCES += fwu/ns_bl2u/${ARCH}/ns_bl2u_entrypoint.S \
+ fwu/ns_bl2u/ns_bl2u_main.c \
+ lib/${ARCH}/cache_helpers.S \
+ lib/${ARCH}/exception_stubs.S \
+ lib/${ARCH}/misc_helpers.S \
+ lib/locks/${ARCH}/spinlock.S \
+ lib/smc/${ARCH}/asm_smc.S \
+ lib/smc/${ARCH}/smc.c \
+ ${STD_LIB_SOURCES} \
+ lib/utils/mp_printf.c \
+ lib/utils/uuid.c \
+ ${XLAT_TABLES_LIB_SRCS} \
+ plat/arm/common/arm_fwu_io_storage.c \
+ plat/common/${ARCH}/platform_helpers.S \
+ plat/common/${ARCH}/platform_up_stack.S \
+ plat/common/fwu_nvm_accessors.c \
+ plat/common/plat_common.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_fip.c
+
+NS_BL2U_SOURCES += ${COMPILER_RT_SRCS}
+
+NS_BL2U_LINKERFILE := fwu/ns_bl2u/ns_bl2u.ld.S
+
+# NS_BL2U requires accessing the flash. Force-enable it.
+NS_BL2U_DEFINES := -DUSE_NVM=1
+
+$(eval $(call add_define,NS_BL2U_DEFINES,ARM_ARCH_MAJOR))
+$(eval $(call add_define,NS_BL2U_DEFINES,ARM_ARCH_MINOR))
+$(eval $(call add_define,NS_BL2U_DEFINES,DEBUG))
+$(eval $(call add_define,NS_BL2U_DEFINES,ENABLE_ASSERTIONS))
+$(eval $(call add_define,NS_BL2U_DEFINES,FWU_BL_TEST))
+$(eval $(call add_define,NS_BL2U_DEFINES,LOG_LEVEL))
+$(eval $(call add_define,NS_BL2U_DEFINES,PLAT_${PLAT}))
+ifeq (${ARCH},aarch32)
+ $(eval $(call add_define,NS_BL2U_DEFINES,AARCH32))
+else
+ $(eval $(call add_define,NS_BL2U_DEFINES,AARCH64))
+endif
+
+ns_bl2u: ${AUTOGEN_DIR}/tests_list.h
diff --git a/fwu/ns_bl2u/ns_bl2u_main.c b/fwu/ns_bl2u/ns_bl2u_main.c
new file mode 100644
index 00000000..815859de
--- /dev/null
+++ b/fwu/ns_bl2u/ns_bl2u_main.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <debug.h>
+#include <firmware_image_package.h>
+#include <fwu_nvm.h>
+#include <platform.h>
+#include <platform_def.h>
+
+extern const char version_string[];
+
+void ns_bl2u_main(void)
+{
+ smc_args fwu_params = {0};
+ smc_ret_values fwu_result = {0};
+
+ NOTICE("NS_BL2U: %s\n", version_string);
+ NOTICE("NS_BL2U: %s\n", build_message);
+
+ tftf_platform_setup();
+
+#if FWU_BL_TEST
+ unsigned int toc_header;
+ STATUS status = fwu_nvm_read(0, &toc_header, 4);
+ if (status != STATUS_SUCCESS) {
+ ERROR("NS_BL2U: Failed to read NVM\n");
+ panic();
+ }
+
+ /* Update the TOC if found invalid. */
+ if (toc_header != TOC_HEADER_NAME) {
+ toc_header = TOC_HEADER_NAME;
+ status = fwu_nvm_write(0, &toc_header, 4);
+ if (status != STATUS_SUCCESS) {
+ ERROR("NS_BL2U: Failed to update TOC value\n");
+ panic();
+ }
+ INFO("NS_BL2U: Updated TOC value\n");
+ }
+#endif
+
+ /* Update the FIP image. */
+ if (fwu_update_fip(FIP_BKP_ADDRESS) != STATUS_SUCCESS) {
+ ERROR("NS_BL2U: Firmware Image Update Failed\n");
+ panic();
+ }
+
+ /* Call FWU_SMC_UPDATE_DONE to indicate image update done. */
+ INFO("NS_BL2U: Calling FWU_SMC_UPDATE_DONE\n");
+ fwu_params.arg0 = FWU_SMC_UPDATE_DONE;
+ fwu_result = tftf_smc(&fwu_params);
+ ERROR("NS_BL2U: Unexpected return from FWU process (%d)\n",
+ (int)fwu_result.ret0);
+ panic();
+}