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author | Marek Bykowski <marek.bykowski@gmail.com> | 2019-12-17 07:41:43 -0600 |
---|---|---|
committer | Marek Bykowski <marek.bykowski@gmail.com> | 2019-12-19 11:17:56 +0100 |
commit | d651444dbf8af93e21c4e205d6ada440d9c679ce (patch) | |
tree | 2741a66b24a4e5b681ed6bc860e552d9f88125a5 /drivers/arm | |
parent | 69a0bfc0abf7ca48ed425d260549822d1fe1b3bb (diff) | |
download | tf-a-tests-d651444dbf8af93e21c4e205d6ada440d9c679ce.tar.gz |
arm: gic: Don't assume the GIC base addresses are within 4G range.
There are systems out where the GIC registers (but not only) are
memory-mapped to addresses above the 4G range, eg. 0x80_0000_0000
to 0xFF_FFFF_FFFF. After following a flat (one to one) mapping a 32-bit
unsigned int isn't big enough for the 40-bit addresses. Change that to
uintptr_t.
Signed-off-by: Marek Bykowski <marek.bykowski@gmail.com>
Change-Id: Ida47495e9b2d6f4f93cbfc6eb2e497d449d6a208
Diffstat (limited to 'drivers/arm')
-rw-r--r-- | drivers/arm/gic/gic_common.c | 52 | ||||
-rw-r--r-- | drivers/arm/gic/gic_v3.c | 22 |
2 files changed, 37 insertions, 37 deletions
diff --git a/drivers/arm/gic/gic_common.c b/drivers/arm/gic/gic_common.c index d9c9fcee5..e16b21374 100644 --- a/drivers/arm/gic/gic_common.c +++ b/drivers/arm/gic/gic_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,49 +15,49 @@ * GIC Distributor interface accessors for reading entire registers ******************************************************************************/ -unsigned int gicd_read_isenabler(unsigned int base, unsigned int interrupt_id) +unsigned int gicd_read_isenabler(uintptr_t base, unsigned int interrupt_id) { unsigned int n = interrupt_id >> ISENABLER_SHIFT; return mmio_read_32(base + GICD_ISENABLER + (n << 2)); } -unsigned int gicd_read_icenabler(unsigned int base, unsigned int interrupt_id) +unsigned int gicd_read_icenabler(uintptr_t base, unsigned int interrupt_id) { unsigned int n = interrupt_id >> ICENABLER_SHIFT; return mmio_read_32(base + GICD_ICENABLER + (n << 2)); } -unsigned int gicd_read_ispendr(unsigned int base, unsigned int interrupt_id) +unsigned int gicd_read_ispendr(uintptr_t base, unsigned int interrupt_id) { unsigned int n = interrupt_id >> ISPENDR_SHIFT; return mmio_read_32(base + GICD_ISPENDR + (n << 2)); } -unsigned int gicd_read_icpendr(unsigned int base, unsigned int interrupt_id) +unsigned int gicd_read_icpendr(uintptr_t base, unsigned int interrupt_id) { unsigned int n = interrupt_id >> ICPENDR_SHIFT; return mmio_read_32(base + GICD_ICPENDR + (n << 2)); } -unsigned int gicd_read_isactiver(unsigned int base, unsigned int interrupt_id) +unsigned int gicd_read_isactiver(uintptr_t base, unsigned int interrupt_id) { unsigned int n = interrupt_id >> ISACTIVER_SHIFT; return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); } -unsigned int gicd_read_icactiver(unsigned int base, unsigned int interrupt_id) +unsigned int gicd_read_icactiver(uintptr_t base, unsigned int interrupt_id) { unsigned int n = interrupt_id >> ICACTIVER_SHIFT; return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); } -unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int interrupt_id) +unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int interrupt_id) { unsigned int n = interrupt_id >> IPRIORITYR_SHIFT; return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); } -unsigned int gicd_read_icfgr(unsigned int base, unsigned int interrupt_id) +unsigned int gicd_read_icfgr(uintptr_t base, unsigned int interrupt_id) { unsigned int n = interrupt_id >> ICFGR_SHIFT; return mmio_read_32(base + GICD_ICFGR + (n << 2)); @@ -67,56 +67,56 @@ unsigned int gicd_read_icfgr(unsigned int base, unsigned int interrupt_id) * GIC Distributor interface accessors for writing entire registers ******************************************************************************/ -void gicd_write_isenabler(unsigned int base, +void gicd_write_isenabler(uintptr_t base, unsigned int interrupt_id, unsigned int val) { unsigned int n = interrupt_id >> ISENABLER_SHIFT; mmio_write_32(base + GICD_ISENABLER + (n << 2), val); } -void gicd_write_icenabler(unsigned int base, +void gicd_write_icenabler(uintptr_t base, unsigned int interrupt_id, unsigned int val) { unsigned int n = interrupt_id >> ICENABLER_SHIFT; mmio_write_32(base + GICD_ICENABLER + (n << 2), val); } -void gicd_write_ispendr(unsigned int base, +void gicd_write_ispendr(uintptr_t base, unsigned int interrupt_id, unsigned int val) { unsigned int n = interrupt_id >> ISPENDR_SHIFT; mmio_write_32(base + GICD_ISPENDR + (n << 2), val); } -void gicd_write_icpendr(unsigned int base, +void gicd_write_icpendr(uintptr_t base, unsigned int interrupt_id, unsigned int val) { unsigned int n = interrupt_id >> ICPENDR_SHIFT; mmio_write_32(base + GICD_ICPENDR + (n << 2), val); } -void gicd_write_isactiver(unsigned int base, +void gicd_write_isactiver(uintptr_t base, unsigned int interrupt_id, unsigned int val) { unsigned int n = interrupt_id >> ISACTIVER_SHIFT; mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); } -void gicd_write_icactiver(unsigned int base, +void gicd_write_icactiver(uintptr_t base, unsigned int interrupt_id, unsigned int val) { unsigned int n = interrupt_id >> ICACTIVER_SHIFT; mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); } -void gicd_write_ipriorityr(unsigned int base, +void gicd_write_ipriorityr(uintptr_t base, unsigned int interrupt_id, unsigned int val) { unsigned int n = interrupt_id >> IPRIORITYR_SHIFT; mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); } -void gicd_write_icfgr(unsigned int base, +void gicd_write_icfgr(uintptr_t base, unsigned int interrupt_id, unsigned int val) { unsigned int n = interrupt_id >> ICFGR_SHIFT; @@ -126,61 +126,61 @@ void gicd_write_icfgr(unsigned int base, /******************************************************************************* * GIC Distributor interface accessors for individual interrupt manipulation ******************************************************************************/ -unsigned int gicd_get_isenabler(unsigned int base, unsigned int interrupt_id) +unsigned int gicd_get_isenabler(uintptr_t base, unsigned int interrupt_id) { unsigned int bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1); return gicd_read_isenabler(base, interrupt_id) & (1 << bit_num); } -void gicd_set_isenabler(unsigned int base, unsigned int interrupt_id) +void gicd_set_isenabler(uintptr_t base, unsigned int interrupt_id) { unsigned int bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1); gicd_write_isenabler(base, interrupt_id, (1 << bit_num)); } -void gicd_set_icenabler(unsigned int base, unsigned int interrupt_id) +void gicd_set_icenabler(uintptr_t base, unsigned int interrupt_id) { unsigned int bit_num = interrupt_id & ((1 << ICENABLER_SHIFT) - 1); gicd_write_icenabler(base, interrupt_id, (1 << bit_num)); } -void gicd_set_ispendr(unsigned int base, unsigned int interrupt_id) +void gicd_set_ispendr(uintptr_t base, unsigned int interrupt_id) { unsigned int bit_num = interrupt_id & ((1 << ISPENDR_SHIFT) - 1); gicd_write_ispendr(base, interrupt_id, (1 << bit_num)); } -void gicd_set_icpendr(unsigned int base, unsigned int interrupt_id) +void gicd_set_icpendr(uintptr_t base, unsigned int interrupt_id) { unsigned int bit_num = interrupt_id & ((1 << ICPENDR_SHIFT) - 1); gicd_write_icpendr(base, interrupt_id, (1 << bit_num)); } -void gicd_set_isactiver(unsigned int base, unsigned int interrupt_id) +void gicd_set_isactiver(uintptr_t base, unsigned int interrupt_id) { unsigned int bit_num = interrupt_id & ((1 << ISACTIVER_SHIFT) - 1); gicd_write_isactiver(base, interrupt_id, (1 << bit_num)); } -void gicd_set_icactiver(unsigned int base, unsigned int interrupt_id) +void gicd_set_icactiver(uintptr_t base, unsigned int interrupt_id) { unsigned int bit_num = interrupt_id & ((1 << ICACTIVER_SHIFT) - 1); gicd_write_icactiver(base, interrupt_id, (1 << bit_num)); } -unsigned int gicd_get_ipriorityr(unsigned int base, unsigned int interrupt_id) +unsigned int gicd_get_ipriorityr(uintptr_t base, unsigned int interrupt_id) { return gicd_read_ipriorityr(base, interrupt_id) & GIC_PRI_MASK; } -void gicd_set_ipriorityr(unsigned int base, unsigned int interrupt_id, +void gicd_set_ipriorityr(uintptr_t base, unsigned int interrupt_id, unsigned int priority) { mmio_write_8(base + GICD_IPRIORITYR + interrupt_id, diff --git a/drivers/arm/gic/gic_v3.c b/drivers/arm/gic/gic_v3.c index 5a777cb3d..ea6615945 100644 --- a/drivers/arm/gic/gic_v3.c +++ b/drivers/arm/gic/gic_v3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -57,7 +57,7 @@ static unsigned long long mpidr_list[PLATFORM_CORE_COUNT] = {UINT64_MAX}; /****************************************************************************** * GIC Distributor interface accessors for writing entire registers *****************************************************************************/ -static void gicd_write_irouter(unsigned int base, +static void gicd_write_irouter(uintptr_t base, unsigned int interrupt_id, unsigned long long route) { @@ -68,17 +68,17 @@ static void gicd_write_irouter(unsigned int base, /****************************************************************************** * GIC Re-distributor interface accessors for writing entire registers *****************************************************************************/ -static void gicr_write_isenabler0(unsigned int base, unsigned int val) +static void gicr_write_isenabler0(uintptr_t base, unsigned int val) { mmio_write_32(base + GICR_ISENABLER0, val); } -static void gicr_write_icenabler0(unsigned int base, unsigned int val) +static void gicr_write_icenabler0(uintptr_t base, unsigned int val) { mmio_write_32(base + GICR_ICENABLER0, val); } -static void gicr_write_icpendr0(unsigned int base, unsigned int val) +static void gicr_write_icpendr0(uintptr_t base, unsigned int val) { mmio_write_32(base + GICR_ICPENDR0, val); } @@ -107,7 +107,7 @@ static unsigned int gicr_read_icfgr1(uintptr_t base) return mmio_read_32(base + GICR_ICFGR1); } -static unsigned int gicr_read_isenabler0(unsigned int base) +static unsigned int gicr_read_isenabler0(uintptr_t base) { return mmio_read_32(base + GICR_ISENABLER0); } @@ -118,7 +118,7 @@ static unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id) return mmio_read_32(base + GICR_IPRIORITYR + (n << 2)); } -static unsigned int gicr_read_ispendr0(unsigned int base) +static unsigned int gicr_read_ispendr0(uintptr_t base) { return mmio_read_32(base + GICR_ISPENDR0); } @@ -127,26 +127,26 @@ static unsigned int gicr_read_ispendr0(unsigned int base) * GIC Re-distributor interface accessors for individual interrupt * manipulation *****************************************************************************/ -static unsigned int gicr_get_isenabler0(unsigned int base, +static unsigned int gicr_get_isenabler0(uintptr_t base, unsigned int interrupt_id) { unsigned bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1); return gicr_read_isenabler0(base) & (1 << bit_num); } -static void gicr_set_isenabler0(unsigned int base, unsigned int interrupt_id) +static void gicr_set_isenabler0(uintptr_t base, unsigned int interrupt_id) { unsigned bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1); gicr_write_isenabler0(base, (1 << bit_num)); } -static void gicr_set_icenabler0(unsigned int base, unsigned int interrupt_id) +static void gicr_set_icenabler0(uintptr_t base, unsigned int interrupt_id) { unsigned bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1); gicr_write_icenabler0(base, (1 << bit_num)); } -static void gicr_set_icpendr0(unsigned int base, unsigned int interrupt_id) +static void gicr_set_icpendr0(uintptr_t base, unsigned int interrupt_id) { unsigned bit_num = interrupt_id & ((1 << ICPENDR_SHIFT) - 1); gicr_write_icpendr0(base, (1 << bit_num)); |