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authorVarun Wadekar <vwadekar@nvidia.com>2020-03-20 22:41:32 -0700
committerVarun Wadekar <vwadekar@nvidia.com>2020-06-08 16:36:27 -0700
commitfa6a2d27307698dadc19bf6665eae1378d3dd8b5 (patch)
tree7e8d2d9905620cb926108f02f28766684add05d9
parent35106bd23a43797cd3ea74994498dc6cc1ceb812 (diff)
downloadtf-a-tests-fa6a2d27307698dadc19bf6665eae1378d3dd8b5.tar.gz
Tegra194: create dummy SMMU context for system resume
This patch creates a dummy SMMU context and saves the base address to a pre-negotiated scratch register for the System Resume Firmware to restore. This allows the System Resume Firmware to complete without any errors or warnings. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ic596e6775c6b78ac051ccff02e9574186d6f5335
-rw-r--r--plat/nvidia/tegra194/include/platform_def.h6
-rw-r--r--plat/nvidia/tegra194/pwr_mgmt.c22
-rw-r--r--plat/nvidia/tegra194/setup.c4
3 files changed, 25 insertions, 7 deletions
diff --git a/plat/nvidia/tegra194/include/platform_def.h b/plat/nvidia/tegra194/include/platform_def.h
index 1c9fff7..501b596 100644
--- a/plat/nvidia/tegra194/include/platform_def.h
+++ b/plat/nvidia/tegra194/include/platform_def.h
@@ -149,6 +149,12 @@
#define SYS_CNT_BASE1 TEGRA194_TMRUS_BASE
#define TEGRA194_AOWAKE_BASE U(0x0C370000)
#define TEGRA194_SCRATCH_BASE U(0x0C390000)
+#define TEGRA194_SMMU0_BASE U(0x12000000)
+
+/*******************************************************************************
+ * DRAM carveout to save the SMMU context
+ ******************************************************************************/
+#define TEGRA194_SMMU_CTX_BASE (DRAM_END - 0x1000)
#ifndef __ASSEMBLY__
diff --git a/plat/nvidia/tegra194/pwr_mgmt.c b/plat/nvidia/tegra194/pwr_mgmt.c
index 0ba2e55..2f43f0b 100644
--- a/plat/nvidia/tegra194/pwr_mgmt.c
+++ b/plat/nvidia/tegra194/pwr_mgmt.c
@@ -5,6 +5,7 @@
*/
#include <arch.h>
+#include <arch_helpers.h>
#include <debug.h>
#include <mmio.h>
#include <platform.h>
@@ -13,11 +14,6 @@
#include <utils_def.h>
/*******************************************************************************
- * Memory Controller SMMU Bypass config register
- ******************************************************************************/
-#define MC_SMMU_BYPASS_CONFIG U(0x1820)
-
-/*******************************************************************************
* Secure Scratch 73 to save base address of SMMU register context
******************************************************************************/
#define SCRATCH_SECURE_RSV73_SCRATCH U(0x2ac)
@@ -29,7 +25,7 @@ typedef struct mc_regs {
#define mc_smmu_bypass_cfg \
{ \
- .reg = TEGRA194_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
+ .reg = TEGRA194_SMMU0_BASE, \
.val = 0x00000000U, \
}
@@ -56,10 +52,22 @@ static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = {
void tegra194_pwr_mgmt_setup(void)
{
+ uintptr_t smmu_ctx_base = (uintptr_t)TEGRA194_SMMU_CTX_BASE;
+
/* index of END_OF_TABLE */
tegra194_mc_context[0].val = ARRAY_SIZE(tegra194_mc_context) - 1U;
+ /* prepare dummy context */
+ for (int i = 1; i < ARRAY_SIZE(tegra194_mc_context) - 1U; i++) {
+ tegra194_mc_context[i].val = mmio_read_32(tegra194_mc_context[i].reg);
+ }
+
+ /* save context for the SC7-RF */
+ memcpy((void *)smmu_ctx_base, (void *)tegra194_mc_context,
+ sizeof(tegra194_mc_context));
+ flush_dcache_range(smmu_ctx_base, sizeof(tegra194_mc_context));
+
/* save SMMU context for SC7-RF to restore */
mmio_write_32(TEGRA194_SCRATCH_BASE + SCRATCH_SECURE_RSV73_SCRATCH,
- ((uintptr_t)tegra194_mc_context) >> 12);
+ smmu_ctx_base >> 12);
}
diff --git a/plat/nvidia/tegra194/setup.c b/plat/nvidia/tegra194/setup.c
index a9d7843..a02a2d8 100644
--- a/plat/nvidia/tegra194/setup.c
+++ b/plat/nvidia/tegra194/setup.c
@@ -40,8 +40,12 @@ static const mmap_region_t tegra194_mmap[] = {
MT_DEVICE | MT_RW | MT_NS),
MAP_REGION_FLAT(TEGRA194_SCRATCH_BASE, 0x1000, /* 4KB */
MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(TEGRA194_SMMU0_BASE, 0x1000, /* 4KB */
+ MT_DEVICE | MT_RW | MT_NS),
MAP_REGION_FLAT(DRAM_BASE + TFTF_NVM_OFFSET, TFTF_NVM_SIZE,
MT_MEMORY | MT_RW | MT_NS),
+ MAP_REGION_FLAT(TEGRA194_SMMU_CTX_BASE, 0x1000, /* 4KB */
+ MT_MEMORY | MT_RW | MT_NS),
{0}
};