diff options
author | Federico Recanati <federico.recanati@arm.com> | 2022-01-14 15:44:45 +0100 |
---|---|---|
committer | Federico Recanati <federico.recanati@arm.com> | 2022-03-25 10:54:00 +0100 |
commit | d3749b08d49a6cb4fd69e66da1e405dbbd3de57f (patch) | |
tree | ba6fa7fa5bbf622dd54281668f885ceaa9091f53 | |
parent | 0091af97592d9cd036a4b70433b70ac9c0ed22b0 (diff) | |
download | tf-a-tests-d3749b08d49a6cb4fd69e66da1e405dbbd3de57f.tar.gz |
fix(plat/arm/fvp): make address space configurable
Make FVP physical/virtual address space sizes configurable, with
default at 34-bit (previously hard-coded value).
Maximum tested value is 48-bit, FVP interconnect doesn't yet support
52-bit PA.
Increase MAX_XLAT_TABLE and consequently NS_BL1U_RW_SIZE and
NS_BLU2_LIMIT to accommodate the increased translation tables (based
on 48-bit max PA size).
Custom PA size is passed to build system through the PA_SIZE define.
FVP needs to be configured in a compatible way through the parameters:
* cluster0.PA_SIZE, for each cluster;
* bp.dram_size, setting a memory limit corresponding at least to
PA_SIZE;
* cci550.addr_width, interconnect address width should match PA_SIZE;
* pci.pci_smmuv3.mmu.SMMU_IDR5, SMMU has to be configured as well if
present.
Change-Id: I57bc898fb2c9696c01fc8e20d00b4a3d09e22326
Signed-off-by: Federico Recanati <federico.recanati@arm.com>
-rw-r--r-- | include/common/test_helpers.h | 12 | ||||
-rw-r--r-- | include/lib/aarch64/arch_features.h | 6 | ||||
-rw-r--r-- | lib/xlat_tables_v2/aarch64/xlat_tables_arch.c | 3 | ||||
-rw-r--r-- | plat/arm/fvp/include/platform_def.h | 10 | ||||
-rw-r--r-- | plat/arm/fvp/platform.mk | 9 |
5 files changed, 33 insertions, 7 deletions
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h index c628ee821..78f1c5808 100644 --- a/include/common/test_helpers.h +++ b/include/common/test_helpers.h @@ -290,6 +290,18 @@ typedef test_result_t (*test_function_arg_t)(void *arg); } \ } while (false) +#define SKIP_TEST_IF_PA_SIZE_LESS_THAN(n) \ + do { \ + static const unsigned int pa_range_bits_arr[] = { \ + PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011,\ + PARANGE_0100, PARANGE_0101, PARANGE_0110 \ + }; \ + if (pa_range_bits_arr[get_pa_range()] < n) { \ + tftf_testcase_printf("PA size less than %d bit\n", n); \ + return TEST_RESULT_SKIPPED; \ + } \ + } while (false) + /* Helper macro to verify if system suspend API is supported */ #define is_psci_sys_susp_supported() \ (tftf_get_psci_feature_info(SMC_PSCI_SYSTEM_SUSPEND) \ diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h index b0ec17a88..4da640750 100644 --- a/include/lib/aarch64/arch_features.h +++ b/include/lib/aarch64/arch_features.h @@ -98,6 +98,12 @@ static inline unsigned long int get_armv8_6_ecv_support(void) ID_AA64MMFR0_EL1_ECV_MASK); } +static inline unsigned long int get_pa_range(void) +{ + return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_PARANGE_SHIFT) & + ID_AA64MMFR0_EL1_PARANGE_MASK); +} + static inline uint32_t arch_get_debug_version(void) { return ((read_id_aa64dfr0_el1() & ID_AA64DFR0_DEBUG_BITS) >> diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c index 037dbf81c..ced9b3695 100644 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c @@ -91,8 +91,7 @@ static const unsigned int pa_range_bits_arr[] = { unsigned long long xlat_arch_get_max_supported_pa(void) { - u_register_t pa_range = read_id_aa64mmfr0_el1() & - ID_AA64MMFR0_EL1_PARANGE_MASK; + u_register_t pa_range = get_pa_range(); /* All other values are reserved */ assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); diff --git a/plat/arm/fvp/include/platform_def.h b/plat/arm/fvp/include/platform_def.h index 8555c1f37..fffacfc6d 100644 --- a/plat/arm/fvp/include/platform_def.h +++ b/plat/arm/fvp/include/platform_def.h @@ -137,7 +137,7 @@ * calculated using the current NS_BL1U RW debug size plus a little space * for growth. ******************************************************************************/ -#define NS_BL1U_RW_SIZE (0x7000) +#define NS_BL1U_RW_SIZE (0x9000) #define NS_BL1U_RW_BASE (NSRAM_BASE) #define NS_BL1U_RW_LIMIT (NS_BL1U_RW_BASE + NS_BL1U_RW_SIZE) @@ -153,7 +153,7 @@ * Base address and limit for NS_BL2U image. ******************************************************************************/ #define NS_BL2U_BASE DRAM_BASE -#define NS_BL2U_LIMIT (NS_BL2U_BASE + 0x4D000) +#define NS_BL2U_LIMIT (NS_BL2U_BASE + 0x4E000) /****************************************************************************** * Memory mapped Generic timer interfaces @@ -239,8 +239,8 @@ * Platform specific page table and MMU setup constants ******************************************************************************/ #ifdef __aarch64__ -#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 34) -#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 34) +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << PA_SIZE) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << PA_SIZE) #else #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) @@ -252,7 +252,7 @@ #define MAX_MMAP_REGIONS 50 #else #if IMAGE_CACTUS -#define MAX_XLAT_TABLES 6 +#define MAX_XLAT_TABLES 8 #else #define MAX_XLAT_TABLES 5 #endif diff --git a/plat/arm/fvp/platform.mk b/plat/arm/fvp/platform.mk index c9bbe6e55..e467cd681 100644 --- a/plat/arm/fvp/platform.mk +++ b/plat/arm/fvp/platform.mk @@ -80,6 +80,15 @@ $(eval $(call add_define,TFTF_DEFINES,FVP_CLUSTER_COUNT)) $(eval $(call add_define,TFTF_DEFINES,FVP_MAX_CPUS_PER_CLUSTER)) $(eval $(call add_define,TFTF_DEFINES,FVP_MAX_PE_PER_CPU)) +# Default PA size for FVP platform +PA_SIZE := 34 + +$(eval $(call add_define,CACTUS_DEFINES,PA_SIZE)) +$(eval $(call add_define,IVY_DEFINES,PA_SIZE)) +$(eval $(call add_define,NS_BL1U_DEFINES,PA_SIZE)) +$(eval $(call add_define,NS_BL2U_DEFINES,PA_SIZE)) +$(eval $(call add_define,TFTF_DEFINES,PA_SIZE)) + PLAT_INCLUDES += -Iplat/arm/fvp/include/ PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \ |