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author | Jimmy Brisson <jimmy.brisson@arm.com> | 2020-04-16 10:54:59 -0500 |
---|---|---|
committer | Jimmy Brisson <jimmy.brisson@arm.com> | 2020-06-03 13:30:29 -0500 |
commit | 945095ad9a97bc9469ca095f8dd057a4021297dd (patch) | |
tree | b0ef7e031939a3c397f5a4ab05cda9ff3bbc438f | |
parent | 90f1d5caed95873e02071ef040191de52ee84a52 (diff) | |
download | tf-a-tests-945095ad9a97bc9469ca095f8dd057a4021297dd.tar.gz |
Test that TF-A supports ARMv8.6-ECV
Note: This test will cause an unhandled exception in the case that TF-A
is not doing its job and enabling ARMv8.6-ECV Self-Synch when the hardware
supports it.
Change-Id: Iee19963f31fa47b0010e77d7b56b05b71ec1b507
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
-rw-r--r-- | include/common/test_helpers.h | 9 | ||||
-rw-r--r-- | include/lib/aarch64/arch.h | 11 | ||||
-rw-r--r-- | include/lib/aarch64/arch_features.h | 6 | ||||
-rw-r--r-- | include/lib/aarch64/arch_helpers.h | 3 | ||||
-rw-r--r-- | tftf/tests/extensions/ecv/test_ecv.c | 27 | ||||
-rw-r--r-- | tftf/tests/tests-cpu-extensions.mk | 1 | ||||
-rw-r--r-- | tftf/tests/tests-cpu-extensions.xml | 1 |
7 files changed, 58 insertions, 0 deletions
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h index 278c01e2e..33fce5375 100644 --- a/include/common/test_helpers.h +++ b/include/common/test_helpers.h @@ -106,6 +106,15 @@ typedef test_result_t (*test_function_arg_t)(void *arg); } \ } while (0) +#define SKIP_TEST_IF_ECV_NOT_SELF_SYNC() \ + do { \ + if (get_armv8_6_ecv_support() != \ + ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { \ + tftf_testcase_printf("ARMv8.6-ECV not supported\n"); \ + return TEST_RESULT_SKIPPED; \ + } \ + } while (0) + #define SKIP_TEST_IF_MM_NOT_PRESENT() \ do { \ smc_args version_smc = { MM_VERSION_AARCH32 }; \ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 7dc971f18..718964e58 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -194,6 +194,12 @@ #define PARANGE_0101 U(48) #define PARANGE_0110 U(52) +#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) +#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) +#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) +#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) +#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) + #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) @@ -935,5 +941,10 @@ #define HDFGRTR_EL2 S3_4_C3_C1_4 #define HDFGWTR_EL2 S3_4_C3_C1_5 +/******************************************************************************* + * Armv8.6 - Enhanced Counter Virtualization Registers + ******************************************************************************/ +#define CNTPOFF_EL2 S3_4_C14_C0_6 + #endif /* ARCH_H */ diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h index 3ee382468..fc9e8d439 100644 --- a/include/lib/aarch64/arch_features.h +++ b/include/lib/aarch64/arch_features.h @@ -74,6 +74,12 @@ static inline bool is_armv8_6_fgt_present(void) ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT_SUPPORTED; } +static inline unsigned long int get_armv8_6_ecv_support(void) +{ + return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) & + ID_AA64MMFR0_EL1_ECV_MASK); +} + static inline uint32_t arch_get_debug_version(void) { return ((read_id_aa64dfr0_el1() & ID_AA64DFR0_DEBUG_BITS) >> diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index a6a1de345..9bcd0bbdf 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -482,6 +482,9 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2) DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2) DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2) +/* Armv8.6 Enhanced Counter Virtualization Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2) + #define IS_IN_EL(x) \ (GET_EL(read_CurrentEl()) == MODE_EL##x) diff --git a/tftf/tests/extensions/ecv/test_ecv.c b/tftf/tests/extensions/ecv/test_ecv.c new file mode 100644 index 000000000..463353b6e --- /dev/null +++ b/tftf/tests/extensions/ecv/test_ecv.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <test_helpers.h> +#include <tftf.h> +#include <tftf_lib.h> +#include <string.h> + +/* + * TF-A is expected to allow access to CNTPOFF_EL2 register from EL2. + * Reading this register will trap to EL3 and crash when TF-A has not + * allowed access. + */ +test_result_t test_ecv_enabled(void) +{ + SKIP_TEST_IF_AARCH32(); + +#ifdef __aarch64__ + SKIP_TEST_IF_ECV_NOT_SELF_SYNC(); + read_cntpoff_el2(); + + return TEST_RESULT_SUCCESS; +#endif /* __aarch64__ */ +} diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk index c57390052..fedf7837d 100644 --- a/tftf/tests/tests-cpu-extensions.mk +++ b/tftf/tests/tests-cpu-extensions.mk @@ -10,6 +10,7 @@ TESTS_SOURCES += $(addprefix tftf/tests/, \ extensions/sve/sve_operations.S \ extensions/sve/test_sve.c \ extensions/fgt/test_fgt.c \ + extensions/ecv/test_ecv.c \ runtime_services/arm_arch_svc/smccc_arch_workaround_1.c \ runtime_services/arm_arch_svc/smccc_arch_workaround_2.c \ runtime_services/arm_arch_svc/smccc_arch_soc_id.c \ diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml index 8b06b5755..08a65c7fc 100644 --- a/tftf/tests/tests-cpu-extensions.xml +++ b/tftf/tests/tests-cpu-extensions.xml @@ -19,6 +19,7 @@ <testcase name="Use MTE Instructions" function="test_mte_instructions" /> <testcase name="Check for MTE register leakage" function="test_mte_leakage" /> <testcase name="Use FGT Registers" function="test_fgt_enabled" /> + <testcase name="Use ECV Registers" function="test_ecv_enabled" /> </testsuite> <testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests"> |