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authorManish Pandey <manish.pandey2@arm.com>2020-06-03 20:46:29 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2020-06-03 20:46:29 +0000
commit9060e3e68241a3fc1ad8588c20a97218c34c6c68 (patch)
tree1ef0aaf51b7a762d72ccf11a35f5b08764ca1c69
parent0825704538540fa183851de902f83f7e22f69f0f (diff)
parent945095ad9a97bc9469ca095f8dd057a4021297dd (diff)
downloadtf-a-tests-9060e3e68241a3fc1ad8588c20a97218c34c6c68.tar.gz
Merge changes from topic "jb/8.6-features"
* changes: Test that TF-A supports ARMv8.6-ECV Test that TF-A supports ARMv8.6-FGT
-rw-r--r--include/common/test_helpers.h18
-rw-r--r--include/lib/aarch64/arch.h28
-rw-r--r--include/lib/aarch64/arch_features.h14
-rw-r--r--include/lib/aarch64/arch_helpers.h12
-rw-r--r--tftf/tests/extensions/ecv/test_ecv.c27
-rw-r--r--tftf/tests/extensions/fgt/test_fgt.c32
-rw-r--r--tftf/tests/tests-cpu-extensions.mk2
-rw-r--r--tftf/tests/tests-cpu-extensions.xml2
8 files changed, 132 insertions, 3 deletions
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index e9e0b7b..33fce53 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -97,6 +97,24 @@ typedef test_result_t (*test_function_arg_t)(void *arg);
} \
} while (0)
+#define SKIP_TEST_IF_FGT_NOT_SUPPORTED() \
+ do { \
+ if (!is_armv8_6_fgt_present()) { \
+ tftf_testcase_printf( \
+ "Fine Grained Traps not supported\n"); \
+ return TEST_RESULT_SKIPPED; \
+ } \
+ } while (0)
+
+#define SKIP_TEST_IF_ECV_NOT_SELF_SYNC() \
+ do { \
+ if (get_armv8_6_ecv_support() != \
+ ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { \
+ tftf_testcase_printf("ARMv8.6-ECV not supported\n"); \
+ return TEST_RESULT_SKIPPED; \
+ } \
+ } while (0)
+
#define SKIP_TEST_IF_MM_NOT_PRESENT() \
do { \
smc_args version_smc = { MM_VERSION_AARCH32 }; \
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 4e9c03b..718964e 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -194,6 +194,17 @@
#define PARANGE_0101 U(48)
#define PARANGE_0110 U(52)
+#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
+#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
+#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
+#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
+#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
+
+#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
+#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
+#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
+#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
+
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
@@ -921,4 +932,19 @@
#define RGSR_EL1 S3_0_C1_C0_5
#define GCR_EL1 S3_0_C1_C0_6
+/*******************************************************************************
+ * Armv8.6 - Fine Grained Virtualization Traps Registers
+ ******************************************************************************/
+#define HFGRTR_EL2 S3_4_C1_C1_4
+#define HFGWTR_EL2 S3_4_C1_C1_5
+#define HFGITR_EL2 S3_4_C1_C1_6
+#define HDFGRTR_EL2 S3_4_C3_C1_4
+#define HDFGWTR_EL2 S3_4_C3_C1_5
+
+/*******************************************************************************
+ * Armv8.6 - Enhanced Counter Virtualization Registers
+ ******************************************************************************/
+#define CNTPOFF_EL2 S3_4_C14_C0_6
+
+
#endif /* ARCH_H */
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index 20433fd..fc9e8d4 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -68,6 +68,18 @@ static inline unsigned int get_armv8_5_mte_support(void)
ID_AA64PFR1_EL1_MTE_MASK);
}
+static inline bool is_armv8_6_fgt_present(void)
+{
+ return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
+ ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT_SUPPORTED;
+}
+
+static inline unsigned long int get_armv8_6_ecv_support(void)
+{
+ return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) &
+ ID_AA64MMFR0_EL1_ECV_MASK);
+}
+
static inline uint32_t arch_get_debug_version(void)
{
return ((read_id_aa64dfr0_el1() & ID_AA64DFR0_DEBUG_BITS) >>
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index d16960a..9bcd0bb 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -475,6 +475,16 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
+/* Armv8.6 Fine Grained Virtualization Traps Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2)
+
+/* Armv8.6 Enhanced Counter Virtualization Register */
+DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2)
+
#define IS_IN_EL(x) \
(GET_EL(read_CurrentEl()) == MODE_EL##x)
diff --git a/tftf/tests/extensions/ecv/test_ecv.c b/tftf/tests/extensions/ecv/test_ecv.c
new file mode 100644
index 0000000..463353b
--- /dev/null
+++ b/tftf/tests/extensions/ecv/test_ecv.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <test_helpers.h>
+#include <tftf.h>
+#include <tftf_lib.h>
+#include <string.h>
+
+/*
+ * TF-A is expected to allow access to CNTPOFF_EL2 register from EL2.
+ * Reading this register will trap to EL3 and crash when TF-A has not
+ * allowed access.
+ */
+test_result_t test_ecv_enabled(void)
+{
+ SKIP_TEST_IF_AARCH32();
+
+#ifdef __aarch64__
+ SKIP_TEST_IF_ECV_NOT_SELF_SYNC();
+ read_cntpoff_el2();
+
+ return TEST_RESULT_SUCCESS;
+#endif /* __aarch64__ */
+}
diff --git a/tftf/tests/extensions/fgt/test_fgt.c b/tftf/tests/extensions/fgt/test_fgt.c
new file mode 100644
index 0000000..6213d4b
--- /dev/null
+++ b/tftf/tests/extensions/fgt/test_fgt.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <test_helpers.h>
+#include <tftf_lib.h>
+#include <tftf.h>
+#include <string.h>
+#include <arch_helpers.h>
+
+/*
+ * TF-A is expected to allow access to ARMv8.6-FGT system registers from EL2.
+ * Reading these registers causes a trap to EL3 and crash when TF-A has not
+ * allowed access.
+ */
+test_result_t test_fgt_enabled(void)
+{
+ SKIP_TEST_IF_AARCH32();
+
+#ifdef __aarch64__
+ SKIP_TEST_IF_FGT_NOT_SUPPORTED();
+ read_hfgrtr_el2();
+ read_hfgwtr_el2();
+ read_hfgitr_el2();
+ read_hdfgrtr_el2();
+ read_hdfgwtr_el2();
+
+ return TEST_RESULT_SUCCESS;
+#endif /* __aarch64__ */
+}
diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk
index 1b7743e..fedf783 100644
--- a/tftf/tests/tests-cpu-extensions.mk
+++ b/tftf/tests/tests-cpu-extensions.mk
@@ -9,6 +9,8 @@ TESTS_SOURCES += $(addprefix tftf/tests/, \
extensions/mte/test_mte.c \
extensions/sve/sve_operations.S \
extensions/sve/test_sve.c \
+ extensions/fgt/test_fgt.c \
+ extensions/ecv/test_ecv.c \
runtime_services/arm_arch_svc/smccc_arch_workaround_1.c \
runtime_services/arm_arch_svc/smccc_arch_workaround_2.c \
runtime_services/arm_arch_svc/smccc_arch_soc_id.c \
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index aff6b61..08a65c7 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -18,6 +18,8 @@
<testcase name="Check for Pointer Authentication key leakage from TSP" function="test_pauth_leakage_tsp" />
<testcase name="Use MTE Instructions" function="test_mte_instructions" />
<testcase name="Check for MTE register leakage" function="test_mte_leakage" />
+ <testcase name="Use FGT Registers" function="test_fgt_enabled" />
+ <testcase name="Use ECV Registers" function="test_ecv_enabled" />
</testsuite>
<testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">