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authorDavid Horstmann <david.horstmann@arm.com>2020-11-09 11:42:31 +0000
committerDavid Horstmann <david.horstmann@arm.com>2020-11-09 16:24:11 +0000
commit85c39c56326ecd9a9e5f4ddefe8ec378fdedeb1c (patch)
tree677aa02949c48b3777a914f66147a72ee81c8bed
parent5786b00f3457f1cebad04347cbe9ee7d1fab9961 (diff)
downloadtf-a-tests-85c39c56326ecd9a9e5f4ddefe8ec378fdedeb1c.tar.gz
Fix race condition in SError inject test
tftf/tests/misc_tests/inject_serror.S clears a flag, serror_received, then waits for it to be set by an error handler. However, it currently clears the flag after having started the count down timer to generate the error, so there is a data race between it and the error handler. This can cause the test to fail, if the error is generated and the flag set before it is first cleared. Fix this by clearing the serror_received flag before starting the count down timer. Change-Id: I919ef2a1bba66b19f47bccfcdbee944357881e8f Signed-off-by: David Horstmann <david.horstmann@arm.com>
-rw-r--r--tftf/tests/misc_tests/inject_serror.S19
1 files changed, 10 insertions, 9 deletions
diff --git a/tftf/tests/misc_tests/inject_serror.S b/tftf/tests/misc_tests/inject_serror.S
index 008503f1..d42441dd 100644
--- a/tftf/tests/misc_tests/inject_serror.S
+++ b/tftf/tests/misc_tests/inject_serror.S
@@ -16,9 +16,7 @@
/*
* Program fault injection register, and wait for ever for the fault to trigger.
- * Note that Trusted Firmware must be compiled for ARMv8.4 along with
- * FAULT_INJECTION_SUPPORT=1 for this to work. Besides, the model has to be
- * launched with fault inject support.
+ * Note that the model must be launched with fault inject support.
*
* x0: Fault record number to program
* x1: Injected fault properties
@@ -26,6 +24,10 @@
* x3: Memory location to wait for, or 0 if no waiting is required
*/
func inject_serror_record
+ /* Clear SError received flag if necessary */
+ cbz x3, 1f
+ str xzr, [x3, #0]
+1:
/* Choose Error record 0 on the PE */
msr ERRSELR_EL1, x0
isb
@@ -43,18 +45,17 @@ func inject_serror_record
msr ERXPFGCTL_EL1, x2
isb
- cbz x3, 2f
+ /* If no waiting is required, jump to end */
+ cbz x3, 3f
- /* Clear SError received flag */
- str xzr, [x3, #0]
sevl
-1:
+2:
wfe
ldr x0, [x3, #0]
- cbz x0, 1b
+ cbz x0, 2b
-2:
+3:
ret
endfunc inject_serror_record