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authorVarun Wadekar <vwadekar@nvidia.com>2020-03-27 09:43:24 -0700
committerVarun Wadekar <vwadekar@nvidia.com>2020-06-08 16:36:28 -0700
commit607d8d662b717d80d0587c6a0e2c1df278687062 (patch)
tree153cecc74c980110d1d2849733d83cc66a65e388
parent941be71a56d7ec5cce98a27765c87def1dcd803f (diff)
downloadtf-a-tests-607d8d662b717d80d0587c6a0e2c1df278687062.tar.gz
Tegra194: introduce per-CPU Hypervisor Timer Interrupt ID
This patch uses PPI 26 as the per-CPU Hypervisor Timer Interrupt ID. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I3e70aec91c129f57b39ca0d1165148880d59c8b3
-rw-r--r--plat/nvidia/tegra194/include/platform_def.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/plat/nvidia/tegra194/include/platform_def.h b/plat/nvidia/tegra194/include/platform_def.h
index fd9ecf69..bdfd98f0 100644
--- a/plat/nvidia/tegra194/include/platform_def.h
+++ b/plat/nvidia/tegra194/include/platform_def.h
@@ -117,6 +117,11 @@
#define IRQ_NS_SGI_7 7
/*******************************************************************************
+ * Per-CPU Hypervisor Timer Interrupt ID
+ ******************************************************************************/
+#define IRQ_PCPU_HP_TIMER 26
+
+/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)