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authorManish Pandey <manish.pandey2@arm.com>2022-01-25 14:26:12 +0000
committerManish Pandey <manish.pandey2@arm.com>2022-03-01 17:46:55 +0000
commit572ee4fde07faf8c208ebfd1bcaf745a93db003d (patch)
treef2a2755cc1937255fcd11b3c89b7adfce965b9c7
parent5f513d692006ac52b8cb87fe91cbfb002dd98e13 (diff)
downloadtf-a-tests-572ee4fde07faf8c208ebfd1bcaf745a93db003d.tar.gz
feat(fvp): enable test to access el3 memory
With newly introduced test to perform invalid accesses requires platform to provide test memory addresses. This patch provides EL3 memory access address for FVP platform. The invalid_access test will try to access el3 owned memory from tftf(ns-el2). Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I9c9493f1b33bdd91d8d4140cf9e96b2d9007fbe2
-rw-r--r--plat/arm/fvp/include/platform_def.h30
-rw-r--r--plat/arm/fvp/plat_setup.c2
2 files changed, 32 insertions, 0 deletions
diff --git a/plat/arm/fvp/include/platform_def.h b/plat/arm/fvp/include/platform_def.h
index 7fc147d4d..8555c1f37 100644
--- a/plat/arm/fvp/include/platform_def.h
+++ b/plat/arm/fvp/include/platform_def.h
@@ -57,6 +57,36 @@
#define NOR_FLASH_BLOCKS_COUNT 255
#define FLASH_SIZE (NOR_FLASH_BLOCK_SIZE * NOR_FLASH_BLOCKS_COUNT)
+/**********************************
+ * Addresses to test invalid access
+ **********************************/
+/*
+ * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as
+ * follows for FVP platform:
+ * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled
+ * - REALM DRAM: Reserved for Realm world if RME is enabled
+ * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
+ *
+ * RME enabled(64MB) RME not enabled(16MB)
+ * 0xFC00_0000 -------------------- ------------------- 0xFF00_0000
+ * | | | |
+ * | AP Secure (~28MB)| | AP TZC (~14MB) |
+ * -------------------- ------------------- 0xFFE0_0000
+ * | | | |
+ * | REALM (32MB) | | EL3 TZC (2MB) |
+ * -------------------- ------------------- 0xFFFF_FFFF
+ * | |
+ * 0xFFE0_0000 | EL3 Root (3MB) |
+ * --------------------
+ * | L1 GPT (1MB) |
+ * | |
+ * 0xFFFF_FFFF --------------------
+ *
+ *
+ */
+/* For both RME & non-RME case top 2MB will be EL3 memory */
+#define EL3_MEMORY_ACCESS_ADDR U(0xFFE00000)
+
/*******************************************************************************
* Base address and size for the FIP that contains FWU images.
******************************************************************************/
diff --git a/plat/arm/fvp/plat_setup.c b/plat/arm/fvp/plat_setup.c
index fa978142b..814261150 100644
--- a/plat/arm/fvp/plat_setup.c
+++ b/plat/arm/fvp/plat_setup.c
@@ -34,6 +34,8 @@ static const mmap_region_t mmap[] = {
MAP_REGION_FLAT(FLASH_BASE, FLASH_SIZE, MT_DEVICE | MT_RW | MT_NS),
#endif
MAP_REGION_FLAT(DRAM_BASE, TFTF_BASE - DRAM_BASE, MT_MEMORY | MT_RW | MT_NS),
+ /* Not usable in tftf, Only for testing purpose */
+ MAP_REGION_FLAT(EL3_MEMORY_ACCESS_ADDR, PAGE_SIZE, MT_MEMORY | MT_RW | MT_NS),
{0}
};
#endif /* IMAGE_NS_BL1U */