diff options
author | Manish V Badarkhe <Manish.Badarkhe@arm.com> | 2021-07-08 16:36:57 +0100 |
---|---|---|
committer | Manish V Badarkhe <Manish.Badarkhe@arm.com> | 2021-08-26 18:53:50 +0100 |
commit | 2c518e5c677e7b39100784a0360387b717506564 (patch) | |
tree | 987cdd4b72d88830568278e5d26953f7f9555e7f | |
parent | 87c03d1f4c06c1dea78abb359d9b1b4c24470f88 (diff) | |
download | tf-a-tests-2c518e5c677e7b39100784a0360387b717506564.tar.gz |
feat(trf): add trace filter control registers access test
Added a test to read trace filter control registers to ensure that EL3
is giving permission to non-secure EL2 to access these registers.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9354d8592bd187206add717b9d3b0206382a06d3
-rw-r--r-- | include/common/test_helpers.h | 8 | ||||
-rw-r--r-- | include/lib/aarch32/arch.h | 12 | ||||
-rw-r--r-- | include/lib/aarch32/arch_features.h | 9 | ||||
-rw-r--r-- | include/lib/aarch32/arch_helpers.h | 7 | ||||
-rw-r--r-- | include/lib/aarch64/arch.h | 11 | ||||
-rw-r--r-- | include/lib/aarch64/arch_features.h | 9 | ||||
-rw-r--r-- | include/lib/aarch64/arch_helpers.h | 4 | ||||
-rw-r--r-- | tftf/tests/extensions/trf/test_trf.c | 31 | ||||
-rw-r--r-- | tftf/tests/tests-cpu-extensions.mk | 1 | ||||
-rw-r--r-- | tftf/tests/tests-cpu-extensions.xml | 1 |
10 files changed, 90 insertions, 3 deletions
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h index 8d24a050f..a6f3768a1 100644 --- a/include/common/test_helpers.h +++ b/include/common/test_helpers.h @@ -255,6 +255,14 @@ typedef test_result_t (*test_function_arg_t)(void *arg); } \ } while (false) +#define SKIP_TEST_IF_TRF_NOT_SUPPORTED() \ + do { \ + if (!get_armv8_4_trf_support()) { \ + tftf_testcase_printf("ARMv8.4-TRF not supported\n"); \ + return TEST_RESULT_SKIPPED; \ + } \ + } while (false) + /* Helper macro to verify if system suspend API is supported */ #define is_psci_sys_susp_supported() \ (tftf_get_psci_feature_info(SMC_PSCI_SYSTEM_SUSPEND) \ diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 640457b51..3ecc047b3 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -99,6 +99,11 @@ #define ID_MMFR4_CNP_LENGTH U(4) #define ID_MMFR4_CNP_MASK U(0xf) +/* ID_DFR0_EL1 definitions */ +#define ID_DFR0_TRACEFILT_SHIFT U(28) +#define ID_DFR0_TRACEFILT_MASK U(0xf) +#define ID_DFR0_TRACEFILT_SUPPORTED U(1) + /* ID_PFR0 definitions */ #define ID_PFR0_AMU_SHIFT U(20) #define ID_PFR0_AMU_LENGTH U(4) @@ -522,6 +527,7 @@ #define ID_MMFR4 p15, 0, c0, c2, 6 #define ID_PFR0 p15, 0, c0, c1, 0 #define ID_PFR1 p15, 0, c0, c1, 1 +#define ID_DFR0 p15, 0, c0, c1, 2 #define MAIR0 p15, 0, c10, c2, 0 #define MAIR1 p15, 0, c10, c2, 1 #define TTBCR p15, 0, c2, c0, 2 @@ -725,4 +731,10 @@ #define AMEVTYPER1E p15, 0, c13, c15, 6 #define AMEVTYPER1F p15, 0, c13, c15, 7 +/******************************************************************************* + * Armv8.4 - Trace Filter System Registers + ******************************************************************************/ +#define TRFCR p15, 0, c1, c2, 1 +#define HTRFCR p15, 4, c1, c2, 1 + #endif /* ARCH_H */ diff --git a/include/lib/aarch32/arch_features.h b/include/lib/aarch32/arch_features.h index e2c2f2ccf..7d0ec5ffe 100644 --- a/include/lib/aarch32/arch_features.h +++ b/include/lib/aarch32/arch_features.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,4 +35,11 @@ static inline uint32_t arch_get_debug_version(void) DBGDIDR_VERSION_SHIFT); } +static inline bool get_armv8_4_trf_support(void) +{ + return ((read_id_dfr0() >> ID_DFR0_TRACEFILT_SHIFT) & + ID_DFR0_TRACEFILT_MASK) == + ID_DFR0_TRACEFILT_SUPPORTED; +} + #endif /* ARCH_FEATURES_H */ diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h index f2e3e009f..7bb2d0460 100644 --- a/include/lib/aarch32/arch_helpers.h +++ b/include/lib/aarch32/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -209,6 +209,7 @@ DEFINE_SYSREG_RW_FUNCS(elr_hyp) DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR) DEFINE_COPROCR_READ_FUNC(midr, MIDR) DEFINE_COPROCR_READ_FUNC(id_mmfr4, ID_MMFR4) +DEFINE_COPROCR_READ_FUNC(id_dfr0, ID_DFR0) DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0) DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1) DEFINE_COPROCR_READ_FUNC(isr, ISR) @@ -294,6 +295,10 @@ DEFINE_COPROCR_RW_FUNCS_64(par, PAR_64) DEFINE_COPROCR_RW_FUNCS(nsacr, NSACR) +/* AArch32 coproc registers for trace filter */ +DEFINE_COPROCR_RW_FUNCS(htrfcr, HTRFCR) +DEFINE_COPROCR_RW_FUNCS(trfcr, TRFCR) + /* AArch32 coproc registers for 32bit MMU descriptor support */ DEFINE_COPROCR_RW_FUNCS(prrr, PRRR) DEFINE_COPROCR_RW_FUNCS(nmrr, NMRR) diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index da76039aa..f21135dc8 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -167,6 +167,11 @@ #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) +/* ID_DFR0_EL1.Tracefilt definitions */ +#define ID_AA64DFR0_TRACEFILT_SHIFT U(40) +#define ID_AA64DFR0_TRACEFILT_MASK U(0xf) +#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) + #define EL_IMPL_NONE ULL(0) #define EL_IMPL_A64ONLY ULL(1) #define EL_IMPL_A64_A32 ULL(2) @@ -1014,4 +1019,10 @@ #define TRBTRG_EL1 S3_0_C9_C11_6 #define TRBIDR_EL1 S3_0_C9_C11_7 +/******************************************************************************* + * Armv8.4 - Trace Filter System Registers + ******************************************************************************/ +#define TRFCR_EL1 S3_0_C1_C2_1 +#define TRFCR_EL2 S3_4_C1_C2_1 + #endif /* ARCH_H */ diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h index d2665b419..fc8ac332f 100644 --- a/include/lib/aarch64/arch_features.h +++ b/include/lib/aarch64/arch_features.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -99,4 +99,11 @@ static inline bool get_armv9_0_trbe_support(void) ID_AA64DFR0_TRACEBUFFER_SUPPORTED; } +static inline bool get_armv8_4_trf_support(void) +{ + return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEFILT_SHIFT) & + ID_AA64DFR0_TRACEFILT_MASK) == + ID_AA64DFR0_TRACEFILT_SUPPORTED; +} + #endif /* ARCH_FEATURES_H */ diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index cb10cfe08..b1090d1d9 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -498,6 +498,10 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(trbmar_el1, TRBMAR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(trbtrg_el1, TRBTRG_EL1) DEFINE_RENAME_SYSREG_READ_FUNC(trbidr_el1, TRBIDR_EL1) +/* Armv8.4 Trace filter control System Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2) + #define IS_IN_EL(x) \ (GET_EL(read_CurrentEl()) == MODE_EL##x) diff --git a/tftf/tests/extensions/trf/test_trf.c b/tftf/tests/extensions/trf/test_trf.c new file mode 100644 index 000000000..eeb967db8 --- /dev/null +++ b/tftf/tests/extensions/trf/test_trf.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <string.h> + +#include <test_helpers.h> +#include <tftf_lib.h> +#include <tftf.h> + +/* + * EL3 is expected to allow access to trace filter control registers from EL2. + * Reading these register will trap to EL3 and crash when EL3 has not + * allowed access. + */ +test_result_t test_trf_enabled(void) +{ + SKIP_TEST_IF_TRF_NOT_SUPPORTED(); + +#ifdef __aarch64__ + read_trfcr_el1(); + read_trfcr_el2(); +#else + read_htrfcr(); + read_trfcr(); +#endif /* __aarch64__ */ + + return TEST_RESULT_SUCCESS; +} diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk index a4e5d112e..e5f4f799f 100644 --- a/tftf/tests/tests-cpu-extensions.mk +++ b/tftf/tests/tests-cpu-extensions.mk @@ -13,6 +13,7 @@ TESTS_SOURCES += $(addprefix tftf/tests/, \ extensions/sve/sve_operations.S \ extensions/sve/test_sve.c \ extensions/trbe/test_trbe.c \ + extensions/trf/test_trf.c \ runtime_services/arm_arch_svc/smccc_arch_soc_id.c \ runtime_services/arm_arch_svc/smccc_arch_workaround_1.c \ runtime_services/arm_arch_svc/smccc_arch_workaround_2.c \ diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml index d6b3d0068..a0d2c9a49 100644 --- a/tftf/tests/tests-cpu-extensions.xml +++ b/tftf/tests/tests-cpu-extensions.xml @@ -21,6 +21,7 @@ <testcase name="Use FGT Registers" function="test_fgt_enabled" /> <testcase name="Use ECV Registers" function="test_ecv_enabled" /> <testcase name="Use trace buffer control Registers" function="test_trbe_enabled" /> + <testcase name="Use trace filter control Registers" function="test_trf_enabled" /> </testsuite> <testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests"> |