diff options
author | anzhou <anzhou@nvidia.com> | 2020-06-04 13:20:18 +0800 |
---|---|---|
committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-10-28 09:00:18 -0700 |
commit | 113d2d2f4be90ba060ccb994bbbed4ee429c820b (patch) | |
tree | 3a710cd6f496a5da82f67d9582a7e427ceb50e41 | |
parent | b3bcf77a65880049e40fa6f1b764a19dbd9faead (diff) | |
download | tf-a-tests-113d2d2f4be90ba060ccb994bbbed4ee429c820b.tar.gz |
Tegra194: move drivers to common folder
The drivers: reset, timers. wake, watchdog can be used for
other nvidia platforms. Move them to drivers and remove the
t194 tag for the common functions and defines.
Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I658341ccd5d7a0fe21e65291c8ed71f9ccc93e5d
-rw-r--r-- | plat/nvidia/drivers/reset/reset.c (renamed from plat/nvidia/tegra194/reset.c) | 0 | ||||
-rw-r--r-- | plat/nvidia/drivers/timer/timers.c | 175 | ||||
-rw-r--r-- | plat/nvidia/drivers/wake/wake.c (renamed from plat/nvidia/tegra194/wake.c) | 4 | ||||
-rw-r--r-- | plat/nvidia/drivers/watchdog/watchdog.c (renamed from plat/nvidia/tegra194/watchdog.c) | 34 | ||||
-rw-r--r-- | plat/nvidia/tegra194/helpers.S | 20 | ||||
-rw-r--r-- | plat/nvidia/tegra194/include/platform_def.h | 42 | ||||
-rw-r--r-- | plat/nvidia/tegra194/platform.mk | 10 | ||||
-rw-r--r-- | plat/nvidia/tegra194/pwr_mgmt.c | 10 | ||||
-rw-r--r-- | plat/nvidia/tegra194/setup.c | 34 | ||||
-rw-r--r-- | plat/nvidia/tegra194/timers.c | 175 |
10 files changed, 252 insertions, 252 deletions
diff --git a/plat/nvidia/tegra194/reset.c b/plat/nvidia/drivers/reset/reset.c index 2112be428..2112be428 100644 --- a/plat/nvidia/tegra194/reset.c +++ b/plat/nvidia/drivers/reset/reset.c diff --git a/plat/nvidia/drivers/timer/timers.c b/plat/nvidia/drivers/timer/timers.c new file mode 100644 index 000000000..e8f359a64 --- /dev/null +++ b/plat/nvidia/drivers/timer/timers.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <stddef.h> +#include <platform.h> + +#include <mmio.h> +#include <timer.h> +#include <tftf_lib.h> +#include <utils_def.h> + +/* timer granularity in ms */ +#define TEGRA_RTC_STEP_VALUE_MS U(5) + +/* IRQ value for Tegra Timer0 */ +#define TEGRA_RTC_IRQ U(42) + +/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */ +#define TEGRA_RTC_REG_BUSY U(0x004) +#define TEGRA_RTC_REG_SECONDS U(0x008) +/* when msec is read, the seconds are buffered into shadow seconds. */ +#define TEGRA_RTC_REG_SHADOW_SECONDS U(0x00c) +#define TEGRA_RTC_REG_MILLI_SECONDS U(0x010) +#define TEGRA_RTC_REG_SECONDS_ALARM0 U(0x014) +#define TEGRA_RTC_REG_SECONDS_ALARM1 U(0x018) +#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 U(0x01c) +#define TEGRA_RTC_REG_MSEC_CDN_ALARM0 U(0x024) +#define TEGRA_RTC_REG_INTR_MASK U(0x028) +/* write 1 bits to clear status bits */ +#define TEGRA_RTC_REG_INTR_STATUS U(0x02c) + +/* + * bits in the TEGRA_RTC_REG_BUSY register + * bit 0: 1 = busy, 0 = idle + */ +#define TEGRA_RTC_REG_BUSY_BIT BIT_32(0) + +/* bits in INTR_MASK and INTR_STATUS */ +#define TEGRA_RTC_INTR_MSEC_CDN_ALARM BIT_32(4) +#define TEGRA_RTC_INTR_SEC_CDN_ALARM BIT_32(3) +#define TEGRA_RTC_INTR_MSEC_ALARM BIT_32(2) +#define TEGRA_RTC_INTR_SEC_ALARM1 BIT_32(1) +#define TEGRA_RTC_INTR_SEC_ALARM0 BIT_32(0) + +static bool is_rtc_busy(void) +{ + uint32_t reg = mmio_read_32(TEGRA_RTC_BASE + TEGRA_RTC_REG_BUSY) & + TEGRA_RTC_REG_BUSY_BIT; + + /* 1 = busy, 0 = idle */ + return (reg == 1U); +} + +/* + * Wait for hardware to be ready for writing. + * This function tries to maximize the amount of time before the next update. + * It does this by waiting for the RTC to become busy with its periodic update, + * then returning once the RTC first becomes not busy. + * This periodic update (where the seconds and milliseconds are copied to the + * AHB side) occurs every eight 32kHz clocks (~250uS). + * The behavior of this function allows us to make some assumptions without + * introducing a race, because 250uS is plenty of time to write a value. + */ +static void wait_until_idle(void) +{ + uint32_t retries = 500U; + + /* wait until idle */ + while (is_rtc_busy() || (retries-- > 0U)) { + waitus(1ULL); + } +} + +static void timer_idle_write_32(uint32_t offset, uint32_t val) +{ + /* wait until the RTC is idle first */ + wait_until_idle(); + + /* actual write */ + mmio_write_32(TEGRA_RTC_BASE + offset, val); + + /* wait until RTC has processed the write */ + wait_until_idle(); +} + +static uint32_t timer_idle_read_32(uint32_t offset) +{ + /* wait until the RTC is idle first */ + wait_until_idle(); + + /* actual read */ + return mmio_read_32(TEGRA_RTC_BASE + offset); +} + +static int cancel_timer(void) +{ + /* read current values to clear them */ + (void)timer_idle_read_32(TEGRA_RTC_REG_MILLI_SECONDS); + (void)timer_idle_read_32(TEGRA_RTC_REG_SHADOW_SECONDS); + + /* clear the alarm */ + timer_idle_write_32(TEGRA_RTC_REG_MSEC_CDN_ALARM0, 0U); + /* clear all status values */ + timer_idle_write_32(TEGRA_RTC_REG_INTR_STATUS, 0xffffffffU); + /* disable all interrupts */ + timer_idle_write_32(TEGRA_RTC_REG_INTR_MASK, 0U); + + return 0; +} + +static int program_timer(unsigned long time_out_ms) +{ + uint32_t reg; + + /* set timer value */ + reg = BIT_32(31) | (0x0fffffffU & time_out_ms); + timer_idle_write_32(TEGRA_RTC_REG_MSEC_CDN_ALARM0, reg); + + /* enable timer interrupt */ + timer_idle_write_32(TEGRA_RTC_REG_INTR_MASK, TEGRA_RTC_INTR_MSEC_ALARM); + + /* program timeout value */ + reg = timer_idle_read_32(TEGRA_RTC_REG_MILLI_SECONDS); + timer_idle_write_32(TEGRA_RTC_REG_MILLI_SECONDS_ALARM0, reg + time_out_ms); + + return 0; +} + +static int handler_timer(void) +{ + uint32_t __unused reg, status, mask; + + /* disable timer interrupt */ + reg = timer_idle_read_32(TEGRA_RTC_REG_INTR_MASK); + reg &= ~TEGRA_RTC_INTR_MSEC_CDN_ALARM; + timer_idle_write_32(TEGRA_RTC_REG_INTR_MASK, reg); + + /* read current values to clear them */ + reg = timer_idle_read_32(TEGRA_RTC_REG_MILLI_SECONDS); + reg = timer_idle_read_32(TEGRA_RTC_REG_SHADOW_SECONDS); + + /* clear interrupts */ + status = timer_idle_read_32(TEGRA_RTC_REG_INTR_STATUS); + mask = timer_idle_read_32(TEGRA_RTC_REG_INTR_MASK); + mask &= ~status; + if (status != 0U) { + timer_idle_write_32(TEGRA_RTC_REG_INTR_MASK, mask); + timer_idle_write_32(TEGRA_RTC_REG_INTR_STATUS, status); + } + + return 0; +} + +static const plat_timer_t tegra_timers = { + .program = program_timer, + .cancel = cancel_timer, + .handler = handler_timer, + .timer_step_value = TEGRA_RTC_STEP_VALUE_MS, + .timer_irq = TEGRA_RTC_IRQ +}; + +int plat_initialise_timer_ops(const plat_timer_t **timer_ops) +{ + assert(timer_ops != NULL); + *timer_ops = &tegra_timers; + + /* clear the timers */ + cancel_timer(); + + return 0; +} diff --git a/plat/nvidia/tegra194/wake.c b/plat/nvidia/drivers/wake/wake.c index d4bfbd6bd..c5d2103ae 100644 --- a/plat/nvidia/tegra194/wake.c +++ b/plat/nvidia/drivers/wake/wake.c @@ -30,10 +30,10 @@ static inline void aowake_write_32(uint32_t offset, uint32_t value) { - mmio_write_32(TEGRA194_AOWAKE_BASE + offset, value); + mmio_write_32(TEGRA_AOWAKE_BASE + offset, value); } -void tegra194_set_rtc_as_wakeup_source(void) +void tegra_set_rtc_as_wakeup_source(void) { /* * Configure RTC as the wake source to tier2 = CCPLEX, diff --git a/plat/nvidia/tegra194/watchdog.c b/plat/nvidia/drivers/watchdog/watchdog.c index 3773a3b6e..d3c0e9273 100644 --- a/plat/nvidia/tegra194/watchdog.c +++ b/plat/nvidia/drivers/watchdog/watchdog.c @@ -32,24 +32,24 @@ #define WDT_TIMEOUT_SECONDS U(10) #define WDT_TIMEOUT_MULTIPLIER UL(125000) -static inline void tegra194_wdt_write(uint32_t offset, uint32_t val) +static inline void tegra_wdt_write(uint32_t offset, uint32_t val) { - mmio_write_32(TEGRA194_WDT0_BASE + offset, val); + mmio_write_32(TEGRA_WDT0_BASE + offset, val); } -static inline uint32_t tegra194_wdt_read(uint32_t offset) +static inline uint32_t tegra_wdt_read(uint32_t offset) { - return mmio_read_32(TEGRA194_WDT0_BASE + offset); + return mmio_read_32(TEGRA_WDT0_BASE + offset); } -static inline void tegra194_tmr_write(uint32_t offset, uint32_t val) +static inline void tegra_tmr_write(uint32_t offset, uint32_t val) { - mmio_write_32(TEGRA194_TMR0_BASE + offset, val); + mmio_write_32(TEGRA_TMR0_BASE + offset, val); } -static inline uint32_t tegra194_tmr_read(uint32_t offset) +static inline uint32_t tegra_tmr_read(uint32_t offset) { - return mmio_read_32(TEGRA194_TMR0_BASE + offset); + return mmio_read_32(TEGRA_TMR0_BASE + offset); } /* @@ -60,24 +60,24 @@ void tftf_platform_watchdog_set(void) uint32_t val; /* Clear pending interrupts first */ - tegra194_tmr_write(TIMER_PCR, TIMER_PCR_INTR_BIT); + tegra_tmr_write(TIMER_PCR, TIMER_PCR_INTR_BIT); /* * Normally, we would set the period to 1 second by writing 125000ul, * but the watchdog system reset actually occurs on the 4th expiration * of this counter, so we set the period to 1/4 of this amount. */ - val = (WDT_TIMEOUT_SECONDS * WDT_TIMEOUT_MULTIPLIER) / 4; + val = (WDT_TIMEOUT_SECONDS * WDT_TIMEOUT_MULTIPLIER) / 4U; val |= (TIMER_EN_BIT | TIMER_PERIODIC_BIT); - tegra194_tmr_write(TIMER_PTV, val); + tegra_tmr_write(TIMER_PTV, val); /* * Set number of periods and start counter. */ val = WDT_CFG_TMR_SRC | WDT_CFG_SYS_RST_EN_BIT | WDT_CFG_PMC2CAR_RST_EN_BIT; - tegra194_wdt_write(WDT_CFG, val); - tegra194_wdt_write(WDT_CMD, WDT_CMD_START_COUNTER_BIT); + tegra_wdt_write(WDT_CFG, val); + tegra_wdt_write(WDT_CMD, WDT_CMD_START_COUNTER_BIT); } /* @@ -85,8 +85,8 @@ void tftf_platform_watchdog_set(void) */ void tftf_platform_watchdog_reset(void) { - tegra194_tmr_write(TIMER_PCR, TIMER_PCR_INTR_BIT); - tegra194_wdt_write(WDT_UNLOCK, WDT_UNLOCK_PATTERN); - tegra194_wdt_write(WDT_CMD, WDT_CMD_DISABLE_COUNTER_BIT); - tegra194_tmr_write(TIMER_PTV, 0); + tegra_tmr_write(TIMER_PCR, TIMER_PCR_INTR_BIT); + tegra_wdt_write(WDT_UNLOCK, WDT_UNLOCK_PATTERN); + tegra_wdt_write(WDT_CMD, WDT_CMD_DISABLE_COUNTER_BIT); + tegra_tmr_write(TIMER_PTV, 0U); } diff --git a/plat/nvidia/tegra194/helpers.S b/plat/nvidia/tegra194/helpers.S index 166913121..38681b56f 100644 --- a/plat/nvidia/tegra194/helpers.S +++ b/plat/nvidia/tegra194/helpers.S @@ -23,14 +23,14 @@ func platform_get_core_pos lsr x2, x0, #MPIDR_AFF1_SHIFT and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */ - /* core_id >= PLATFORM_CORES_PER_CLUSTER */ + /* core_id > PLATFORM_CORES_PER_CLUSTER */ mov x0, #-1 cmp x1, #(PLATFORM_CORES_PER_CLUSTER - 1) - b.gt 1f + b.hi 1f - /* cluster_id >= PLATFORM_CLUSTER_COUNT */ + /* cluster_id > PLATFORM_CLUSTER_COUNT */ cmp x2, #(PLATFORM_CLUSTER_COUNT - 1) - b.gt 1f + b.hi 1f /* CorePos = CoreId + (ClusterId * cpus per cluster) */ mov x3, #PLATFORM_CORES_PER_CLUSTER @@ -49,9 +49,9 @@ endfunc platform_get_core_pos * --------------------------------------------- */ func plat_crash_console_init - mov_imm x0, TEGRA194_UARTC_BASE - mov_imm x1, TEGRA194_CONSOLE_CLKRATE - mov_imm x2, TEGRA194_CONSOLE_BAUDRATE + mov_imm x0, TEGRA_UARTC_BASE + mov_imm x1, TEGRA_CONSOLE_CLKRATE + mov_imm x2, TEGRA_CONSOLE_BAUDRATE b console_init endfunc plat_crash_console_init @@ -63,7 +63,7 @@ endfunc plat_crash_console_init * --------------------------------------------- */ func plat_crash_console_putc - mov_imm x1, TEGRA194_UARTC_BASE + mov_imm x1, TEGRA_UARTC_BASE b console_putc endfunc plat_crash_console_putc @@ -72,10 +72,10 @@ endfunc plat_crash_console_putc * Function to force a write of all buffered * data that hasn't been output. * Out : return -1 on error else return 0. - * Clobber list : r0 - r1 + * Clobber list : x0 - x1 * --------------------------------------------- */ func plat_crash_console_flush - mov_imm x1, TEGRA194_UARTC_BASE + mov_imm x1, TEGRA_UARTC_BASE b console_flush endfunc plat_crash_console_flush diff --git a/plat/nvidia/tegra194/include/platform_def.h b/plat/nvidia/tegra194/include/platform_def.h index bdfd98f01..e580b4d05 100644 --- a/plat/nvidia/tegra194/include/platform_def.h +++ b/plat/nvidia/tegra194/include/platform_def.h @@ -11,8 +11,8 @@ * Platform definitions used by common code ******************************************************************************/ -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H /******************************************************************************* * Platform binary types for linking @@ -138,39 +138,39 @@ /******************************************************************************* * Platform console related constants ******************************************************************************/ -#define TEGRA194_CONSOLE_BAUDRATE U(115200) -#define TEGRA194_CONSOLE_CLKRATE U(408000000) +#define TEGRA_CONSOLE_BAUDRATE U(115200) +#define TEGRA_CONSOLE_CLKRATE U(408000000) /******************************************************************************* * Platform MMIO devices ******************************************************************************/ -#define TEGRA194_MC_BASE U(0x02C10000) -#define TEGRA194_TMR0_BASE U(0x03020000) -#define TEGRA194_WDT0_BASE U(0x030c0000) -#define TEGRA194_GICD_BASE U(0x03881000) -#define TEGRA194_GICC_BASE U(0x03882000) -#define TEGRA194_SPE_BASE U(0x0C168000) -#define TEGRA194_UARTC_BASE U(0x0C280000) -#define TEGRA194_RTC_BASE U(0x0C2A0000) -#define TEGRA194_TMRUS_BASE U(0x0C2E0000) -#define SYS_CNT_BASE1 TEGRA194_TMRUS_BASE -#define TEGRA194_AOWAKE_BASE U(0x0C370000) -#define TEGRA194_SCRATCH_BASE U(0x0C390000) -#define TEGRA194_SMMU0_BASE U(0x12000000) +#define TEGRA_MC_BASE U(0x02C10000) +#define TEGRA_TMR0_BASE U(0x03020000) +#define TEGRA_WDT0_BASE U(0x030c0000) +#define TEGRA_GICD_BASE U(0x03881000) +#define TEGRA_GICC_BASE U(0x03882000) +#define TEGRA_SPE_BASE U(0x0C168000) +#define TEGRA_UARTC_BASE U(0x0C280000) +#define TEGRA_RTC_BASE U(0x0C2A0000) +#define TEGRA_TMRUS_BASE U(0x0C2E0000) +#define SYS_CNT_BASE1 TEGRA_TMRUS_BASE +#define TEGRA_AOWAKE_BASE U(0x0C370000) +#define TEGRA_SCRATCH_BASE U(0x0C390000) +#define TEGRA_SMMU0_BASE U(0x12000000) /******************************************************************************* * DRAM carveout to save the SMMU context ******************************************************************************/ -#define TEGRA194_SMMU_CTX_BASE (DRAM_END - 0x1000) +#define TEGRA_SMMU_CTX_BASE (DRAM_END - 0x1000) #ifndef __ASSEMBLY__ /* * Platform functions */ -void tegra194_pwr_mgmt_setup(void); -void tegra194_set_rtc_as_wakeup_source(void); +void tegra_pwr_mgmt_setup(void); +void tegra_set_rtc_as_wakeup_source(void); #endif /* __ASSEMBLY__ */ -#endif /* __PLATFORM_DEF_H__ */ +#endif /* PLATFORM_DEF_H */ diff --git a/plat/nvidia/tegra194/platform.mk b/plat/nvidia/tegra194/platform.mk index 361e39836..081c24427 100644 --- a/plat/nvidia/tegra194/platform.mk +++ b/plat/nvidia/tegra194/platform.mk @@ -11,15 +11,15 @@ PLAT_SOURCES := drivers/arm/gic/arm_gic_v2.c \ drivers/arm/gic/gic_v2.c \ drivers/arm/timer/private_timer.c \ drivers/ti/uart/aarch64/16550_console.S \ + plat/nvidia/drivers/reset/reset.c \ + plat/nvidia/drivers/timer/timers.c \ + plat/nvidia/drivers/wake/wake.c \ + plat/nvidia/drivers/watchdog/watchdog.c \ plat/nvidia/tegra194/helpers.S \ plat/nvidia/tegra194/pwr_state.c \ plat/nvidia/tegra194/pwr_mgmt.c \ - plat/nvidia/tegra194/reset.c \ plat/nvidia/tegra194/setup.c \ - plat/nvidia/tegra194/topology.c \ - plat/nvidia/tegra194/timers.c \ - plat/nvidia/tegra194/wake.c \ - plat/nvidia/tegra194/watchdog.c + plat/nvidia/tegra194/topology.c PLAT_TESTS_SKIP_LIST := plat/nvidia/tegra194/tests_to_skip.txt diff --git a/plat/nvidia/tegra194/pwr_mgmt.c b/plat/nvidia/tegra194/pwr_mgmt.c index 2f43f0b9c..b5fe92b81 100644 --- a/plat/nvidia/tegra194/pwr_mgmt.c +++ b/plat/nvidia/tegra194/pwr_mgmt.c @@ -25,7 +25,7 @@ typedef struct mc_regs { #define mc_smmu_bypass_cfg \ { \ - .reg = TEGRA194_SMMU0_BASE, \ + .reg = TEGRA_SMMU0_BASE, \ .val = 0x00000000U, \ } @@ -50,15 +50,15 @@ static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = { END_OF_TABLE, }; -void tegra194_pwr_mgmt_setup(void) +void tegra_pwr_mgmt_setup(void) { - uintptr_t smmu_ctx_base = (uintptr_t)TEGRA194_SMMU_CTX_BASE; + uintptr_t smmu_ctx_base = (uintptr_t)TEGRA_SMMU_CTX_BASE; /* index of END_OF_TABLE */ tegra194_mc_context[0].val = ARRAY_SIZE(tegra194_mc_context) - 1U; /* prepare dummy context */ - for (int i = 1; i < ARRAY_SIZE(tegra194_mc_context) - 1U; i++) { + for (unsigned int i = 1U; i < ARRAY_SIZE(tegra194_mc_context) - 1U; i++) { tegra194_mc_context[i].val = mmio_read_32(tegra194_mc_context[i].reg); } @@ -68,6 +68,6 @@ void tegra194_pwr_mgmt_setup(void) flush_dcache_range(smmu_ctx_base, sizeof(tegra194_mc_context)); /* save SMMU context for SC7-RF to restore */ - mmio_write_32(TEGRA194_SCRATCH_BASE + SCRATCH_SECURE_RSV73_SCRATCH, + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV73_SCRATCH, smmu_ctx_base >> 12); } diff --git a/plat/nvidia/tegra194/setup.c b/plat/nvidia/tegra194/setup.c index d420acd6b..08529d7bf 100644 --- a/plat/nvidia/tegra194/setup.c +++ b/plat/nvidia/tegra194/setup.c @@ -17,31 +17,31 @@ * Memory map */ static const mmap_region_t tegra194_mmap[] = { - MAP_REGION_FLAT(TEGRA194_MC_BASE, 0x2000, /* 8KB */ + MAP_REGION_FLAT(TEGRA_MC_BASE, 0x2000, /* 8KB */ MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_TMR0_BASE, 0x1000, /* 4KB */ + MAP_REGION_FLAT(TEGRA_TMR0_BASE, 0x1000, /* 4KB */ MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_WDT0_BASE, 0x1000, /* 4KB */ + MAP_REGION_FLAT(TEGRA_WDT0_BASE, 0x1000, /* 4KB */ MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_GICD_BASE, 0x1000, /* 4KB */ + MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */ MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_GICC_BASE, 0x1000, /* 4KB */ + MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */ MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_UARTC_BASE, 0x20000U, /* 128KB */ + MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB */ MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_RTC_BASE, 0x1000, /* 4KB */ + MAP_REGION_FLAT(TEGRA_RTC_BASE, 0x1000, /* 4KB */ MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_TMRUS_BASE, 0x1000, /* 4KB */ + MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000, /* 4KB */ MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_AOWAKE_BASE, 0x1000, /* 4KB */ + MAP_REGION_FLAT(TEGRA_AOWAKE_BASE, 0x1000, /* 4KB */ MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_SCRATCH_BASE, 0x1000, /* 4KB */ + MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000, /* 4KB */ MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_SMMU0_BASE, 0x1000, /* 4KB */ + MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000, /* 4KB */ MT_DEVICE | MT_RW | MT_NS), MAP_REGION_FLAT(DRAM_BASE + TFTF_NVM_OFFSET, TFTF_NVM_SIZE, MT_MEMORY | MT_RW | MT_NS), - MAP_REGION_FLAT(TEGRA194_SMMU_CTX_BASE, 0x1000, /* 4KB */ + MAP_REGION_FLAT(TEGRA_SMMU_CTX_BASE, 0x1000, /* 4KB */ MT_MEMORY | MT_RW | MT_NS), {0} }; @@ -59,20 +59,20 @@ void tftf_plat_arch_setup(void) void tftf_early_platform_setup(void) { /* Tegra194 platforms use UARTC as the console */ - console_init(TEGRA194_UARTC_BASE, TEGRA194_CONSOLE_CLKRATE, - TEGRA194_CONSOLE_BAUDRATE); + console_init(TEGRA_UARTC_BASE, TEGRA_CONSOLE_CLKRATE, + TEGRA_CONSOLE_BAUDRATE); } void tftf_platform_setup(void) { - gicv2_init(TEGRA194_GICC_BASE, TEGRA194_GICD_BASE); + gicv2_init(TEGRA_GICC_BASE, TEGRA_GICD_BASE); gicv2_setup_distif(); gicv2_probe_gic_cpu_id(); gicv2_setup_cpuif(); /* Setup power management dependencies */ - tegra194_pwr_mgmt_setup(); + tegra_pwr_mgmt_setup(); /* Configure system suspend wake sources */ - tegra194_set_rtc_as_wakeup_source(); + tegra_set_rtc_as_wakeup_source(); } diff --git a/plat/nvidia/tegra194/timers.c b/plat/nvidia/tegra194/timers.c deleted file mode 100644 index 39080dfc9..000000000 --- a/plat/nvidia/tegra194/timers.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <stddef.h> - -#include <mmio.h> -#include <platform.h> -#include <timer.h> -#include <tftf_lib.h> -#include <utils_def.h> - -/* timer granularity in ms */ -#define TEGRA194_RTC_STEP_VALUE_MS U(5) - -/* IRQ value for Tegra194 Timer0 */ -#define TEGRA194_RTC_IRQ U(42) - -/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */ -#define TEGRA194_RTC_REG_BUSY U(0x004) -#define TEGRA194_RTC_REG_SECONDS U(0x008) -/* when msec is read, the seconds are buffered into shadow seconds. */ -#define TEGRA194_RTC_REG_SHADOW_SECONDS U(0x00c) -#define TEGRA194_RTC_REG_MILLI_SECONDS U(0x010) -#define TEGRA194_RTC_REG_SECONDS_ALARM0 U(0x014) -#define TEGRA194_RTC_REG_SECONDS_ALARM1 U(0x018) -#define TEGRA194_RTC_REG_MILLI_SECONDS_ALARM0 U(0x01c) -#define TEGRA194_RTC_REG_MSEC_CDN_ALARM0 U(0x024) -#define TEGRA194_RTC_REG_INTR_MASK U(0x028) -/* write 1 bits to clear status bits */ -#define TEGRA194_RTC_REG_INTR_STATUS U(0x02c) - -/* - * bits in the TEGRA194_RTC_REG_BUSY register - * bit 0: 1 = busy, 0 = idle - */ -#define TEGRA194_RTC_REG_BUSY_BIT BIT_32(0) - -/* bits in INTR_MASK and INTR_STATUS */ -#define TEGRA194_RTC_INTR_MSEC_CDN_ALARM BIT_32(4) -#define TEGRA194_RTC_INTR_SEC_CDN_ALARM BIT_32(3) -#define TEGRA194_RTC_INTR_MSEC_ALARM BIT_32(2) -#define TEGRA194_RTC_INTR_SEC_ALARM1 BIT_32(1) -#define TEGRA194_RTC_INTR_SEC_ALARM0 BIT_32(0) - -static bool is_rtc_busy(void) -{ - uint32_t reg = mmio_read_32(TEGRA194_RTC_BASE + TEGRA194_RTC_REG_BUSY) & - TEGRA194_RTC_REG_BUSY_BIT; - - /* 1 = busy, 0 = idle */ - return (reg == 1); -} - -/* - * Wait for hardware to be ready for writing. - * This function tries to maximize the amount of time before the next update. - * It does this by waiting for the RTC to become busy with its periodic update, - * then returning once the RTC first becomes not busy. - * This periodic update (where the seconds and milliseconds are copied to the - * AHB side) occurs every eight 32kHz clocks (~250uS). - * The behavior of this function allows us to make some assumptions without - * introducing a race, because 250uS is plenty of time to write a value. - */ -static void wait_until_idle(void) -{ - uint32_t retries = 500; - - /* wait until idle */ - while (is_rtc_busy() || (retries-- > 0)) { - waitus(1); - } -} - -static void timer_idle_write_32(uint32_t offset, uint32_t val) -{ - /* wait until the RTC is idle first */ - wait_until_idle(); - - /* actual write */ - mmio_write_32(TEGRA194_RTC_BASE + offset, val); - - /* wait until RTC has processed the write */ - wait_until_idle(); -} - -static uint32_t timer_idle_read_32(uint32_t offset) -{ - /* wait until the RTC is idle first */ - wait_until_idle(); - - /* actual read */ - return mmio_read_32(TEGRA194_RTC_BASE + offset); -} - -static int cancel_timer(void) -{ - /* read current values to clear them */ - (void)timer_idle_read_32(TEGRA194_RTC_REG_MILLI_SECONDS); - (void)timer_idle_read_32(TEGRA194_RTC_REG_SHADOW_SECONDS); - - /* clear the alarm */ - timer_idle_write_32(TEGRA194_RTC_REG_MSEC_CDN_ALARM0, 0); - /* clear all status values */ - timer_idle_write_32(TEGRA194_RTC_REG_INTR_STATUS, 0xffffffff); - /* disable all interrupts */ - timer_idle_write_32(TEGRA194_RTC_REG_INTR_MASK, 0); - - return 0; -} - -static int program_timer(unsigned long time_out_ms) -{ - uint32_t reg; - - /* set timer value */ - reg = BIT_32(31) | (0x0fffffff & time_out_ms); - timer_idle_write_32(TEGRA194_RTC_REG_MSEC_CDN_ALARM0, reg); - - /* enable timer interrupt */ - timer_idle_write_32(TEGRA194_RTC_REG_INTR_MASK, TEGRA194_RTC_INTR_MSEC_ALARM); - - /* program timeout value */ - reg = timer_idle_read_32(TEGRA194_RTC_REG_MILLI_SECONDS); - timer_idle_write_32(TEGRA194_RTC_REG_MILLI_SECONDS_ALARM0, reg + time_out_ms); - - return 0; -} - -static int handler_timer(void) -{ - uint32_t __unused reg, status, mask; - - /* disable timer interrupt */ - reg = timer_idle_read_32(TEGRA194_RTC_REG_INTR_MASK); - reg &= ~TEGRA194_RTC_INTR_MSEC_CDN_ALARM; - timer_idle_write_32(TEGRA194_RTC_REG_INTR_MASK, reg); - - /* read current values to clear them */ - reg = timer_idle_read_32(TEGRA194_RTC_REG_MILLI_SECONDS); - reg = timer_idle_read_32(TEGRA194_RTC_REG_SHADOW_SECONDS); - - /* clear interrupts */ - status = timer_idle_read_32(TEGRA194_RTC_REG_INTR_STATUS); - mask = timer_idle_read_32(TEGRA194_RTC_REG_INTR_MASK); - mask &= ~status; - if (status) { - timer_idle_write_32(TEGRA194_RTC_REG_INTR_MASK, mask); - timer_idle_write_32(TEGRA194_RTC_REG_INTR_STATUS, status); - } - - return 0; -} - -static const plat_timer_t tegra194_timers = { - .program = program_timer, - .cancel = cancel_timer, - .handler = handler_timer, - .timer_step_value = TEGRA194_RTC_STEP_VALUE_MS, - .timer_irq = TEGRA194_RTC_IRQ -}; - -int plat_initialise_timer_ops(const plat_timer_t **timer_ops) -{ - assert(timer_ops != NULL); - *timer_ops = &tegra194_timers; - - /* clear the timers */ - cancel_timer(); - - return 0; -} |