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authorVarun Wadekar <vwadekar@nvidia.com>2020-05-06 10:30:59 -0700
committerVarun Wadekar <vwadekar@nvidia.com>2020-06-08 16:36:28 -0700
commit00ed5a4b3b0ddfeb925708e3afb037cc89ebd816 (patch)
treebf3c91e4eebda0e129be310642d0ebdaad9302ee
parent607d8d662b717d80d0587c6a0e2c1df278687062 (diff)
downloadtf-a-tests-00ed5a4b3b0ddfeb925708e3afb037cc89ebd816.tar.gz
tests: arm_arch_svc: introduce support for NVIDIA Denver CPUs
This patch introduces support for NVIDIA Denver CPUs and variants in the SMCCC_ARCH_WORKAROUND_1 test. Verified with TFTF ARM_ARCH_SVC test on Tegra194. <snip> Running test suite 'ARM_ARCH_SVC' Description: Arm Architecture Service tests > Executing 'SMCCC_ARCH_WORKAROUND_1 test' INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off TEST COMPLETE Passed <snip> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ibe179b43fd6a43c4fb5c6cdc7b0c78904efb1b5e
-rw-r--r--tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c b/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c
index e88f183..93abf15 100644
--- a/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c
+++ b/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,9 +20,15 @@
#define CORTEX_A72_MIDR 0x410FD080
#define CORTEX_A73_MIDR 0x410FD090
#define CORTEX_A75_MIDR 0x410FD0A0
+#define DENVER_MIDR_PN0 0x4E0F0000
+#define DENVER_MIDR_PN1 0x4E0F0010
+#define DENVER_MIDR_PN2 0x4E0F0020
+#define DENVER_MIDR_PN3 0x4E0F0030
+#define DENVER_MIDR_PN4 0x4E0F0040
static int cortex_a57_test(void);
static int csv2_test(void);
+static int denver_test(void);
static struct ent {
unsigned int midr;
@@ -31,6 +38,11 @@ static struct ent {
{ .midr = CORTEX_A72_MIDR, .wa_required = csv2_test },
{ .midr = CORTEX_A73_MIDR, .wa_required = csv2_test },
{ .midr = CORTEX_A75_MIDR, .wa_required = csv2_test },
+ { .midr = DENVER_MIDR_PN0, .wa_required = denver_test },
+ { .midr = DENVER_MIDR_PN1, .wa_required = denver_test },
+ { .midr = DENVER_MIDR_PN2, .wa_required = denver_test },
+ { .midr = DENVER_MIDR_PN3, .wa_required = denver_test },
+ { .midr = DENVER_MIDR_PN4, .wa_required = denver_test },
};
static int cortex_a57_test(void)
@@ -48,6 +60,11 @@ static int csv2_test(void)
return 1;
}
+static int denver_test(void)
+{
+ return 1;
+}
+
static test_result_t test_smccc_entrypoint(void)
{
smc_args args;