diff options
author | Deepika Bhavnani <deepika.bhavnani@arm.com> | 2020-02-06 16:29:45 -0600 |
---|---|---|
committer | Deepika Bhavnani <deepika.bhavnani@arm.com> | 2020-02-11 09:22:12 -0600 |
commit | c249d5e5cfbf2aa0f584001543c1d39953e1d6aa (patch) | |
tree | bae825efb76949c451188bb0e96de2ea1b120514 | |
parent | 1b5952a79ca1a6feb7b23372420285e886497852 (diff) | |
download | tf-a-tests-c249d5e5cfbf2aa0f584001543c1d39953e1d6aa.tar.gz |
Switch AARCH32/AARCH64 to __aarch64__
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.
All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)
NOTE: This change is based on below TFA commit
https://github.com/ARM-software/arm-trusted-firmware/commit/402b3cf8766fe2cb4ae462f7ee7761d08a1ba56c
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: If2c3dbaeb01d4a9d8cfd95d906e5eaf4ae94417f
38 files changed, 91 insertions, 113 deletions
@@ -157,12 +157,6 @@ $(eval $(call add_define,TFTF_DEFINES,NEW_TEST_SESSION)) $(eval $(call add_define,TFTF_DEFINES,PLAT_${PLAT})) $(eval $(call add_define,TFTF_DEFINES,USE_NVM)) -ifeq (${ARCH},aarch32) - $(eval $(call add_define,TFTF_DEFINES,AARCH32)) -else - $(eval $(call add_define,TFTF_DEFINES,AARCH64)) -endif - ################################################################################ # Assembler, compiler and linker flags shared across all test images. diff --git a/drivers/arm/gic/gic_common.c b/drivers/arm/gic/gic_common.c index e16b21374..7e76a20ed 100644 --- a/drivers/arm/gic/gic_common.c +++ b/drivers/arm/gic/gic_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -190,7 +190,7 @@ void gicd_set_ipriorityr(uintptr_t base, unsigned int interrupt_id, unsigned int is_gicv3_mode(void) { /* Check if GICv3 system register available */ -#ifndef AARCH32 +#ifdef __aarch64__ if (!(read_id_aa64pfr0_el1() & (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT))) return 0; #else diff --git a/drivers/arm/gic/gic_v3.c b/drivers/arm/gic/gic_v3.c index ea6615945..56049e313 100644 --- a/drivers/arm/gic/gic_v3.c +++ b/drivers/arm/gic/gic_v3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,7 +18,7 @@ static uintptr_t gicr_base_addr; static uintptr_t gicd_base_addr; -#ifndef AARCH32 +#ifdef __aarch64__ #define MPIDR_AFFLVL3_MASK ((unsigned long long)MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) #define gic_typer_affinity_from_mpidr(mpidr) \ (((mpidr) & (~MPIDR_AFFLVL3_MASK)) | (((mpidr) & MPIDR_AFFLVL3_MASK) >> 8)) @@ -312,7 +312,7 @@ void gicv3_send_sgi(unsigned int sgi_id, unsigned int core_pos) aff0 = MPIDR_AFF_ID(mpidr_list[core_pos], 0); aff1 = MPIDR_AFF_ID(mpidr_list[core_pos], 1); aff2 = MPIDR_AFF_ID(mpidr_list[core_pos], 2); -#ifndef AARCH32 +#ifdef __aarch64__ unsigned long long aff3; aff3 = MPIDR_AFF_ID(mpidr_list[core_pos], 3); #endif @@ -323,7 +323,7 @@ void gicv3_send_sgi(unsigned int sgi_id, unsigned int core_pos) /* Construct the SGI target affinity */ sgir = -#ifndef AARCH32 +#ifdef __aarch64__ ((aff3 & SGI1R_AFF_MASK) << SGI1R_AFF3_SHIFT) | #endif ((aff2 & SGI1R_AFF_MASK) << SGI1R_AFF2_SHIFT) | @@ -333,7 +333,7 @@ void gicv3_send_sgi(unsigned int sgi_id, unsigned int core_pos) /* Combine SGI target affinity with the SGI ID */ sgir |= ((sgi_id & SGI1R_INTID_MASK) << SGI1R_INTID_SHIFT); -#ifndef AARCH32 +#ifdef __aarch64__ write_icc_sgi1r(sgir); #else write64_icc_sgi1r(sgir); @@ -477,7 +477,7 @@ void gicv3_setup_distif(void) assert(gicd_base_addr); /* Check for system register support */ -#ifndef AARCH32 +#ifdef __aarch64__ assert(read_id_aa64pfr0_el1() & (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); #else diff --git a/fwu/ns_bl1u/ns_bl1u.mk b/fwu/ns_bl1u/ns_bl1u.mk index 7bdb03429..7e0e76791 100644 --- a/fwu/ns_bl1u/ns_bl1u.mk +++ b/fwu/ns_bl1u/ns_bl1u.mk @@ -70,9 +70,6 @@ $(eval $(call add_define,NS_BL1U_DEFINES,ENABLE_ASSERTIONS)) $(eval $(call add_define,NS_BL1U_DEFINES,FWU_BL_TEST)) $(eval $(call add_define,NS_BL1U_DEFINES,LOG_LEVEL)) $(eval $(call add_define,NS_BL1U_DEFINES,PLAT_${PLAT})) -ifeq (${ARCH},aarch32) - $(eval $(call add_define,NS_BL1U_DEFINES,AARCH32)) -else - $(eval $(call add_define,NS_BL1U_DEFINES,AARCH64)) +ifeq (${ARCH},aarch64) $(eval $(call add_define,NS_BL1U_DEFINES,ENABLE_PAUTH)) endif diff --git a/fwu/ns_bl2u/ns_bl2u.mk b/fwu/ns_bl2u/ns_bl2u.mk index 209e78b77..b6e616e8e 100644 --- a/fwu/ns_bl2u/ns_bl2u.mk +++ b/fwu/ns_bl2u/ns_bl2u.mk @@ -65,9 +65,6 @@ $(eval $(call add_define,NS_BL2U_DEFINES,ENABLE_ASSERTIONS)) $(eval $(call add_define,NS_BL2U_DEFINES,FWU_BL_TEST)) $(eval $(call add_define,NS_BL2U_DEFINES,LOG_LEVEL)) $(eval $(call add_define,NS_BL2U_DEFINES,PLAT_${PLAT})) -ifeq (${ARCH},aarch32) - $(eval $(call add_define,NS_BL2U_DEFINES,AARCH32)) -else - $(eval $(call add_define,NS_BL2U_DEFINES,AARCH64)) +ifeq (${ARCH},aarch64) $(eval $(call add_define,NS_BL2U_DEFINES,ENABLE_PAUTH)) endif diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h index 205d203f0..a90fd715f 100644 --- a/include/common/test_helpers.h +++ b/include/common/test_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,7 +26,7 @@ typedef struct { typedef test_result_t (*test_function_arg_t)(void *arg); -#ifdef AARCH32 +#ifndef __aarch64__ #define SKIP_TEST_IF_AARCH32() \ do { \ tftf_testcase_printf("Test not supported on aarch32\n"); \ diff --git a/include/drivers/arm/gic_v3.h b/include/drivers/arm/gic_v3.h index 1b028b6e8..0346a235f 100644 --- a/include/drivers/arm/gic_v3.h +++ b/include/drivers/arm/gic_v3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -71,7 +71,7 @@ #define SGI1R_AFF_MASK 0xff #define SGI1R_AFF1_SHIFT 16ULL #define SGI1R_AFF2_SHIFT 32ULL -#ifndef AARCH32 +#ifdef __aarch64__ #define SGI1R_AFF3_SHIFT 48ULL #endif #define SGI1R_INTID_MASK 0xf diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 02963ac50..78d41311d 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,7 +19,7 @@ #define BIT_32(nr) (U(1) << (nr)) #define BIT_64(nr) (ULL(1) << (nr)) -#ifdef AARCH32 +#ifndef __aarch64__ #define BIT BIT_32 #else #define BIT BIT_64 @@ -44,7 +44,7 @@ (((~UINT64_C(0)) << (l)) & (~UINT64_C(0) >> (64 - 1 - (h)))) #endif -#ifdef AARCH32 +#ifndef __aarch64__ #define GENMASK GENMASK_32 #else #define GENMASK GENMASK_64 @@ -130,7 +130,7 @@ #endif /* Register size of the current architecture. */ -#ifdef AARCH32 +#ifndef __aarch64__ #define REGSZ U(4) #else #define REGSZ U(8) diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h index 85effcaa5..15ab2ef12 100644 --- a/include/lib/xlat_tables/xlat_mmu_helpers.h +++ b/include/lib/xlat_tables/xlat_mmu_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -65,7 +65,7 @@ void setup_mmu_cfg(uint64_t *params, unsigned int flags, const uint64_t *base_table, unsigned long long max_pa, uintptr_t max_va, int xlat_regime); -#ifdef AARCH32 +#ifndef __aarch64__ /* AArch32 specific translation table API */ void enable_mmu_svc_mon(unsigned int flags); void enable_mmu_hyp(unsigned int flags); @@ -81,7 +81,7 @@ void enable_mmu_el3(unsigned int flags); void enable_mmu_direct_el1(unsigned int flags); void enable_mmu_direct_el2(unsigned int flags); void enable_mmu_direct_el3(unsigned int flags); -#endif /* AARCH32 */ +#endif /* !__aarch64__ */ bool xlat_arch_is_granule_size_supported(size_t size); size_t xlat_arch_get_max_supported_granule_size(void); diff --git a/include/lib/xlat_tables/xlat_tables_arch.h b/include/lib/xlat_tables/xlat_tables_arch.h index 723753403..c8f29e410 100644 --- a/include/lib/xlat_tables/xlat_tables_arch.h +++ b/include/lib/xlat_tables/xlat_tables_arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #ifndef XLAT_TABLES_ARCH_H #define XLAT_TABLES_ARCH_H -#ifdef AARCH32 +#ifndef __aarch64__ #include "aarch32/xlat_tables_aarch32.h" #else #include "aarch64/xlat_tables_aarch64.h" diff --git a/include/runtime_services/pmf.h b/include/runtime_services/pmf.h index 55828e219..d2ed412f8 100644 --- a/include/runtime_services/pmf.h +++ b/include/runtime_services/pmf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ /* * Defines for PMF SMC function ids. */ -#ifdef AARCH32 +#ifndef __aarch64__ #define PMF_SMC_GET_TIMESTAMP 0x82000010 #else #define PMF_SMC_GET_TIMESTAMP 0xC2000010 diff --git a/include/runtime_services/psci.h b/include/runtime_services/psci.h index 1ecfc63d6..f93ee407a 100644 --- a/include/runtime_services/psci.h +++ b/include/runtime_services/psci.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,7 +67,7 @@ /* * Architecture-specific SMC function IDs */ -#ifndef AARCH32 +#ifdef __aarch64__ #define SMC_PSCI_CPU_SUSPEND SMC_PSCI_CPU_SUSPEND_AARCH64 #define SMC_PSCI_CPU_ON SMC_PSCI_CPU_ON_AARCH64 #define SMC_PSCI_AFFINITY_INFO SMC_PSCI_AFFINITY_INFO_AARCH64 diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c index 9b481a18d..0f3bab90c 100644 --- a/lib/xlat_tables_v2/xlat_tables_context.c +++ b/lib/xlat_tables_v2/xlat_tables_context.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -134,7 +134,7 @@ int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr) #define MAX_PHYS_ADDR tf_xlat_ctx.max_pa #endif -#ifdef AARCH32 +#ifndef __aarch64__ void enable_mmu_svc_mon(unsigned int flags) { @@ -178,4 +178,4 @@ void enable_mmu_el3(unsigned int flags) enable_mmu_direct_el3(flags); } -#endif /* AARCH32 */ +#endif /* !__aarch64__ */ diff --git a/plat/arm/fvp/fvp_mem_prot.c b/plat/arm/fvp/fvp_mem_prot.c index 6a7d651ef..2682ba92e 100644 --- a/plat/arm/fvp/fvp_mem_prot.c +++ b/plat/arm/fvp/fvp_mem_prot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,7 @@ static const mem_region_t fvp_ram_ranges[] = { {NS_IMAGE_LIMIT, 1 << ONE_GB_SHIFT}, -#ifdef AARCH64 +#ifdef __aarch64__ {FVP_DRAM2_BASE, 1 << ONE_GB_SHIFT}, #endif }; diff --git a/plat/arm/fvp/include/platform_def.h b/plat/arm/fvp/include/platform_def.h index 4f64079f1..27f485111 100644 --- a/plat/arm/fvp/include/platform_def.h +++ b/plat/arm/fvp/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,7 +19,7 @@ /******************************************************************************* * Platform binary types for linking ******************************************************************************/ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 #else @@ -176,7 +176,7 @@ /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ -#if AARCH64 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 34) #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 34) #else diff --git a/plat/arm/juno/include/platform_def.h b/plat/arm/juno/include/platform_def.h index 4be864595..03a71246b 100644 --- a/plat/arm/juno/include/platform_def.h +++ b/plat/arm/juno/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,7 +19,7 @@ /******************************************************************************* * Platform binary types for linking ******************************************************************************/ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 #else @@ -171,7 +171,7 @@ /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ -#if AARCH64 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 34) #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 34) #else diff --git a/plat/arm/juno/juno_mem_prot.c b/plat/arm/juno/juno_mem_prot.c index f0e350673..3570e38fc 100644 --- a/plat/arm/juno/juno_mem_prot.c +++ b/plat/arm/juno/juno_mem_prot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,7 @@ static const mem_region_t juno_ram_ranges[] = { {NS_IMAGE_LIMIT, 128 << TWO_MB_SHIFT}, -#ifdef AARCH64 +#ifdef __aarch64__ {JUNO_DRAM2_BASE, 1 << ONE_GB_SHIFT}, #endif }; diff --git a/plat/common/plat_common.c b/plat/common/plat_common.c index 4cfbebbf3..b6cfec30c 100644 --- a/plat/common/plat_common.c +++ b/plat/common/plat_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -112,7 +112,7 @@ void tftf_plat_configure_mmu(void) void tftf_plat_enable_mmu(void) { -#ifndef AARCH32 +#ifdef __aarch64__ if (IS_IN_EL1()) enable_mmu_el1(0); else if (IS_IN_EL2()) diff --git a/spm/cactus/cactus.mk b/spm/cactus/cactus.mk index 56209027b..d4be8c625 100644 --- a/spm/cactus/cactus.mk +++ b/spm/cactus/cactus.mk @@ -57,11 +57,7 @@ $(eval $(call add_define,CACTUS_DEFINES,FVP_MAX_PE_PER_CPU)) $(eval $(call add_define,CACTUS_DEFINES,ENABLE_ASSERTIONS)) $(eval $(call add_define,CACTUS_DEFINES,LOG_LEVEL)) $(eval $(call add_define,CACTUS_DEFINES,PLAT_${PLAT})) -ifeq (${ARCH},aarch32) - $(eval $(call add_define,CACTUS_DEFINES,AARCH32)) -else - $(eval $(call add_define,CACTUS_DEFINES,AARCH64)) -endif + $(CACTUS_DTB) : $(BUILD_PLAT)/cactus $(BUILD_PLAT)/cactus/cactus.elf $(CACTUS_DTB) : spm/cactus/cactus.dts diff --git a/spm/cactus_mm/cactus_mm.mk b/spm/cactus_mm/cactus_mm.mk index 449f2ce8f..c76890d65 100644 --- a/spm/cactus_mm/cactus_mm.mk +++ b/spm/cactus_mm/cactus_mm.mk @@ -54,4 +54,4 @@ CACTUS_MM_DEFINES += -DENABLE_ASSERTIONS=0 $(eval $(call add_define,CACTUS_MM_DEFINES,DEBUG)) $(eval $(call add_define,CACTUS_MM_DEFINES,LOG_LEVEL)) $(eval $(call add_define,CACTUS_MM_DEFINES,PLAT_${PLAT})) -$(eval $(call add_define,CACTUS_MM_DEFINES,AARCH64)) + diff --git a/spm/ivy/ivy.mk b/spm/ivy/ivy.mk index 2985b60cc..16f62add5 100644 --- a/spm/ivy/ivy.mk +++ b/spm/ivy/ivy.mk @@ -53,11 +53,6 @@ $(eval $(call add_define,IVY_DEFINES,DEBUG)) $(eval $(call add_define,IVY_DEFINES,ENABLE_ASSERTIONS)) $(eval $(call add_define,IVY_DEFINES,LOG_LEVEL)) $(eval $(call add_define,IVY_DEFINES,PLAT_${PLAT})) -ifeq (${ARCH},aarch32) - $(eval $(call add_define,IVY_DEFINES,AARCH32)) -else - $(eval $(call add_define,IVY_DEFINES,AARCH64)) -endif $(IVY_DTB) : $(BUILD_PLAT)/ivy $(BUILD_PLAT)/ivy/ivy.elf $(IVY_DTB) : spm/ivy/ivy.dts diff --git a/spm/quark/quark.mk b/spm/quark/quark.mk index 9bf81d148..20ddd1f5b 100644 --- a/spm/quark/quark.mk +++ b/spm/quark/quark.mk @@ -50,7 +50,6 @@ QUARK_DEFINES := $(eval $(call add_define,QUARK_DEFINES,DEBUG)) $(eval $(call add_define,QUARK_DEFINES,ENABLE_ASSERTIONS)) $(eval $(call add_define,QUARK_DEFINES,PLAT_${PLAT})) -$(eval $(call add_define,QUARK_DEFINES,AARCH64)) $(QUARK_DTB) : $(BUILD_PLAT)/quark $(BUILD_PLAT)/quark/quark.elf $(QUARK_DTB) : spm/quark/quark.dts diff --git a/tftf/framework/main.c b/tftf/framework/main.c index 2523a9784..2350b9622 100644 --- a/tftf/framework/main.c +++ b/tftf/framework/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -517,7 +517,7 @@ void __dead2 tftf_cold_boot_main(void) NOTICE("%s\n", build_message); NOTICE("%s\n\n", version_string); -#ifndef AARCH32 +#ifdef __aarch64__ NOTICE("Running at NS-EL%u\n", IS_IN_EL(1) ? 1 : 2); #else NOTICE("Running in AArch32 HYP mode\n"); diff --git a/tftf/tests/extensions/mte/test_mte.c b/tftf/tests/extensions/mte/test_mte.c index 13da667d2..7dbb9ef7f 100644 --- a/tftf/tests/extensions/mte/test_mte.c +++ b/tftf/tests/extensions/mte/test_mte.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ test_result_t test_mte_instructions(void) { SKIP_TEST_IF_AARCH32(); -#ifdef AARCH64 +#ifdef __aarch64__ SKIP_TEST_IF_MTE_SUPPORT_LESS_THAN(MTE_IMPLEMENTED_EL0); /* irg */ @@ -24,13 +24,13 @@ test_result_t test_mte_instructions(void) __asm__ volatile (".inst 0xD1800129"); return TEST_RESULT_SUCCESS; -#endif /* AARCH64 */ +#endif /* __aarch64__ */ } test_result_t test_mte_leakage(void) { SKIP_TEST_IF_AARCH32(); -#ifdef AARCH64 +#ifdef __aarch64__ smc_args tsp_svc_params; int gcr_el1; @@ -53,5 +53,5 @@ test_result_t test_mte_leakage(void) } return TEST_RESULT_SUCCESS; -#endif /* AARCH64 */ +#endif /* __aarch64__ */ } diff --git a/tftf/tests/extensions/sve/sve_operations.S b/tftf/tests/extensions/sve/sve_operations.S index 9440b1367..e528b2bfe 100644 --- a/tftf/tests/extensions/sve/sve_operations.S +++ b/tftf/tests/extensions/sve/sve_operations.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,7 @@ #include "./test_sve.h" -#ifdef AARCH64 +#ifdef __aarch64__ #if __GNUC__ > 8 || (__GNUC__ == 8 && __GNUC_MINOR__ > 0) /* @@ -36,4 +36,4 @@ func sve_subtract_arrays endfunc sve_subtract_arrays #endif /* __GNUC__ > 8 || (__GNUC__ == 8 && __GNUC_MINOR__ > 0) */ -#endif /* AARCH64 */ +#endif /* __aarch64__ */ diff --git a/tftf/tests/misc_tests/inject_serror.S b/tftf/tests/misc_tests/inject_serror.S index 0d7dbf2d7..008503f1f 100644 --- a/tftf/tests/misc_tests/inject_serror.S +++ b/tftf/tests/misc_tests/inject_serror.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,7 @@ #include <sdei.h> -#ifdef AARCH64 +#ifdef __aarch64__ .globl inject_serror .globl inject_uncontainable .globl serror_sdei_event_handler diff --git a/tftf/tests/misc_tests/test_pmu_leakage.c b/tftf/tests/misc_tests/test_pmu_leakage.c index da289992f..36b3138ba 100644 --- a/tftf/tests/misc_tests/test_pmu_leakage.c +++ b/tftf/tests/misc_tests/test_pmu_leakage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -75,7 +75,7 @@ struct pmu_event_info { unsigned long long avg; }; -#ifdef AARCH64 +#ifdef __aarch64__ #define V8_2_DEBUG_ARCH_SUPPORTED ID_AA64DFR0_V8_2_DEBUG_ARCH_SUPPORTED #else #define V8_2_DEBUG_ARCH_SUPPORTED DBGDIDR_V8_2_DEBUG_ARCH_SUPPORTED diff --git a/tftf/tests/misc_tests/test_single_fault.c b/tftf/tests/misc_tests/test_single_fault.c index e6522118e..f55d8de8d 100644 --- a/tftf/tests/misc_tests/test_single_fault.c +++ b/tftf/tests/misc_tests/test_single_fault.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,7 @@ #include <sdei.h> #include <tftf_lib.h> -#ifndef AARCH32 +#ifdef __aarch64__ uint64_t serror_received; diff --git a/tftf/tests/misc_tests/test_uncontainable.c b/tftf/tests/misc_tests/test_uncontainable.c index 79c903114..231e5e8cf 100644 --- a/tftf/tests/misc_tests/test_uncontainable.c +++ b/tftf/tests/misc_tests/test_uncontainable.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <tftf_lib.h> -#ifndef AARCH32 +#ifdef __aarch64__ extern void inject_uncontainable(void); diff --git a/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c b/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c index 90a43f33b..e88f183f0 100644 --- a/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c +++ b/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,7 @@ #include <string.h> #include <tftf_lib.h> -#ifdef AARCH64 +#ifdef __aarch64__ #define CORTEX_A57_MIDR 0x410FD070 #define CORTEX_A72_MIDR 0x410FD080 #define CORTEX_A73_MIDR 0x410FD090 diff --git a/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_2.c b/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_2.c index cf36e4f80..1557e4f9a 100644 --- a/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_2.c +++ b/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,7 @@ #include <string.h> #include <tftf_lib.h> -#ifdef AARCH64 +#ifdef __aarch64__ #define NOT_REQUIRED_DONOT_INVOKE -2 #define NOT_SUPPORTED -1 #define IS_REQUIRED 0 @@ -159,4 +159,4 @@ test_result_t test_smccc_arch_workaround_2(void) INFO("%s skipped on AArch32\n", __func__); return TEST_RESULT_SKIPPED; } -#endif /* AARCH64 */ +#endif /* __aarch64__ */ diff --git a/tftf/tests/runtime_services/generic/generic_smc.c b/tftf/tests/runtime_services/generic/generic_smc.c index dc0b10230..6d057a6a8 100644 --- a/tftf/tests/runtime_services/generic/generic_smc.c +++ b/tftf/tests/runtime_services/generic/generic_smc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -236,7 +236,7 @@ test_result_t smc64_yielding(void) return TEST_RESULT_SUCCESS; } -#ifdef AARCH32 +#ifndef __aarch64__ static test_result_t smc64_fast_caller32(void) { /* Valid Fast SMC32 using all 4 return values. */ @@ -295,12 +295,12 @@ static test_result_t smc64_fast_caller64(void) return TEST_RESULT_SUCCESS; } -#endif /* AARCH32 */ +#endif /* !__aarch64__ */ /* Exercise SMC64 calling convention with fast SMC calls. */ test_result_t smc64_fast(void) { -#ifdef AARCH32 +#ifndef __aarch64__ return smc64_fast_caller32(); #else return smc64_fast_caller64(); diff --git a/tftf/tests/runtime_services/sip_service/test_exec_state_switch.c b/tftf/tests/runtime_services/sip_service/test_exec_state_switch.c index 713c8196e..9b272ba5c 100644 --- a/tftf/tests/runtime_services/sip_service/test_exec_state_switch.c +++ b/tftf/tests/runtime_services/sip_service/test_exec_state_switch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -65,7 +65,7 @@ extern int do_state_switch(void *); */ test_result_t test_exec_state_switch_reset_before(void) { -#ifdef AARCH64 +#ifdef __aarch64__ int version; smc_args sip_version_smc = { ARM_SIP_SVC_VERSION }; smc_args reset = { SMC_PSCI_SYSTEM_RESET }; @@ -126,7 +126,7 @@ test_result_t test_exec_state_switch_reset_before(void) */ test_result_t test_exec_state_switch_invalid_pc(void) { -#ifdef AARCH64 +#ifdef __aarch64__ int ret; smc_args args = { @@ -159,7 +159,7 @@ test_result_t test_exec_state_switch_invalid_pc(void) */ test_result_t test_exec_state_switch_invalid_ctx(void) { -#ifdef AARCH64 +#ifdef __aarch64__ int ret; smc_args args = { @@ -191,7 +191,7 @@ test_result_t test_exec_state_switch_invalid_ctx(void) */ test_result_t test_exec_state_switch_valid(void) { -#ifdef AARCH64 +#ifdef __aarch64__ int ret; smc_args args = { @@ -233,7 +233,7 @@ test_result_t test_exec_state_switch_valid(void) */ static inline test_result_t cpu_ping(void) { -#ifdef AARCH64 +#ifdef __aarch64__ /* Tell the lead CPU that the calling CPU has entered the test */ tftf_send_event(&secondary_booted); @@ -254,7 +254,7 @@ static inline test_result_t cpu_ping(void) */ test_result_t test_exec_state_switch_after_cpu_on(void) { -#ifdef AARCH64 +#ifdef __aarch64__ u_register_t other_mpidr, my_mpidr; int ret; diff --git a/tftf/tests/runtime_services/sip_service/test_exec_state_switch_asm.S b/tftf/tests/runtime_services/sip_service/test_exec_state_switch_asm.S index 577f89f7a..d86575600 100644 --- a/tftf/tests/runtime_services/sip_service/test_exec_state_switch_asm.S +++ b/tftf/tests/runtime_services/sip_service/test_exec_state_switch_asm.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,7 @@ #define COOKIE_SIZE 20 -#ifdef AARCH64 +#ifdef __aarch64__ /* int do_state_switch(void *) */ .globl do_state_switch func do_state_switch @@ -167,7 +167,7 @@ state_switch_a32_entry: .word 0xe1600070 /* smc #0x0 */ .word 0xeafffffe /* b . */ -#else /* !AARCH64 */ +#else /* !__aarch64__ */ /* Not supported on AArch32 yet */ func do_state_switch @@ -175,4 +175,4 @@ func do_state_switch bx lr endfunc do_state_switch -#endif /* AARCH64 */ +#endif /* __aarch64__ */ diff --git a/tftf/tests/runtime_services/standard_service/psci/api_tests/affinity_info/test_psci_affinity_info.c b/tftf/tests/runtime_services/standard_service/psci/api_tests/affinity_info/test_psci_affinity_info.c index cc4ad191c..708ea132f 100644 --- a/tftf/tests/runtime_services/standard_service/psci/api_tests/affinity_info/test_psci_affinity_info.c +++ b/tftf/tests/runtime_services/standard_service/psci/api_tests/affinity_info/test_psci_affinity_info.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -293,7 +293,7 @@ test_result_t test_affinity_info_level2(void) */ test_result_t test_affinity_info_level3(void) { -#ifndef AARCH32 +#ifdef __aarch64__ int expected_values[3]; uint64_t target_mpid; int32_t aff_info; diff --git a/tftf/tests/runtime_services/standard_service/sdei/system_tests/sdei_entrypoint.S b/tftf/tests/runtime_services/standard_service/sdei/system_tests/sdei_entrypoint.S index 27ffa39eb..655bb2480 100644 --- a/tftf/tests/runtime_services/standard_service/sdei/system_tests/sdei_entrypoint.S +++ b/tftf/tests/runtime_services/standard_service/sdei/system_tests/sdei_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,7 @@ .local event_handled .comm event_handled, PLATFORM_CORE_COUNT * 4, 8 -#ifdef AARCH64 +#ifdef __aarch64__ func sdei_entrypoint stp xzr, x30, [sp, #-16]! bl sdei_event_handler diff --git a/tftf/tests/xlat_lib_v2/xlat_lib_v2_tests.c b/tftf/tests/xlat_lib_v2/xlat_lib_v2_tests.c index a62bb918a..519ff16b2 100644 --- a/tftf/tests/xlat_lib_v2/xlat_lib_v2_tests.c +++ b/tftf/tests/xlat_lib_v2/xlat_lib_v2_tests.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,7 +67,7 @@ static unsigned long long va2pa(uintptr_t base_va) * Performs stage 1 address translation for the current EL, with * read permissions. */ -#ifdef AARCH32 +#ifndef __aarch64__ if (IS_IN_HYP()) write_ats1hr(base_va); else @@ -497,7 +497,7 @@ test_result_t xlat_lib_v2_basic_test(void) return TEST_RESULT_FAIL; } -#if AARCH64 +#ifdef __aarch64__ unsigned long long memory_base_pa; /* @@ -644,7 +644,7 @@ test_result_t xlat_lib_v2_alignment_test(void) return TEST_RESULT_FAIL; } -#if AARCH64 +#ifdef __aarch64__ /* * 3) Try to allocate at least 1 GB aligned. There is only room for this * in AArch64. diff --git a/tools/generate_dtb/generate_dtb.sh b/tools/generate_dtb/generate_dtb.sh index 20a08d066..84ba88090 100755 --- a/tools/generate_dtb/generate_dtb.sh +++ b/tools/generate_dtb/generate_dtb.sh @@ -75,5 +75,5 @@ INCLUDES="-I spm/cactus -I spm/include -I include/lib" -cpp -x c -P -o "$PREPROCESSED_DTS" "$COMBINED_DTS" ${INCLUDES} -DAARCH64 +cpp -x c -P -o "$PREPROCESSED_DTS" "$COMBINED_DTS" ${INCLUDES} dtc -I dts -O dtb "$PREPROCESSED_DTS" > "$GENERATED_DTB" |