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author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2018-12-18 15:45:01 +0100 |
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committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2019-01-07 16:31:16 +0000 |
commit | dddec6bc4834e4e83c7d6d3a24abcc4dd6b631e5 (patch) | |
tree | 3225788c372e74a584857ad2b4f7cd6515629d09 | |
parent | 9e7d37e7d4de365e56c4a6e1a38950378ae0c841 (diff) | |
download | tf-a-tests-dddec6bc4834e4e83c7d6d3a24abcc4dd6b631e5.tar.gz |
Explain why we set HCR.TGE bit
Change-Id: Id55a62e8610f0b162a26a0eeb8f69e4a87910ed7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
-rw-r--r-- | tftf/framework/aarch32/arch.c | 5 | ||||
-rw-r--r-- | tftf/framework/aarch64/arch.c | 6 |
2 files changed, 11 insertions, 0 deletions
diff --git a/tftf/framework/aarch32/arch.c b/tftf/framework/aarch32/arch.c index 763ea1a13..2d023cd6b 100644 --- a/tftf/framework/aarch32/arch.c +++ b/tftf/framework/aarch32/arch.c @@ -14,5 +14,10 @@ void tftf_arch_setup(void) if (!IS_IN_HYP()) panic(); + /* + * Route physical interrupts to Hyp mode regardless of the value of the + * IMO/FMO bits. Without this, interrupts would not be taken and would + * remain pending, regardless of the PSTATE.{A, I, F} interrupt masks. + */ write_hcr(HCR_TGE_BIT); } diff --git a/tftf/framework/aarch64/arch.c b/tftf/framework/aarch64/arch.c index dfaa9d1bd..0cdfd65c7 100644 --- a/tftf/framework/aarch64/arch.c +++ b/tftf/framework/aarch64/arch.c @@ -10,6 +10,12 @@ void tftf_arch_setup(void) { /* Do not try to configure EL2 if TFTF is running at NS-EL1 */ if (IS_IN_EL2()) { + /* + * Route physical interrupts to EL2 regardless of the value of + * the IMO/FMO bits. Without this, interrupts would not be taken + * and would remain pending, regardless of the PSTATE.{A, I, F} + * interrupt masks. + */ write_hcr_el2(HCR_TGE_BIT); isb(); } |