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#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc

/*
 * Copyright (c) 2017-2018 ARM Limited
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include "region_defs.h"

LR_CODE S_CODE_START {

    /****  This initial section contains common code for TEE */
    ER_TFM_CODE S_CODE_START S_CODE_SIZE {
        *.o (RESET +First)
        .ANY (+RO)
    }

#if TFM_LVL == 1

    ER_TFM_DATA S_DATA_START S_DATA_SIZE {
        .ANY (+RW +ZI)
    }

    TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }

    TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
    }

#else /* TFM_LVL == 1 */

    /**** Unprivileged Secure code start here */
    TFM_UNPRIV_CODE +0 ALIGN 32 {
        tfm_unpriv_api.o (+RO)
        dummy_crypto_keys.o (+RO)
        dummy_nv_counters.o (+RO)
        platform_retarget_dev.o (+RO)
        *(SFN)
        *armlib*
    }

    TFM_SP_STORAGE +0 ALIGN 32 {
        *tfm_storage* (+RO)
        *(TFM_SP_STORAGE_ATTR_FN)
    }

    TFM_SP_AUDIT_LOG +0 ALIGN 32 {
        *tfm_audit* (+RO)
        *(TFM_SP_AUDIT_LOG_ATTR_FN)
    }

    TFM_SP_CRYPTO +0 ALIGN 32 {
        *tfm_crypto* (+RO)
        *(TFM_SP_CRYPTO_ATTR_FN)
    }

    TFM_SP_PLATFORM +0 ALIGN 32 {
        *tfm_platform* (+RO)
        *(TFM_SP_PLATFORM_ATTR_FN)
    }

#ifdef TFM_PARTITION_TEST_CORE
    TFM_SP_CORE_TEST +0 ALIGN 32 {
        *tfm_ss_core_test.* (+RO)
        *(TFM_SP_CORE_TEST_ATTR_FN)
    }

    TFM_SP_CORE_TEST_2 +0 ALIGN 32 {
        *tfm_ss_core_test_2.* (+RO)
        *(TFM_SP_CORE_TEST_2_ATTR_FN)
    }
#endif /* TFM_PARTITION_TEST_CORE */

#ifdef TFM_PARTITION_TEST_SST
    TFM_SP_SST_TEST_PARTITION +0 ALIGN 32 {
        *sst_test_service.* (+RO)
        *(TFM_SP_SST_TEST_PARTITION_ATTR_FN)
    }
#endif /* TFM_PARTITION_TEST_SST */

#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
    TFM_SP_SECURE_TEST_PARTITION +0 ALIGN 32 {
        *tfm_secure_client_service.* (+RO)
        *test_framework* (+RO)
        *uart_stdout.* (+RO)
        *Driver_USART.* (+RO)
        *arm_uart_drv.* (+RO)
        *secure_suites.* (+RO)
        *(TFM_SP_SECURE_TEST_PARTITION_ATTR_FN)
    }
#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */

    ER_TFM_DATA S_DATA_START S_DATA_SIZE {
        .ANY (+RW +ZI)
    }

    TFM_UNPRIV_RO_DATA +0 ALIGN 32 {
        tfm_unpriv_api.o (+RW +ZI)
        dummy_crypto_keys.o (+RW +ZI)
        dummy_nv_counters.o (+RW +ZI)
        platform_retarget_dev.o (+RW +ZI)
    }

    TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
    }

    TFM_SP_STORAGE_DATA +0 ALIGN 32 {
        *tfm_storage* (+RW +ZI)
    }

    TFM_SP_STORAGE_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }

    TFM_SP_AUDIT_LOG_DATA +0 ALIGN 32 {
        *tfm_audit* (+RW +ZI)
    }

    TFM_SP_AUDIT_LOG_STACK +0 ALIGN 128 EMPTY 0x1000 {
    }

    TFM_SP_CRYPTO_DATA +0 ALIGN 32 {
        *tfm_crypto* (+RW +ZI)
    }

    TFM_SP_CRYPTO_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }

    TFM_SP_PLATFORM_DATA +0 ALIGN 32 {
        *tfm_platform* (+RW +ZI)
    }

    TFM_SP_PLATFORM_STACK +0 ALIGN 128 EMPTY 0x0400 {
    }

#ifdef TFM_PARTITION_TEST_CORE
    TFM_SP_CORE_TEST_DATA +0 ALIGN 32 {
        tfm_ss_core_test.o (+RW +ZI)
    }

    TFM_SP_CORE_TEST_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }

    TFM_SP_CORE_TEST_2_DATA +0 ALIGN 32 {
        tfm_ss_core_test_2.o (+RW +ZI)
    }

    TFM_SP_CORE_TEST_2_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }
#endif /* TFM_PARTITION_TEST_CORE */

#ifdef TFM_PARTITION_TEST_SST
    TFM_SP_SST_TEST_PARTITION_DATA +0 ALIGN 32 {
        sst_test_service.o (+RW +ZI)
    }

    TFM_SP_SST_TEST_PARTITION_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }
#endif /* TFM_PARTITION_TEST_SST */

#ifdef TFM_PARTITION_TEST_SECURE_SERVICES
    TFM_SP_SECURE_TEST_PARTITION_DATA +0 ALIGN 32 {
        *tfm_secure_client_service.* (+RW +ZI)
        *test_framework* (+RW +ZI)
        *uart_stdout.* (+RW +ZI)
        *Driver_USART.* (+RW +ZI)
        *arm_uart_drv.* (+RW +ZI)
        *secure_suites.* (+RW +ZI)
    }

    TFM_SP_SECURE_TEST_PARTITION_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }
#endif /* TFM_PARTITION_TEST_SECURE_SERVICES */

#endif /* TFM_LVL == 1 */

}

LR_VENEER CMSE_VENEER_REGION_START {
    /*
     * Place the CMSE Veneers (containing the SG instruction) in a separate
     * 32 bytes aligned region so that the SAU can be programmed to
     * just set this region as Non-Secure Callable.
     */
    ER_CODE_CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
        *(Veneer$$CMSE)
    }
}

LR_NS_PARTITION NS_PARTITION_START {
    /* Reserved place for NS application.
     * No code will be placed here, just address of this region is used in the
     * secure code to configure certain HW components.
     */
    ER_NS_PARTITION NS_PARTITION_START EMPTY NS_PARTITION_SIZE {
    }
}

#ifdef BL2
LR_SECONDARY_PARTITION SECONDARY_PARTITION_START {
    /* Reserved place for new image in case of firmware upgrade.
     * No code will be placed here, just address of this region is used in the
     * secure code to configure certain HW components.
     */
    ER_SECONDARY_PARTITION SECONDARY_PARTITION_START \
        EMPTY SECONDARY_PARTITION_SIZE {
    }
}
#endif /* BL2 */