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authorAlamy Liu <alamy.liu@cypress.com>2019-11-27 09:35:36 -0800
committerDavid Hu <david.hu@arm.com>2020-01-21 08:14:58 +0000
commitc900ad932e4d0208fad4972e525bcf38eb186528 (patch)
tree1f007d316736cbb9dc8794aa486483433c903880
parent2b632e2886de711e965ecee0e5b84e1ceb249259 (diff)
downloadtrusted-firmware-m-c900ad932e4d0208fad4972e525bcf38eb186528.tar.gz
Platform: PSoC64: S-IRQ: enable Clocks for TCPWM0 Counters
Change-Id: I363bac5182403b1a76709d4f23e9435405ec117b Signed-off-by: Alamy Liu <alamy.liu@cypress.com>
-rw-r--r--platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.c b/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.c
index 811b944fa..98e764f65 100644
--- a/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.c
+++ b/platform/ext/target/cypress/psoc64/Native_Driver/generated_source/cycfg_peripherals.c
@@ -8,7 +8,7 @@
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
*
********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2017-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -55,7 +55,7 @@ const cy_stc_scb_uart_config_t KITPROG_UART_config =
.txFifoIntEnableMask = 0UL,
};
-cy_stc_csd_context_t cy_csd_0_context =
+cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
@@ -65,4 +65,8 @@ void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
+ /* Secure: TIMER0 */
+ Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 1U);
+ /* Non-Secure: TIMER1 */
+ Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 1U);
}