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authorTamas Kaman <tamas.kaman@arm.com>2019-11-21 15:46:19 +0100
committerMáté Tóth-Pál <Mate.Toth-Pal@arm.com>2019-12-09 13:18:55 +0000
commit8354051be3cae5ab5520a6eee9eeda99042bbcf1 (patch)
treec7345512b585869a717f14fb6c8666fc421ca430
parenta642cd29eff2d0065acbf6a501f642c6b01f4c0a (diff)
downloadtrusted-firmware-m-8354051be3cae5ab5520a6eee9eeda99042bbcf1.tar.gz
Platform: Fix QSPI uninit for Musca-A platform
Current QSPI uninit puts QSPI flash into an invalid state which can cause an issue if the core is soft resetted as code fetch will fail from Flash. This commit fixes uninit and puts flash into a proper state where direct read still works. Change-Id: I56ad948641c1bf2354cc239df4a5a4c32fcd63db Signed-off-by: Tamas Kaman <tamas.kaman@arm.com>
-rw-r--r--platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c4
-rw-r--r--platform/ext/target/musca_a/Device/Source/device_definition.c2
-rw-r--r--platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.c202
-rw-r--r--platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.h45
-rw-r--r--platform/ext/target/musca_a/Native_Driver/qspi_ip6514e_drv.c6
-rw-r--r--platform/ext/target/musca_b1/Device/Source/device_definition.c4
6 files changed, 122 insertions, 141 deletions
diff --git a/platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c b/platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c
index 9a32afbe30..b29f03f49c 100644
--- a/platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c
+++ b/platform/ext/target/musca_a/CMSIS_Driver/Driver_QSPI_Flash.c
@@ -156,8 +156,8 @@ static int32_t ARM_Flash_Uninitialize(void)
{
enum mt25ql_error_t err = MT25QL_ERR_NONE;
- /* Restores the QSPI Flash controller and MT25QL to default state */
- err = mt25ql_restore_default_state(ARM_FLASH0_DEV.dev);
+ /* Restores the QSPI Flash controller and MT25QL to reset state */
+ err = mt25ql_restore_reset_state(ARM_FLASH0_DEV.dev);
if(err != MT25QL_ERR_NONE) {
return ARM_DRIVER_ERROR;
}
diff --git a/platform/ext/target/musca_a/Device/Source/device_definition.c b/platform/ext/target/musca_a/Device/Source/device_definition.c
index 5a9f3da562..8aa430d688 100644
--- a/platform/ext/target/musca_a/Device/Source/device_definition.c
+++ b/platform/ext/target/musca_a/Device/Source/device_definition.c
@@ -620,6 +620,7 @@ struct mt25ql_dev_t MT25QL_DEV_S = {
* more.
*/
.size = 0x00800000U, /* 8 MiB */
+ .config_state = { 0 },
};
#endif
@@ -636,5 +637,6 @@ struct mt25ql_dev_t MT25QL_DEV_NS
* more.
*/
.size = 0x00800000U, /* 8 MiB */
+ .config_state = { 0 },
};
#endif
diff --git a/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.c b/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.c
index cddb48734a..578cc5b376 100644
--- a/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.c
+++ b/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 Arm Limited
+ * Copyright (c) 2018-2019 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -19,7 +19,7 @@
#include <string.h>
#include "mt25ql_flash_lib.h"
-#include "Native_Driver/qspi_ip6514e_drv.h"
+#include "qspi_ip6514e_drv.h"
/** Setter bit manipulation macro */
#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX)))
@@ -70,11 +70,12 @@
#define FLAG_STATUS_REG_READY_POS 7U
/*
- * 8 is the minimal number of dummy clock cycles needed to reach the maximal
+ * 10 is the minimal number of dummy clock cycles needed to reach the maximal
* frequency of the Quad Output Fast Read Command.
*/
-#define QUAD_OUTPUT_FAST_READ_DUMMY_CYCLES 8U
+#define QUAD_OUTPUT_FAST_READ_DUMMY_CYCLES 10U
#define FAST_READ_DUMMY_CYCLES 8U
+#define RESET_STATE_DUMMY_CYCLES 8U
#define DEFAULT_READ_DUMMY_CYCLES 0U
#define QUAD_INPUT_FAST_PROGRAM_DUMMY_CYCLES 0U
#define PAGE_PROGRAM_DUMMY_CYCLES 0U
@@ -356,12 +357,9 @@ static enum mt25ql_error_t send_boundary_cross_write_cmd(
uint32_t page_remainder = FLASH_PAGE_SIZE - (addr % FLASH_PAGE_SIZE);
/* First write up to the end of the current page. */
- controller_error = qspi_ip6514e_send_write_cmd(dev->controller,
- opcode,
- write_data,
- page_remainder,
- addr,
- addr_bytes_number,
+ controller_error = qspi_ip6514e_send_write_cmd(dev->controller, opcode,
+ write_data, page_remainder,
+ addr, addr_bytes_number,
dummy_cycles);
if (controller_error != QSPI_IP6514E_ERR_NONE) {
return (enum mt25ql_error_t)controller_error;
@@ -378,12 +376,10 @@ static enum mt25ql_error_t send_boundary_cross_write_cmd(
/* Then write the remaining data of the write_len bytes. */
send_write_enable(dev);
- controller_error = qspi_ip6514e_send_write_cmd(dev->controller,
- opcode,
+ controller_error = qspi_ip6514e_send_write_cmd(dev->controller, opcode,
write_data,
write_len - page_remainder,
- addr,
- addr_bytes_number,
+ addr, addr_bytes_number,
dummy_cycles);
if (controller_error != QSPI_IP6514E_ERR_NONE) {
return (enum mt25ql_error_t)controller_error;
@@ -393,53 +389,53 @@ static enum mt25ql_error_t send_boundary_cross_write_cmd(
}
enum mt25ql_error_t mt25ql_config_mode(struct mt25ql_dev_t* dev,
- enum mt25ql_functional_state_t config)
+ enum mt25ql_functional_state_t f_state)
{
- enum qspi_ip6514e_spi_mode_t spi_mode;
enum qspi_ip6514e_error_t controller_error;
enum mt25ql_error_t library_error;
- uint8_t opcode_read;
- uint8_t opcode_write;
- uint32_t dummy_cycles_read;
- uint32_t dummy_cycles_write;
- switch(config) {
+ switch(f_state) {
case MT25QL_FUNC_STATE_DEFAULT:
- spi_mode = QSPI_IP6514E_SPI_MODE;
- opcode_read = READ_CMD;
- dummy_cycles_read = DEFAULT_READ_DUMMY_CYCLES;
- opcode_write = PAGE_PROGRAM_CMD;
- dummy_cycles_write = PAGE_PROGRAM_DUMMY_CYCLES;
+ dev->config_state.spi_mode = QSPI_IP6514E_SPI_MODE;
+ dev->config_state.opcode_read = READ_CMD;
+ dev->config_state.dummy_cycles_read = DEFAULT_READ_DUMMY_CYCLES;
+ dev->config_state.opcode_write = PAGE_PROGRAM_CMD;
+ dev->config_state.dummy_cycles_write = PAGE_PROGRAM_DUMMY_CYCLES;
break;
case MT25QL_FUNC_STATE_FAST:
- spi_mode = QSPI_IP6514E_SPI_MODE;
- opcode_read = FAST_READ_CMD;
- dummy_cycles_read = FAST_READ_DUMMY_CYCLES;
- opcode_write = PAGE_PROGRAM_CMD;
- dummy_cycles_write = PAGE_PROGRAM_DUMMY_CYCLES;
+ dev->config_state.spi_mode = QSPI_IP6514E_SPI_MODE;
+ dev->config_state.opcode_read = FAST_READ_CMD;
+ dev->config_state.dummy_cycles_read = FAST_READ_DUMMY_CYCLES;
+ dev->config_state.opcode_write = PAGE_PROGRAM_CMD;
+ dev->config_state.dummy_cycles_write = PAGE_PROGRAM_DUMMY_CYCLES;
break;
case MT25QL_FUNC_STATE_QUAD_FAST:
- spi_mode = QSPI_IP6514E_QSPI_MODE;
- opcode_read = QUAD_OUTPUT_FAST_READ_CMD;
- dummy_cycles_read = QUAD_OUTPUT_FAST_READ_DUMMY_CYCLES;
- opcode_write = QUAD_INPUT_FAST_PROGRAM_CMD;
- dummy_cycles_write = QUAD_INPUT_FAST_PROGRAM_DUMMY_CYCLES;
+ dev->config_state.spi_mode = QSPI_IP6514E_QSPI_MODE;
+ dev->config_state.opcode_read = QUAD_OUTPUT_FAST_READ_CMD;
+ dev->config_state.dummy_cycles_read =
+ QUAD_OUTPUT_FAST_READ_DUMMY_CYCLES;
+ dev->config_state.opcode_write = QUAD_INPUT_FAST_PROGRAM_CMD;
+ dev->config_state.dummy_cycles_write =
+ QUAD_INPUT_FAST_PROGRAM_DUMMY_CYCLES;
break;
default:
return MT25QL_ERR_WRONG_ARGUMENT;
}
+ dev->config_state.func_state = f_state;
+
/* This function will first set the Flash memory SPI mode and then set
* the controller's SPI mode. It will fail if the two sides do not have
* the same mode when this function is called.
*/
- library_error = set_spi_mode(dev, spi_mode);
+ library_error = set_spi_mode(dev, dev->config_state.spi_mode);
if (library_error != MT25QL_ERR_NONE) {
return library_error;
}
/* Set the number of dummy cycles for read commands. */
- library_error = change_dummy_cycles(dev, dummy_cycles_read);
+ library_error = change_dummy_cycles(
+ dev, dev->config_state.dummy_cycles_read);
if (library_error != MT25QL_ERR_NONE) {
return library_error;
}
@@ -456,17 +452,17 @@ enum mt25ql_error_t mt25ql_config_mode(struct mt25ql_dev_t* dev,
}
/* Set opcode and dummy cycles needed for read commands. */
- controller_error = qspi_ip6514e_cfg_reads(dev->controller,
- opcode_read,
- dummy_cycles_read);
+ controller_error = qspi_ip6514e_cfg_reads(
+ dev->controller, dev->config_state.opcode_read,
+ dev->config_state.dummy_cycles_read);
if (controller_error != QSPI_IP6514E_ERR_NONE) {
return (enum mt25ql_error_t)controller_error;
}
/* Set opcode and dummy cycles needed for write commands. */
- controller_error = qspi_ip6514e_cfg_writes(dev->controller,
- opcode_write,
- dummy_cycles_write);
+ controller_error = qspi_ip6514e_cfg_writes(
+ dev->controller, dev->config_state.opcode_write,
+ dev->config_state.dummy_cycles_write);
if (controller_error != QSPI_IP6514E_ERR_NONE) {
return (enum mt25ql_error_t)controller_error;
}
@@ -486,12 +482,10 @@ enum mt25ql_error_t mt25ql_config_mode(struct mt25ql_dev_t* dev,
qspi_ip6514e_enable(dev->controller);
- dev->func_state = config;
-
return MT25QL_ERR_NONE;
}
-enum mt25ql_error_t mt25ql_restore_default_state(struct mt25ql_dev_t* dev)
+enum mt25ql_error_t mt25ql_restore_reset_state(struct mt25ql_dev_t* dev)
{
enum mt25ql_error_t library_error;
@@ -505,8 +499,8 @@ enum mt25ql_error_t mt25ql_restore_default_state(struct mt25ql_dev_t* dev)
return library_error;
}
- /* Set the default number of dummy cycles for read commands. */
- library_error = change_dummy_cycles(dev, DEFAULT_READ_DUMMY_CYCLES);
+ /* Set the default number of dummy cycles for direct read commands. */
+ library_error = change_dummy_cycles(dev, RESET_STATE_DUMMY_CYCLES);
if (library_error != MT25QL_ERR_NONE) {
return library_error;
}
@@ -520,7 +514,8 @@ enum mt25ql_error_t mt25ql_restore_default_state(struct mt25ql_dev_t* dev)
qspi_ip6514e_enable(dev->controller);
- dev->func_state = MT25QL_FUNC_STATE_DEFAULT;
+ dev->config_state = (struct mt25ql_config_state_t){ 0 };
+ dev->config_state.func_state = MT25QL_FUNC_STATE_NOT_INITED;
return MT25QL_ERR_NONE;
}
@@ -698,34 +693,18 @@ enum mt25ql_error_t mt25ql_command_read(struct mt25ql_dev_t* dev,
/* With one single command only 8 bytes can be read. */
uint32_t cmd_number = len / CMD_DATA_MAX_SIZE;
enum qspi_ip6514e_error_t controller_error;
- uint8_t opcode;
- uint32_t dummy_cycles;
- switch (dev->func_state) {
- case MT25QL_FUNC_STATE_QUAD_FAST:
- opcode = QUAD_OUTPUT_FAST_READ_CMD;
- dummy_cycles = QUAD_OUTPUT_FAST_READ_DUMMY_CYCLES;
- break;
- case MT25QL_FUNC_STATE_FAST:
- opcode = FAST_READ_CMD;
- dummy_cycles = FAST_READ_DUMMY_CYCLES;
- break;
- case MT25QL_FUNC_STATE_DEFAULT:
- default:
- opcode = READ_CMD;
- dummy_cycles = DEFAULT_READ_DUMMY_CYCLES;
- break;
+ if (dev->config_state.func_state == MT25QL_FUNC_STATE_NOT_INITED) {
+ return MT25QL_ERR_NOT_INITED;
}
for (uint32_t cmd_index = 0; cmd_index < cmd_number; cmd_index++) {
controller_error = qspi_ip6514e_send_read_cmd(
- dev->controller,
- opcode,
- data,
- CMD_DATA_MAX_SIZE,
- addr,
- ADDR_BYTES,
- dummy_cycles);
+ dev->controller,
+ dev->config_state.opcode_read,
+ data, CMD_DATA_MAX_SIZE, addr,
+ ADDR_BYTES,
+ dev->config_state.dummy_cycles_read);
if (controller_error != QSPI_IP6514E_ERR_NONE) {
return (enum mt25ql_error_t)controller_error;
}
@@ -738,19 +717,17 @@ enum mt25ql_error_t mt25ql_command_read(struct mt25ql_dev_t* dev,
if (len) {
/* Read the remainder. */
controller_error = qspi_ip6514e_send_read_cmd(
- dev->controller,
- opcode,
- data,
- len,
- addr,
- ADDR_BYTES,
- dummy_cycles);
+ dev->controller,
+ dev->config_state.opcode_read,
+ data, len, addr, ADDR_BYTES,
+ dev->config_state.dummy_cycles_read);
if (controller_error != QSPI_IP6514E_ERR_NONE) {
return (enum mt25ql_error_t)controller_error;
}
}
return MT25QL_ERR_NONE;
+
}
enum mt25ql_error_t mt25ql_command_write(struct mt25ql_dev_t* dev,
@@ -762,20 +739,9 @@ enum mt25ql_error_t mt25ql_command_write(struct mt25ql_dev_t* dev,
uint32_t cmd_number = len / CMD_DATA_MAX_SIZE;
enum qspi_ip6514e_error_t controller_error;
enum mt25ql_error_t library_error;
- uint8_t opcode;
- uint32_t dummy_cycles;
- switch (dev->func_state) {
- case MT25QL_FUNC_STATE_QUAD_FAST:
- opcode = QUAD_INPUT_FAST_PROGRAM_CMD;
- dummy_cycles = QUAD_INPUT_FAST_PROGRAM_DUMMY_CYCLES;
- break;
- case MT25QL_FUNC_STATE_FAST:
- case MT25QL_FUNC_STATE_DEFAULT:
- default:
- opcode = PAGE_PROGRAM_CMD;
- dummy_cycles = PAGE_PROGRAM_DUMMY_CYCLES;
- break;
+ if (dev->config_state.func_state == MT25QL_FUNC_STATE_NOT_INITED) {
+ return MT25QL_ERR_NOT_INITED;
}
for (uint32_t cmd_index = 0; cmd_index < cmd_number; cmd_index++) {
@@ -789,26 +755,21 @@ enum mt25ql_error_t mt25ql_command_write(struct mt25ql_dev_t* dev,
((addr + CMD_DATA_MAX_SIZE - 1) / FLASH_PAGE_SIZE)) {
/* The CMD_DATA_MAX_SIZE bytes written are crossing the boundary. */
library_error = send_boundary_cross_write_cmd(
- dev,
- opcode,
- data,
- CMD_DATA_MAX_SIZE,
- addr,
- ADDR_BYTES,
- dummy_cycles);
+ dev, dev->config_state.opcode_write,
+ data, CMD_DATA_MAX_SIZE, addr,
+ ADDR_BYTES,
+ dev->config_state.dummy_cycles_write);
if (library_error != MT25QL_ERR_NONE) {
return library_error;
}
} else {
/* Normal case: not crossing the boundary. */
controller_error = qspi_ip6514e_send_write_cmd(
- dev->controller,
- opcode,
- data,
- CMD_DATA_MAX_SIZE,
- addr,
- ADDR_BYTES,
- dummy_cycles);
+ dev->controller,
+ dev->config_state.opcode_write,
+ data, CMD_DATA_MAX_SIZE, addr,
+ ADDR_BYTES,
+ dev->config_state.dummy_cycles_write);
if (controller_error != QSPI_IP6514E_ERR_NONE) {
return (enum mt25ql_error_t)controller_error;
}
@@ -835,26 +796,19 @@ enum mt25ql_error_t mt25ql_command_write(struct mt25ql_dev_t* dev,
if ((addr / FLASH_PAGE_SIZE) != ((addr + len - 1) / FLASH_PAGE_SIZE)) {
/* The CMD_DATA_MAX_SIZE bytes written are crossing the boundary. */
library_error = send_boundary_cross_write_cmd(
- dev,
- opcode,
- data,
- len,
- addr,
- ADDR_BYTES,
- dummy_cycles);
+ dev, dev->config_state.opcode_write,
+ data, len, addr, ADDR_BYTES,
+ dev->config_state.dummy_cycles_write);
if (library_error != MT25QL_ERR_NONE) {
return library_error;
}
} else {
/* Normal case: not crossing the boundary. */
controller_error = qspi_ip6514e_send_write_cmd(
- dev->controller,
- opcode,
- data,
- len,
- addr,
- ADDR_BYTES,
- dummy_cycles);
+ dev->controller,
+ dev->config_state.opcode_write,
+ data, len, addr, ADDR_BYTES,
+ dev->config_state.dummy_cycles_write);
if (controller_error != QSPI_IP6514E_ERR_NONE) {
return (enum mt25ql_error_t)controller_error;
}
@@ -867,8 +821,8 @@ enum mt25ql_error_t mt25ql_command_write(struct mt25ql_dev_t* dev,
}
}
-
return MT25QL_ERR_NONE;
+
}
enum mt25ql_error_t mt25ql_erase(struct mt25ql_dev_t* dev,
@@ -880,6 +834,10 @@ enum mt25ql_error_t mt25ql_erase(struct mt25ql_dev_t* dev,
uint8_t erase_cmd;
uint32_t addr_bytes;
+ if (dev->config_state.func_state == MT25QL_FUNC_STATE_NOT_INITED) {
+ return MT25QL_ERR_NOT_INITED;
+ }
+
send_write_enable(dev);
switch (erase_type) {
diff --git a/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.h b/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.h
index f081fb2ce4..c2dac2ca21 100644
--- a/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.h
+++ b/platform/ext/target/musca_a/Libraries/mt25ql_flash_lib.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 Arm Limited
+ * Copyright (c) 2018-2019 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -22,7 +22,7 @@
#ifndef __MT25QL_H__
#define __MT25QL_H__
-#include "Native_Driver/qspi_ip6514e_drv.h"
+#include "qspi_ip6514e_drv.h"
#ifdef __cplusplus
extern "C" {
@@ -44,6 +44,7 @@ enum mt25ql_error_t {
MT25QL_ERR_READ_IN_PROGRESS = QSPI_IP6514E_ERR_READ_IN_PROGRESS,
MT25QL_ERR_WRITE_IN_PROGRESS = QSPI_IP6514E_ERR_WRITE_IN_PROGRESS,
MT25QL_ERR_ADDR_NOT_ALIGNED,
+ MT25QL_ERR_NOT_INITED,
MT25QL_ERR_ADDR_TOO_BIG,
};
@@ -55,22 +56,41 @@ enum mt25ql_erase_t {
};
enum mt25ql_functional_state_t {
- MT25QL_FUNC_STATE_DEFAULT = 0U,
+ MT25QL_FUNC_STATE_NOT_INITED = 0U,
+ /*!< QSPI Flash controller is not initialized, only direct read
+ * is guaranteed to be working
+ */
+ MT25QL_FUNC_STATE_DEFAULT = 1U,
/*!< The QSPI Flash controller and memory is in default state,
- * in the same state as after reset.
+ * using basic read/write commands
*/
- MT25QL_FUNC_STATE_FAST = 1U,
+ MT25QL_FUNC_STATE_FAST = 2U,
/*!< The QSPI Flash controller and memory is configured to operate in
* single SPI mode and fast Flash commands could be used for read and
* program operations.
*/
- MT25QL_FUNC_STATE_QUAD_FAST = 2U,
+ MT25QL_FUNC_STATE_QUAD_FAST = 3U,
/*!< The QSPI Flash controller and memory is configured to operate in
* Quad SPI mode and fast Flash commands could be used for read and
* program operations.
*/
};
+struct mt25ql_config_state_t {
+ enum mt25ql_functional_state_t func_state;
+ /*!< Functional state id */
+ enum qspi_ip6514e_spi_mode_t spi_mode;
+ /*!< SPI mode for the current functional state */
+ uint8_t opcode_read;
+ /*!< Read opcode for the current functional state */
+ uint8_t opcode_write;
+ /*!< Write opcode for the current functional state */
+ uint32_t dummy_cycles_read;
+ /*!< Dummy cycles for the read command for the current functional state */
+ uint32_t dummy_cycles_write;
+ /*!< Dummy cycles for the write command for the current functional state */
+};
+
struct mt25ql_dev_t {
struct qspi_ip6514e_dev_t *controller;
/*!< QSPI Flash controller. */
@@ -87,10 +107,11 @@ struct mt25ql_dev_t {
* dummy cycles and the Quad Input Fast Program with 0 dummy cycles.
*/
uint32_t size; /*!< Total size of the MT25QL Flash memory */
- enum mt25ql_functional_state_t func_state;
- /*!< Functional state (operational parameter settings) of the
+ struct mt25ql_config_state_t config_state;
+ /*!< Configured functional state (with parameter settings) of the
* QSPI Flash controller and memory.
*/
+
};
/**
@@ -105,7 +126,7 @@ struct mt25ql_dev_t {
* + The number of address bytes to 3
*
* \param[in] dev Pointer to MT25QL device structure \ref mt25ql_dev_t
- * \param[in] config Operational configuration to be set on flash controller
+ * \param[in] f_state Functional state to be set on flash controller
* and device \ref mt25ql_functional_state_t
*
* \return Return error code as specified in \ref mt25ql_error_t
@@ -115,10 +136,10 @@ struct mt25ql_dev_t {
* if the Flash device is in a different configuration.
*/
enum mt25ql_error_t mt25ql_config_mode(struct mt25ql_dev_t* dev,
- enum mt25ql_functional_state_t config);
+ enum mt25ql_functional_state_t f_state);
/**
- * \brief Restore the QSPI Flash controller and MT25QL to default state.
+ * \brief Restore the QSPI Flash controller and MT25QL to reset state.
*
* \param[in] dev Pointer to MT25QL device structure \ref mt25ql_dev_t
*
@@ -128,7 +149,7 @@ enum mt25ql_error_t mt25ql_config_mode(struct mt25ql_dev_t* dev,
* controller operates with the same SPI protocol. This function will fail
* if the Flash device is in a different configuration.
*/
-enum mt25ql_error_t mt25ql_restore_default_state(struct mt25ql_dev_t* dev);
+enum mt25ql_error_t mt25ql_restore_reset_state(struct mt25ql_dev_t* dev);
/**
* \brief Read bytes from the flash memory (direct access)
diff --git a/platform/ext/target/musca_a/Native_Driver/qspi_ip6514e_drv.c b/platform/ext/target/musca_a/Native_Driver/qspi_ip6514e_drv.c
index 4b585e5841..bb13a4219b 100644
--- a/platform/ext/target/musca_a/Native_Driver/qspi_ip6514e_drv.c
+++ b/platform/ext/target/musca_a/Native_Driver/qspi_ip6514e_drv.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 Arm Limited
+ * Copyright (c) 2018-2019 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -126,8 +126,8 @@ struct _qspi_ip6514e_reg_map_t {
#define FLASH_CMD_CTRL_OPCODE_POS 24U
/** Default register values of the QSPI Flash controller */
-#define QSPI_CFG_REG_RESET_VALUE (0x80780081U)
-#define DEVICE_READ_INSTR_REG_RESET_VALUE (0x00000003U)
+#define QSPI_CFG_REG_RESET_VALUE (0x80080080U)
+#define DEVICE_READ_INSTR_REG_RESET_VALUE (0x080220EBU)
#define DEVICE_WRITE_INSTR_REG_RESET_VALUE (0x00000002U)
#define DEVICE_SIZE_CFG_REG_RESET_VALUE (0x00101002U)
#define REMAP_ADDR_REG_RESET_VALUE (0x00000000U)
diff --git a/platform/ext/target/musca_b1/Device/Source/device_definition.c b/platform/ext/target/musca_b1/Device/Source/device_definition.c
index 56f8018464..165d2033ec 100644
--- a/platform/ext/target/musca_b1/Device/Source/device_definition.c
+++ b/platform/ext/target/musca_b1/Device/Source/device_definition.c
@@ -461,7 +461,7 @@ struct mt25ql_dev_t MT25QL_DEV_S = {
* more.
*/
.size = 0x00800000U, /* 8 MiB */
- .func_state = MT25QL_FUNC_STATE_DEFAULT,
+ .config_state = { 0 },
};
#endif
@@ -476,6 +476,6 @@ struct mt25ql_dev_t MT25QL_DEV_NS = {
* more.
*/
.size = 0x00800000U, /* 8 MiB */
- .func_state = MT25QL_FUNC_STATE_DEFAULT,
+ .config_state = { 0 },
};
#endif