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authorAlamy Liu <alamy.liu@cypress.com>2019-11-21 19:36:59 -0800
committerDavid Hu <david.hu@arm.com>2020-01-21 08:14:58 +0000
commit085cc98f11db17323d0213fc4ea0b64cc605c3fd (patch)
tree8512253ec9e8a4a3d1f812af97f1cb509c57b0fb
parent044d7ffcc8c9cf435a6dd0c309b6014a2a1e1682 (diff)
downloadtrusted-firmware-m-085cc98f11db17323d0213fc4ea0b64cc605c3fd.tar.gz
Platform: PSoC64: S-IRQ: Define CY_TCPWM0_TIMERx
Define timer structures to be used for IRQ test CY_TCPWM0_TIMER0_S: Secure environment timer CY_TCPWM0_TIMER1_NS: Non-Secure environment timer Change-Id: Ic7d4e276e57619538374e55bd3ca5b22ddf02987 Signed-off-by: Alamy Liu <alamy.liu@cypress.com>
-rw-r--r--platform/ext/target/cypress/psoc64/Device/Config/device_cfg.h5
-rw-r--r--platform/ext/target/cypress/psoc64/Device/Include/device_definition.h23
-rw-r--r--platform/ext/target/cypress/psoc64/Device/Source/device_definition.c86
3 files changed, 84 insertions, 30 deletions
diff --git a/platform/ext/target/cypress/psoc64/Device/Config/device_cfg.h b/platform/ext/target/cypress/psoc64/Device/Config/device_cfg.h
index 531f92621..d3d0c155c 100644
--- a/platform/ext/target/cypress/psoc64/Device/Config/device_cfg.h
+++ b/platform/ext/target/cypress/psoc64/Device/Config/device_cfg.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2017-2018 Arm Limited
+ * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -27,6 +28,10 @@
* This is a default device configuration file with all peripherals enabled.
*/
+/* TCPWM0 Timers (IRQ test) */
+#define CY_TCPWM0_TIMER0_S
+#define CY_TCPWM0_TIMER1_NS
+
#define DEFAULT_UART_BAUDRATE 115200
#endif /* __ARM_LTD_DEVICE_CFG_H__ */
diff --git a/platform/ext/target/cypress/psoc64/Device/Include/device_definition.h b/platform/ext/target/cypress/psoc64/Device/Include/device_definition.h
index 981a0e05f..efa3d3fce 100644
--- a/platform/ext/target/cypress/psoc64/Device/Include/device_definition.h
+++ b/platform/ext/target/cypress/psoc64/Device/Include/device_definition.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2017-2018 Arm Limited
+ * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -50,4 +51,26 @@ extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S;
extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS;
#endif
+#if defined(CY_TCPWM0_TIMER0_S) || defined(CY_TCPWM0_TIMER1_NS)
+#include "cy_tcpwm_counter.h"
+typedef struct tfm_timer_irq_test_dev {
+ bool is_initialized;
+ TCPWM_Type *tcpwm_base;
+ uint32_t tcpwm_counter_num;
+ uint32_t timer_match_value;
+ cy_stc_tcpwm_counter_config_t *tcpwm_config;
+} tfm_timer_irq_test_dev_t;
+#endif
+#ifdef CY_TCPWM0_TIMER0_S
+#include "cy_sysint.h"
+extern cy_stc_sysint_t CY_TCPWM_NVIC_CFG_S;
+extern void TFM_TIMER0_IRQ_Handler(void);
+extern tfm_timer_irq_test_dev_t CY_TCPWM0_TIMER0_DEV_S;
+#define TIMER0_MATCH (1000000 / 8) /* About 1 seconds (CM0+: 50MHz) */
+#endif
+#ifdef CY_TCPWM0_TIMER1_NS
+extern tfm_timer_irq_test_dev_t CY_TCPWM0_TIMER1_DEV_NS;
+#define TIMER1_MATCH (1000000 / 8) /* About 2 seconds (CM4: 100MHz) */
+#endif
+
#endif /* __DEVICE_DEFINITION_H__ */
diff --git a/platform/ext/target/cypress/psoc64/Device/Source/device_definition.c b/platform/ext/target/cypress/psoc64/Device/Source/device_definition.c
index b11f5b2a2..af6ac12c2 100644
--- a/platform/ext/target/cypress/psoc64/Device/Source/device_definition.c
+++ b/platform/ext/target/cypress/psoc64/Device/Source/device_definition.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2018 ARM Limited
+ * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -25,39 +26,64 @@
#include "device_definition.h"
#include "platform_base_address.h"
+#include "tfm_peripherals_def.h"
+#include "tfm_plat_defs.h"
-/* CMSDK Timer driver structures */
-#ifdef CMSDK_TIMER0_S
-static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = {
- .base = CMSDK_TIMER0_BASE_S};
-static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_S = {
- .is_initialized = 0};
-struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S = {&(CMSDK_TIMER0_DEV_CFG_S),
- &(CMSDK_TIMER0_DEV_DATA_S)};
-#endif
-#ifdef CMSDK_TIMER0_NS
-static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = {
- .base = CMSDK_TIMER0_BASE_NS};
-static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = {
- .is_initialized = 0};
-struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS = {&(CMSDK_TIMER0_DEV_CFG_NS),
- &(CMSDK_TIMER0_DEV_DATA_NS)};
+/* TCPWM Timer driver structures */
+#if defined(CY_TCPWM0_TIMER0_S) || defined(CY_TCPWM0_TIMER1_NS)
+/* Sharing the tcpwm configuration data, as the IRQ test runs in sequence */
+cy_stc_tcpwm_counter_config_t tcpwm_config
+ TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_IRQ_TEST_1")
+ = {
+ .period = TIMER0_MATCH, /* Upper limit (wrap around) */
+ .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_8, /* Clk_counter = Clk_input / 8 */
+ .runMode = CY_TCPWM_COUNTER_CONTINUOUS, /* Wrap around */
+ .countDirection = CY_TCPWM_COUNTER_COUNT_UP,
+ .compareOrCapture = CY_TCPWM_COUNTER_MODE_COMPARE,/* match compare0 */
+ .compare0 = TIMER0_MATCH,
+ .compare1 = 0,
+ .enableCompareSwap = false, /* swap compare0 & compare1 upon compare event */
+ .interruptSources = CY_TCPWM_INT_ON_CC,
+ .captureInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */
+ .captureInput = CY_TCPWM_INPUT_0,
+ .reloadInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */
+ .reloadInput = CY_TCPWM_INPUT_0,
+ .startInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */
+ .startInput = CY_TCPWM_INPUT_0,
+ .stopInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* NOT used */
+ .stopInput = CY_TCPWM_INPUT_0,
+ .countInputMode = CY_TCPWM_INPUT_LEVEL,
+ .countInput = CY_TCPWM_INPUT_1, /* count Clk_counter */
+};
#endif
-#ifdef CMSDK_TIMER1_S
-static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = {
- .base = CMSDK_TIMER1_BASE_S};
-static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_S = {
- .is_initialized = 0};
-struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S = {&(CMSDK_TIMER1_DEV_CFG_S),
- &(CMSDK_TIMER1_DEV_DATA_S)};
+#ifdef CY_TCPWM0_TIMER0_S
+#if (CY_CPU_CORTEX_M0P)
+cy_stc_sysint_t CY_TCPWM_NVIC_CFG_S
+ TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_IRQ_TEST_1")
+ = {
+ .intrSrc = TFM_TIMER0_IRQ, /* NVIC #3 */
+ .cm0pSrc = tcpwm_0_interrupts_0_IRQn, /* IRQ 123 */
+ .intrPriority = 2U, /* ?: Flash is 0U, IPC is 1U */
+};
#endif
-#ifdef CMSDK_TIMER1_NS
-static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = {
- .base = CMSDK_TIMER1_BASE_NS};
-static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = {
- .is_initialized = 0};
-struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS = {&(CMSDK_TIMER1_DEV_CFG_NS),
- &(CMSDK_TIMER1_DEV_DATA_NS)};
+tfm_timer_irq_test_dev_t CY_TCPWM0_TIMER0_DEV_S
+ TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_IRQ_TEST_1")
+ = {
+ .is_initialized = false,
+ .tcpwm_base = TCPWM0,
+ .tcpwm_counter_num = 0,
+ .timer_match_value = TIMER0_MATCH,
+ .tcpwm_config = &tcpwm_config,
+};
#endif
+#ifdef CY_TCPWM0_TIMER1_NS
+tfm_timer_irq_test_dev_t CY_TCPWM0_TIMER1_DEV_NS = {
+ .is_initialized = false,
+ .tcpwm_base = TCPWM0,
+ .tcpwm_counter_num = 1,
+ .timer_match_value = TIMER1_MATCH,
+ .tcpwm_config = &tcpwm_config,
+};
+#endif