diff options
author | Edison Ai <edison.ai@arm.com> | 2019-02-27 16:56:16 +0800 |
---|---|---|
committer | Edison Ai <edison.ai@arm.com> | 2019-02-27 17:05:07 +0800 |
commit | f876e5cf4aae95d471d5a566cab18706668d6652 (patch) | |
tree | afa0f3530805737a16810398d8a0a9ca321cdb47 | |
parent | 7595dc872c9dadb5843c6442221c78da82884bc4 (diff) | |
download | trusted-firmware-m-feature-ipc.tar.gz |
Platform: Correct region namefeature-ipc
Change "TFM_DATA" to "ER_TFM_DATA" in gcc linker scripts
to align with armclang.
Change-Id: Ic6071204f8b260f75652353cb49b57602a0dcdd9
Signed-off-by: Edison Ai <edison.ai@arm.com>
6 files changed, 24 insertions, 24 deletions
diff --git a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld index 67da77c48..13478b080 100644 --- a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld +++ b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld @@ -874,8 +874,8 @@ SECTIONS . = ALIGN(4); } > RAM AT> FLASH - Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); - Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); .TFM_BSS : ALIGN(4) { @@ -885,8 +885,8 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM AT> FLASH - Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); - Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA); Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS); diff --git a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template index 048081015..15e09e066 100644 --- a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template +++ b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template @@ -410,8 +410,8 @@ SECTIONS . = ALIGN(4); } > RAM AT> FLASH - Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); - Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); .TFM_BSS : ALIGN(4) { @@ -421,8 +421,8 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM AT> FLASH - Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); - Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA); Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS); diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld index f0066d9ca..5ae4939eb 100644 --- a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld +++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld @@ -874,8 +874,8 @@ SECTIONS . = ALIGN(4); } > RAM AT> FLASH - Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); - Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); .TFM_BSS : ALIGN(4) { @@ -885,8 +885,8 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM AT> FLASH - Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); - Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA); Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS); diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template index e1f12bbe3..bb8ba9987 100644 --- a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template +++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template @@ -410,8 +410,8 @@ SECTIONS . = ALIGN(4); } > RAM AT> FLASH - Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); - Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); .TFM_BSS : ALIGN(4) { @@ -421,8 +421,8 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM AT> FLASH - Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); - Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA); Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS); diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld index 67da77c48..13478b080 100644 --- a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld +++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld @@ -874,8 +874,8 @@ SECTIONS . = ALIGN(4); } > RAM AT> FLASH - Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); - Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); .TFM_BSS : ALIGN(4) { @@ -885,8 +885,8 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM AT> FLASH - Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); - Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA); Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS); diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template index 048081015..15e09e066 100644 --- a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template +++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template @@ -410,8 +410,8 @@ SECTIONS . = ALIGN(4); } > RAM AT> FLASH - Image$$TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); - Image$$TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); .TFM_BSS : ALIGN(4) { @@ -421,8 +421,8 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM AT> FLASH - Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); - Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA); Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS); 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