aboutsummaryrefslogtreecommitdiff
path: root/platform/ext/target/sse_200_mps2/sse_200/armclang/sse_200_s.sct
blob: 46c7ee8362124073e430f3d1ef56f451b13a2d45 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc

/*
 * Copyright (c) 2017 ARM Limited
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include "../partition/region_defs.h"

LR_CODE S_CODE_START {

    /****  This initial section contains common code for TEE */
    ER_TFM_CODE S_CODE_START S_CODE_SIZE {
        *.o (RESET +First)
        .ANY (+RO)
    }

#if TFM_LVL == 1

    ER_TFM_DATA S_DATA_START S_DATA_SIZE {
        .ANY (+RW +ZI)
    }

    TFM_SECURE_STACK +0 ALIGN 128 EMPTY 0x4000 {
    }

    TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
    }

#else /* TFM_LVL == 1 */

    /**** Unprivileged Secure code start here */
    TFM_UNPRIV_CODE +0 ALIGN 32 {
        tfm_unpriv_api.o (+RO)
        platform_retarget_dev.o (+RO)
        *(SFN)
    }

    TFM_SEC_FUNC_STORAGE +0 ALIGN 32 {
        *tfm_storage* (+RO)
    }

#ifdef CORE_TEST_SERVICES
    TFM_SEC_FUNC_CORE_TEST +0 ALIGN 32 {
        *tfm_ss_core_test.* (+RO)
    }

    TFM_SEC_FUNC_CORE_TEST_2 +0 ALIGN 32 {
        *tfm_ss_core_test_2.* (+RO)
    }
#endif /* CORE_TEST_SERVICES */

    ER_TFM_DATA S_DATA_START S_DATA_SIZE {
        .ANY (+RW +ZI)
    }

    TFM_UNPRIV_RO_DATA +0 ALIGN 32 {
        tfm_unpriv_api.o (+RW +ZI)
        platform_retarget_dev.o (+RW +ZI)
    }

    TFM_UNPRIV_SCRATCH +0 ALIGN 32 EMPTY 0x400 {
    }

    TFM_SEC_FUNC_STORAGE_DATA +0 ALIGN 32 {
        *tfm_storage* (+RW +ZI)
    }

    TFM_SEC_FUNC_STORAGE_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }

#ifdef CORE_TEST_SERVICES
    TFM_SEC_FUNC_CORE_TEST_DATA +0 ALIGN 32 {
        tfm_ss_core_test.o (+RW +ZI)
    }

    TFM_SEC_FUNC_CORE_TEST_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }

    TFM_SEC_FUNC_CORE_TEST_2_DATA +0 ALIGN 32 {
        tfm_ss_core_test_2.o (+RW +ZI)
    }

    TFM_SEC_FUNC_CORE_TEST_2_STACK +0 ALIGN 128 EMPTY 0x2000 {
    }
#endif /* CORE_TEST_SERVICES */

#endif /* TFM_LVL == 1 */

}

LR_VENEER CMSE_VENEER_REGION_START {
    /*
     * Place the CMSE Veneers (containing the SG instruction) in a separate
     * 32 bytes aligned region so that the SAU can be programmed to
     * just set this region as Non-Secure Callable.
     */
    ER_CODE_CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
        *(Veneer$$CMSE)
    }
}