From 56ef30234e922539a8916ccc27f219dd10e00706 Mon Sep 17 00:00:00 2001 From: Tamas Ban Date: Thu, 13 Sep 2018 23:49:16 +0100 Subject: Platform: Clean-up stack and heap allocation Details: - ARMCLANG: relocate heap and stack allocation to scatter file from start-up assembly, to be aligned with GNUARM - Explicitly distinguish main and process stack - Reorder the allocation of heap and stack area in RAM: main stack, process stack, heap - Introduce shared data area b/w bootloader and runtime to exchange data - Main stack and shared area are overlapping sections in memory, to prepare the recycling the shared area as stack - Increase bootloader stack size to avoid overflow - Remove unnecessary .heap(COPY) section from GCC linker script Change-Id: Id8702fd9262764814250356868fb8de630b4a1af Signed-off-by: Tamas Ban --- .../target/mps2/an519/armclang/mps2_an519_bl2.sct | 12 ++++- .../target/mps2/an519/armclang/mps2_an519_ns.sct | 11 +++++ .../target/mps2/an519/armclang/mps2_an519_s.sct | 34 ++++++++++++- .../an519/armclang/startup_cmsdk_mps2_an519_bl2.s | 50 +------------------- .../an519/armclang/startup_cmsdk_mps2_an519_ns.s | 53 ++------------------- .../an519/armclang/startup_cmsdk_mps2_an519_s.s | 55 ++-------------------- .../ext/target/mps2/an519/gcc/mps2_an519_bl2.ld | 41 +++++----------- .../ext/target/mps2/an519/gcc/mps2_an519_ns.ld | 36 +++++--------- platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld | 44 ++++++++++------- .../target/mps2/an519/gcc/mps2_an519_s.ld.template | 44 ++++++++++------- .../mps2/an519/gcc/startup_cmsdk_mps2_an519_bl2.S | 5 +- .../mps2/an519/gcc/startup_cmsdk_mps2_an519_ns.S | 4 +- .../mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S | 4 +- .../ext/target/mps2/an519/partition/flash_layout.h | 11 +++++ .../ext/target/mps2/an519/partition/region_defs.h | 18 +++++-- .../target/mps2/an521/armclang/mps2_an521_bl2.sct | 12 ++++- .../target/mps2/an521/armclang/mps2_an521_ns.sct | 11 +++++ .../target/mps2/an521/armclang/mps2_an521_s.sct | 34 ++++++++++++- .../an521/armclang/startup_cmsdk_mps2_an521_bl2.s | 48 ++----------------- .../an521/armclang/startup_cmsdk_mps2_an521_ns.s | 51 ++------------------ .../an521/armclang/startup_cmsdk_mps2_an521_s.s | 50 ++------------------ .../ext/target/mps2/an521/gcc/mps2_an521_bl2.ld | 45 ++++++------------ .../ext/target/mps2/an521/gcc/mps2_an521_ns.ld | 40 +++++----------- platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld | 44 ++++++++++------- .../target/mps2/an521/gcc/mps2_an521_s.ld.template | 44 ++++++++++------- .../mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S | 5 +- .../mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S | 4 +- .../mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S | 4 +- .../ext/target/mps2/an521/partition/flash_layout.h | 11 +++++ .../ext/target/mps2/an521/partition/region_defs.h | 16 +++++-- .../musca_a/Device/Source/armclang/musca_bl2.sct | 12 ++++- .../musca_a/Device/Source/armclang/musca_ns.sct | 11 +++++ .../musca_a/Device/Source/armclang/musca_s.sct | 34 ++++++++++++- .../Source/armclang/startup_cmsdk_musca_bl2.s | 46 +----------------- .../Source/armclang/startup_cmsdk_musca_ns.s | 48 ++----------------- .../Device/Source/armclang/startup_cmsdk_musca_s.s | 50 ++------------------ .../target/musca_a/Device/Source/gcc/musca_bl2.ld | 41 +++++----------- .../target/musca_a/Device/Source/gcc/musca_ns.ld | 36 +++++--------- .../target/musca_a/Device/Source/gcc/musca_s.ld | 44 ++++++++++------- .../musca_a/Device/Source/gcc/musca_s.ld.template | 44 ++++++++++------- .../Device/Source/gcc/startup_cmsdk_musca_bl2.S | 5 +- .../Device/Source/gcc/startup_cmsdk_musca_ns.S | 4 +- .../Device/Source/gcc/startup_cmsdk_musca_s.S | 4 +- .../ext/target/musca_a/partition/flash_layout.h | 11 +++++ .../ext/target/musca_a/partition/region_defs.h | 12 +++++ .../musca_b1/Device/Source/armclang/musca_bl2.sct | 12 ++++- .../musca_b1/Device/Source/armclang/musca_ns.sct | 11 +++++ .../musca_b1/Device/Source/armclang/musca_s.sct | 34 ++++++++++++- .../Source/armclang/startup_cmsdk_musca_bl2.s | 46 +----------------- .../Source/armclang/startup_cmsdk_musca_ns.s | 48 ++----------------- .../Device/Source/armclang/startup_cmsdk_musca_s.s | 50 ++------------------ .../target/musca_b1/Device/Source/gcc/musca_bl2.ld | 40 +++++----------- .../target/musca_b1/Device/Source/gcc/musca_ns.ld | 35 +++++--------- .../target/musca_b1/Device/Source/gcc/musca_s.ld | 44 ++++++++++------- .../musca_b1/Device/Source/gcc/musca_s.ld.template | 44 ++++++++++------- .../Device/Source/gcc/startup_cmsdk_musca_bl2.S | 5 +- .../Device/Source/gcc/startup_cmsdk_musca_ns.S | 4 +- .../Device/Source/gcc/startup_cmsdk_musca_s.S | 4 +- .../ext/target/musca_b1/partition/flash_layout.h | 11 +++++ .../ext/target/musca_b1/partition/region_defs.h | 17 ++++++- secure_fw/core/tfm_core.c | 5 +- secure_fw/core/tfm_secure_api.c | 6 ++- secure_fw/spm/spm_api.c | 14 +++--- 63 files changed, 691 insertions(+), 982 deletions(-) diff --git a/platform/ext/target/mps2/an519/armclang/mps2_an519_bl2.sct b/platform/ext/target/mps2/an519/armclang/mps2_an519_bl2.sct index 85c6569fd4..f798c8ce44 100644 --- a/platform/ext/target/mps2/an519/armclang/mps2_an519_bl2.sct +++ b/platform/ext/target/mps2/an519/armclang/mps2_an519_bl2.sct @@ -24,7 +24,17 @@ LR_CODE BL2_CODE_START { .ANY (+RO) } - ER_DATA BL2_DATA_START BL2_DATA_SIZE { + TFM_SHARED_DATA BL2_DATA_START ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + ER_DATA +0 BL2_DATA_SIZE { .ANY (+ZI +RW) } + + /* MSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL2_HEAP_SIZE { + } } diff --git a/platform/ext/target/mps2/an519/armclang/mps2_an519_ns.sct b/platform/ext/target/mps2/an519/armclang/mps2_an519_ns.sct index e1049f6987..ee68147b77 100644 --- a/platform/ext/target/mps2/an519/armclang/mps2_an519_ns.sct +++ b/platform/ext/target/mps2/an519/armclang/mps2_an519_ns.sct @@ -27,5 +27,16 @@ LR_CODE NS_CODE_START { ER_DATA NS_DATA_START NS_DATA_SIZE { .ANY (+ZI +RW) } + + /* MSP */ + ARM_LIB_STACK_MSP +0 ALIGN 32 EMPTY NS_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY NS_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY NS_HEAP_SIZE { + } } diff --git a/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct b/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct index a399414e88..496850129a 100644 --- a/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct +++ b/platform/ext/target/mps2/an519/armclang/mps2_an519_s.sct @@ -28,7 +28,22 @@ LR_CODE S_CODE_START { #if TFM_LVL == 1 - ER_TFM_DATA S_DATA_START S_DATA_SIZE { + /* Shared area between BL2 and runtime to exchange data */ + TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + /* MSP */ + ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { + } + + ER_TFM_DATA +0 S_DATA_SIZE { .ANY (+RW +ZI) } @@ -101,7 +116,22 @@ LR_CODE S_CODE_START { } #endif /* TFM_PARTITION_TEST_SECURE_SERVICES */ - ER_TFM_DATA S_DATA_START S_DATA_SIZE { + /* Shared area between BL2 and runtime to exchange data */ + TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + /* MSP */ + ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { + } + + ER_TFM_DATA +0 S_DATA_SIZE { .ANY (+RW +ZI) } diff --git a/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_bl2.s b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_bl2.s index 9948f336e4..658b9285cc 100644 --- a/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_bl2.s +++ b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_bl2.s @@ -25,25 +25,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000800 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT Stack_Mem -Stack_Mem SPACE Stack_Size -__initial_msp -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -52,7 +34,7 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_msp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -313,34 +295,6 @@ GPIO1_7_Handler ; 95 ENDP - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - ALIGN - ENDIF - - END diff --git a/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_ns.s b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_ns.s index cd25673611..01d359c1b2 100644 --- a/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_ns.s +++ b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_ns.s @@ -25,25 +25,8 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_msp - -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -52,7 +35,7 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_msp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -185,7 +168,7 @@ Reset_Handler PROC MOVS R1, #2 ORRS R0, R0, R1 ; Select switch to PSP MSR control, R0 - LDR R0, =__initial_sp + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| MOV SP, R0 ; Initialise PSP LDR R0, =__main BX R0 @@ -367,34 +350,6 @@ GPIO1_7_Handler ; 95 ENDP - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s index 9c795d8287..363d83e95f 100644 --- a/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s +++ b/platform/ext/target/mps2/an519/armclang/startup_cmsdk_mps2_an519_s.s @@ -25,27 +25,8 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000800 - - AREA STACK, NOINIT, READWRITE, ALIGN=7 - EXPORT Stack_Mem -Stack_Mem SPACE Stack_Size -__initial_msp -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - EXPORT Stack_top -Stack_top EQU __initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -56,7 +37,7 @@ __heap_limit PRESERVE8 -__Vectors DCD __initial_msp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -191,7 +172,7 @@ Reset_Handler PROC MOVS R1, #2 ORRS R0, R0, R1 ; Select switch to PSP MSR control, R0 - LDR R0, =__initial_sp + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| MOVS R1, #7 BICS R0, R1 ; Make sure that the SP address is aligned to 8 MOV SP, R0 ; Initialise PSP @@ -383,34 +364,6 @@ GPIO1_7_Handler ; 95 ENDP - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - ALIGN - ENDIF - - END diff --git a/platform/ext/target/mps2/an519/gcc/mps2_an519_bl2.ld b/platform/ext/target/mps2/an519/gcc/mps2_an519_bl2.ld index b6b8d62378..bf066f629f 100644 --- a/platform/ext/target/mps2/an519/gcc/mps2_an519_bl2.ld +++ b/platform/ext/target/mps2/an519/gcc/mps2_an519_bl2.ld @@ -28,9 +28,8 @@ MEMORY RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE } -__heap_size__ = 0x00010000; -__psp_stack_size__ = 0x00000800; -__msp_stack_size__ = 0x00000800; +__heap_size__ = BL2_HEAP_SIZE; +__msp_stack_size__ = BL2_MSP_STACK_SIZE; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a) @@ -115,6 +114,13 @@ SECTIONS __etext = .; + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM + Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data); + Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data); + .data : AT (__etext) { __data_start__ = .; @@ -161,35 +167,14 @@ SECTIONS bss_size = __bss_end__ - __bss_start__; - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - .psp_stack : - { - . = ALIGN(8); - KEEP(*(.psp_stack*)) - . += __psp_stack_size__; - } > RAM - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : + .msp_stack : ALIGN(32) { - . = ALIGN(8); - KEEP(*(.psp_stack*)) . += __msp_stack_size__; } > RAM - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); - .heap : + .heap : ALIGN(8) { - . = ALIGN(8); __end__ = .; PROVIDE(end = .); __HeapBase = .; @@ -198,5 +183,5 @@ SECTIONS __heap_limit = .; /* Add for _sbrk */ } > RAM - PROVIDE( __stack = __initial_msp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/mps2/an519/gcc/mps2_an519_ns.ld b/platform/ext/target/mps2/an519/gcc/mps2_an519_ns.ld index f5167ab4b0..1bdcbfb1fa 100644 --- a/platform/ext/target/mps2/an519/gcc/mps2_an519_ns.ld +++ b/platform/ext/target/mps2/an519/gcc/mps2_an519_ns.ld @@ -28,9 +28,9 @@ MEMORY RAM (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00000C00; -__msp_stack_size__ = 0x00000400; +__heap_size__ = NS_HEAP_SIZE; +__psp_stack_size__ = NS_PSP_STACK_SIZE; +__msp_stack_size__ = NS_MSP_STACK_SIZE; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a) @@ -161,35 +161,21 @@ SECTIONS bss_size = __bss_end__ - __bss_start__; - .heap (COPY): + .msp_stack : ALIGN(32) { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; + . += __msp_stack_size__; } > RAM + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); - .psp_stack : + .psp_stack : ALIGN(32) { - . = ALIGN(8); - KEEP(*(.psp_stack*)) . += __psp_stack_size__; } > RAM - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : - { - . = ALIGN(8); - KEEP(*(.psp_stack*)) - . += __msp_stack_size__; - } > RAM - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); - .heap : + .heap : ALIGN(8) { - . = ALIGN(8); __end__ = .; PROVIDE(end = .); __HeapBase = .; @@ -198,5 +184,5 @@ SECTIONS __heap_limit = .; /* Add for _sbrk */ } > RAM - PROVIDE(__stack = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld index 649fc8ceae..53a73371a1 100644 --- a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld +++ b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld @@ -31,9 +31,9 @@ MEMORY VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00001000; -__msp_stack_size__ = 0x00000800; +__heap_size__ = S_HEAP_SIZE; +__psp_stack_size__ = S_PSP_STACK_SIZE; +__msp_init_stack_size__ = S_MSP_STACK_SIZE_INIT; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a) @@ -356,6 +356,28 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH + /* shared_data and msp_stack are overlapping on purpose when + * msp_stack is extended until the beginning of RAM, when shared_date + * was read out by partitions + */ + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM AT> FLASH + + .msp_stack : ALIGN(32) + { + . += __msp_init_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .psp_stack : ALIGN(32) + { + . += __psp_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + #if TFM_LVL == 1 .TFM_SECURE_STACK : ALIGN(128) @@ -683,19 +705,6 @@ SECTIONS Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); - .psp_stack : ALIGN(128) - { - . += __psp_stack_size__; - } > RAM AT> FLASH - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : ALIGN(128) - { - . += __msp_stack_size__; - } > RAM AT> FLASH - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); - /* * Place the CMSE Veneers (containing the SG instruction) after the code, in a * separate 32 bytes aligned region so that the SAU can programmed to just set @@ -714,6 +723,5 @@ SECTIONS Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = __initial_sp); - PROVIDE(Stack_top = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template index d257d4dc77..738344d8dc 100644 --- a/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template +++ b/platform/ext/target/mps2/an519/gcc/mps2_an519_s.ld.template @@ -31,9 +31,9 @@ MEMORY VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00001000; -__msp_stack_size__ = 0x00000800; +__heap_size__ = S_HEAP_SIZE; +__psp_stack_size__ = S_PSP_STACK_SIZE; +__msp_init_stack_size__ = S_MSP_STACK_SIZE_INIT; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a) @@ -215,6 +215,28 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH + /* shared_data and msp_stack are overlapping on purpose when + * msp_stack is extended until the beginning of RAM, when shared_date + * was read out by partitions + */ + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM AT> FLASH + + .msp_stack : ALIGN(32) + { + . += __msp_init_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .psp_stack : ALIGN(32) + { + . += __psp_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + #if TFM_LVL == 1 .TFM_SECURE_STACK : ALIGN(128) @@ -364,19 +386,6 @@ SECTIONS Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); - .psp_stack : ALIGN(128) - { - . += __psp_stack_size__; - } > RAM AT> FLASH - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : ALIGN(128) - { - . += __msp_stack_size__; - } > RAM AT> FLASH - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); - /* * Place the CMSE Veneers (containing the SG instruction) after the code, in a * separate 32 bytes aligned region so that the SAU can programmed to just set @@ -395,6 +404,5 @@ SECTIONS Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = __initial_sp); - PROVIDE(Stack_top = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_bl2.S b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_bl2.S index 6328ce1703..d5ad2abe04 100644 --- a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_bl2.S +++ b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_bl2.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -307,9 +307,6 @@ Reset_Handler: bl SystemInit - ldr r0, =__initial_sp - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_ns.S b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_ns.S index 009756bd4f..3b10898875 100644 --- a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_ns.S +++ b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_ns.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -311,7 +311,7 @@ Reset_Handler: movs r1, #2 orrs r0, r0, r1 /* Select switch to PSP */ msr control, r0 - ldr r0, =__initial_sp + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit msr psp, r0 #ifndef __START diff --git a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S index c69141754f..df87164bfc 100644 --- a/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S +++ b/platform/ext/target/mps2/an519/gcc/startup_cmsdk_mps2_an519_s.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -312,7 +312,7 @@ Reset_Handler: movs r1, #2 orrs r0, r0, r1 /* Select switch to PSP */ msr control, r0 - ldr r0, =__initial_sp + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit msr psp, r0 #ifndef __START diff --git a/platform/ext/target/mps2/an519/partition/flash_layout.h b/platform/ext/target/mps2/an519/partition/flash_layout.h index e953227eb7..1dc4306caf 100644 --- a/platform/ext/target/mps2/an519/partition/flash_layout.h +++ b/platform/ext/target/mps2/an519/partition/flash_layout.h @@ -116,4 +116,15 @@ #define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET #define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE +/* FIXME: Use SRAM2 memory to store RW data */ +#define S_RAM_ALIAS_BASE (0x38000000) +#define NS_RAM_ALIAS_BASE (0x28000000) + +/* Shared data area between bootloader and runtime firmware. + * Shared data area is allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE +#define BOOT_TFM_SHARED_DATA_SIZE 0x400 + #endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/mps2/an519/partition/region_defs.h b/platform/ext/target/mps2/an519/partition/region_defs.h index c0ccd9bdcf..081b848a6d 100644 --- a/platform/ext/target/mps2/an519/partition/region_defs.h +++ b/platform/ext/target/mps2/an519/partition/region_defs.h @@ -22,6 +22,18 @@ #define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE #define TOTAL_RAM_SIZE (0x00200000) /* 2 MB */ +#define BL2_HEAP_SIZE 0x0001000 +#define BL2_MSP_STACK_SIZE 0x0001000 + +#define S_HEAP_SIZE 0x0001000 +#define S_MSP_STACK_SIZE_INIT 0x0000400 +#define S_MSP_STACK_SIZE 0x0000800 +#define S_PSP_STACK_SIZE 0x0000800 + +#define NS_HEAP_SIZE 0x0001000 +#define NS_MSP_STACK_SIZE 0x0000400 +#define NS_PSP_STACK_SIZE 0x0000C00 + /* * MPC granularity is 128 KB on AN519 MPS2 FPGA image. Alignment * of partitions is defined in accordance with this constraint. @@ -73,10 +85,6 @@ #define S_ROM_ALIAS_BASE (0x10000000) #define NS_ROM_ALIAS_BASE (0x00000000) -/* FIXME: Use SRAM2 memory to store RW data */ -#define S_RAM_ALIAS_BASE (0x38000000) -#define NS_RAM_ALIAS_BASE (0x28000000) - /* Alias definitions for secure and non-secure areas*/ #define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + x) #define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + x) @@ -100,7 +108,7 @@ /* Non-secure regions */ #define NS_IMAGE_PRIMARY_AREA_OFFSET \ - (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) + (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) #define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) #define NS_CODE_SIZE (IMAGE_CODE_SIZE) #define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) diff --git a/platform/ext/target/mps2/an521/armclang/mps2_an521_bl2.sct b/platform/ext/target/mps2/an521/armclang/mps2_an521_bl2.sct index 2253ddf472..ad02012e63 100644 --- a/platform/ext/target/mps2/an521/armclang/mps2_an521_bl2.sct +++ b/platform/ext/target/mps2/an521/armclang/mps2_an521_bl2.sct @@ -24,7 +24,17 @@ LR_CODE BL2_CODE_START { .ANY (+RO) } - ER_DATA BL2_DATA_START BL2_DATA_SIZE { + TFM_SHARED_DATA BL2_DATA_START ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + ER_DATA +0 BL2_DATA_SIZE { .ANY (+ZI +RW) } + + /* MSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL2_HEAP_SIZE { + } } diff --git a/platform/ext/target/mps2/an521/armclang/mps2_an521_ns.sct b/platform/ext/target/mps2/an521/armclang/mps2_an521_ns.sct index e1049f6987..ee68147b77 100644 --- a/platform/ext/target/mps2/an521/armclang/mps2_an521_ns.sct +++ b/platform/ext/target/mps2/an521/armclang/mps2_an521_ns.sct @@ -27,5 +27,16 @@ LR_CODE NS_CODE_START { ER_DATA NS_DATA_START NS_DATA_SIZE { .ANY (+ZI +RW) } + + /* MSP */ + ARM_LIB_STACK_MSP +0 ALIGN 32 EMPTY NS_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY NS_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY NS_HEAP_SIZE { + } } diff --git a/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct b/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct index a399414e88..496850129a 100644 --- a/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct +++ b/platform/ext/target/mps2/an521/armclang/mps2_an521_s.sct @@ -28,7 +28,22 @@ LR_CODE S_CODE_START { #if TFM_LVL == 1 - ER_TFM_DATA S_DATA_START S_DATA_SIZE { + /* Shared area between BL2 and runtime to exchange data */ + TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + /* MSP */ + ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { + } + + ER_TFM_DATA +0 S_DATA_SIZE { .ANY (+RW +ZI) } @@ -101,7 +116,22 @@ LR_CODE S_CODE_START { } #endif /* TFM_PARTITION_TEST_SECURE_SERVICES */ - ER_TFM_DATA S_DATA_START S_DATA_SIZE { + /* Shared area between BL2 and runtime to exchange data */ + TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + /* MSP */ + ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { + } + + ER_TFM_DATA +0 S_DATA_SIZE { .ANY (+RW +ZI) } diff --git a/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_bl2.s b/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_bl2.s index bedeec0079..404f2a5d67 100644 --- a/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_bl2.s +++ b/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_bl2.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016 ARM Limited +; * Copyright (c) 2016-2018 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -25,21 +25,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000800 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT Stack_Mem -Stack_Mem SPACE Stack_Size -__initial_msp -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -48,7 +34,7 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_msp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -330,34 +316,6 @@ GPIO1_7_Handler ; 95 ENDP - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - ALIGN - ENDIF - - END diff --git a/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_ns.s b/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_ns.s index 188188dddc..a5067545bf 100644 --- a/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_ns.s +++ b/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_ns.s @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016 ARM Limited +; * Copyright (c) 2016-2018 ARM Limited ; * ; * Licensed under the Apache License, Version 2.0 (the "License"); ; * you may not use this file except in compliance with the License. @@ -25,22 +25,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_msp - -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -49,7 +34,7 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_msp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -178,7 +163,7 @@ Reset_Handler PROC IMPORT __main MRS R0, control ; Get control value ORR R0, R0, #1 ; Select switch to unprivilage mode - ORR R0, R0, #2 ; Select switch to PSP, which will be set by __user_initial_stackheap + ORR R0, R0, #2 ; Select switch to PSP MSR control, R0 LDR R0, =__main BX R0 @@ -380,34 +365,6 @@ GPIO1_7_Handler ; 95 ENDP - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - ALIGN - ENDIF - - END diff --git a/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s b/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s index 14ffbcbd42..1d7ede5c53 100644 --- a/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s +++ b/platform/ext/target/mps2/an521/armclang/startup_cmsdk_mps2_an521_s.s @@ -25,23 +25,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000800 - - AREA STACK, NOINIT, READWRITE, ALIGN=7 - EXPORT Stack_Mem -Stack_Mem SPACE Stack_Size -__initial_msp -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - EXPORT Stack_top -Stack_top EQU __initial_sp - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -50,7 +34,7 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_msp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -182,7 +166,7 @@ Reset_Handler PROC LDR R0, =SystemInit BLX R0 MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP, which will be set by __user_initial_stackheap + ORR R0, R0, #2 ; Select switch to PSP MSR control, R0 LDR R0, =__main BX R0 @@ -399,34 +383,6 @@ GPIO1_7_Handler ; 95 ENDP - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - ALIGN - ENDIF - - END diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_bl2.ld b/platform/ext/target/mps2/an521/gcc/mps2_an521_bl2.ld index 23136a89cf..16f0d8ce7c 100644 --- a/platform/ext/target/mps2/an521/gcc/mps2_an521_bl2.ld +++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_bl2.ld @@ -28,9 +28,8 @@ MEMORY RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE } -__heap_size__ = 0x00010000; -__psp_stack_size__ = 0x00000800; -__msp_stack_size__ = 0x00000800; +__heap_size__ = BL2_HEAP_SIZE; +__msp_stack_size__ = BL2_MSP_STACK_SIZE; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a) @@ -85,7 +84,7 @@ SECTIONS /* To copy multiple ROM to RAM sections, * define etext2/data2_start/data2_end and - * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps2_sse_200.S */ + * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps2_an521_bl2.S */ .copy.table : { . = ALIGN(4); @@ -101,7 +100,7 @@ SECTIONS /* To clear multiple BSS sections, * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_mps2_an521_bl2.S */ .zero.table : { . = ALIGN(4); @@ -115,6 +114,13 @@ SECTIONS __etext = .; + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM + Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data); + Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data); + .data : AT (__etext) { __data_start__ = .; @@ -161,35 +167,14 @@ SECTIONS bss_size = __bss_end__ - __bss_start__; - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - .psp_stack : - { - . = ALIGN(8); - KEEP(*(.psp_stack*)) - . += __psp_stack_size__; - } > RAM - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : + .msp_stack : ALIGN(32) { - . = ALIGN(8); - KEEP(*(.psp_stack*)) . += __msp_stack_size__; } > RAM - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); - .heap : + .heap : ALIGN(8) { - . = ALIGN(8); __end__ = .; PROVIDE(end = .); __HeapBase = .; @@ -198,5 +183,5 @@ SECTIONS __heap_limit = .; /* Add for _sbrk */ } > RAM - PROVIDE( __stack = __initial_msp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_ns.ld b/platform/ext/target/mps2/an521/gcc/mps2_an521_ns.ld index 130c41a03a..8453b78d56 100644 --- a/platform/ext/target/mps2/an521/gcc/mps2_an521_ns.ld +++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_ns.ld @@ -28,9 +28,9 @@ MEMORY RAM (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00000C00; -__msp_stack_size__ = 0x00000400; +__heap_size__ = NS_HEAP_SIZE; +__psp_stack_size__ = NS_PSP_STACK_SIZE; +__msp_stack_size__ = NS_MSP_STACK_SIZE; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a) @@ -85,7 +85,7 @@ SECTIONS /* To copy multiple ROM to RAM sections, * define etext2/data2_start/data2_end and - * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps2_sse_200.S */ + * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps2_an521_ns.S */ .copy.table : { . = ALIGN(4); @@ -101,7 +101,7 @@ SECTIONS /* To clear multiple BSS sections, * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_mps2_an521_ns.S */ .zero.table : { . = ALIGN(4); @@ -161,35 +161,21 @@ SECTIONS bss_size = __bss_end__ - __bss_start__; - .heap (COPY): + .msp_stack : ALIGN(32) { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; + . += __msp_stack_size__; } > RAM + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); - .psp_stack : + .psp_stack : ALIGN(32) { - . = ALIGN(8); - KEEP(*(.psp_stack*)) . += __psp_stack_size__; } > RAM - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : - { - . = ALIGN(8); - KEEP(*(.psp_stack*)) - . += __msp_stack_size__; - } > RAM - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); - .heap : + .heap : ALIGN(8) { - . = ALIGN(8); __end__ = .; PROVIDE(end = .); __HeapBase = .; @@ -198,5 +184,5 @@ SECTIONS __heap_limit = .; /* Add for _sbrk */ } > RAM - PROVIDE(__stack = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld index 05fbee33da..4334f92a60 100644 --- a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld +++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld @@ -31,9 +31,9 @@ MEMORY VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00001000; -__msp_stack_size__ = 0x00000800; +__heap_size__ = S_HEAP_SIZE; +__psp_stack_size__ = S_PSP_STACK_SIZE; +__msp_init_stack_size__ = S_MSP_STACK_SIZE_INIT; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a) @@ -356,6 +356,28 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH + /* shared_data and msp_stack are overlapping on purpose when + * msp_stack is extended until the beginning of RAM, when shared_date + * was read out by partitions + */ + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM AT> FLASH + + .msp_stack : ALIGN(32) + { + . += __msp_init_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .psp_stack : ALIGN(32) + { + . += __psp_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + #if TFM_LVL == 1 .TFM_SECURE_STACK : ALIGN(128) @@ -683,19 +705,6 @@ SECTIONS Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); - .psp_stack : ALIGN(128) - { - . += __psp_stack_size__; - } > RAM AT> FLASH - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : ALIGN(128) - { - . += __msp_stack_size__; - } > RAM AT> FLASH - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); - /* * Place the CMSE Veneers (containing the SG instruction) after the code, in a * separate 32 bytes aligned region so that the SAU can programmed to just set @@ -714,6 +723,5 @@ SECTIONS Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = __initial_sp); - PROVIDE(Stack_top = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template index 982481f315..029a428f1f 100644 --- a/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template +++ b/platform/ext/target/mps2/an521/gcc/mps2_an521_s.ld.template @@ -31,9 +31,9 @@ MEMORY VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00001000; -__msp_stack_size__ = 0x00000800; +__heap_size__ = S_HEAP_SIZE; +__psp_stack_size__ = S_PSP_STACK_SIZE; +__msp_init_stack_size__ = S_MSP_STACK_SIZE_INIT; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a) @@ -215,6 +215,28 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH + /* shared_data and msp_stack are overlapping on purpose when + * msp_stack is extended until the beginning of RAM, when shared_date + * was read out by partitions + */ + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM AT> FLASH + + .msp_stack : ALIGN(32) + { + . += __msp_init_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .psp_stack : ALIGN(32) + { + . += __psp_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + #if TFM_LVL == 1 .TFM_SECURE_STACK : ALIGN(128) @@ -364,19 +386,6 @@ SECTIONS Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); - .psp_stack : ALIGN(128) - { - . += __psp_stack_size__; - } > RAM AT> FLASH - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : ALIGN(128) - { - . += __msp_stack_size__; - } > RAM AT> FLASH - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); - /* * Place the CMSE Veneers (containing the SG instruction) after the code, in a * separate 32 bytes aligned region so that the SAU can programmed to just set @@ -395,6 +404,5 @@ SECTIONS Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = __initial_sp); - PROVIDE(Stack_top = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S index a40203e9d4..0374bee5bd 100644 --- a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S +++ b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_bl2.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -277,9 +277,6 @@ not_the_core_to_run_on: bl SystemInit - ldr r0, =__initial_sp - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S index 0fdc7bb401..aa13bc187f 100644 --- a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S +++ b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_ns.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -271,7 +271,7 @@ Reset_Handler: orr r0, r0, #1 /* Select switch to unprivilage mode */ orr r0, r0, #2 /* Select switch to PSP */ msr control, r0 - ldr r0, =__initial_sp + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit msr psp, r0 #ifndef __START diff --git a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S index 2c92cd6810..99d42a6523 100644 --- a/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S +++ b/platform/ext/target/mps2/an521/gcc/startup_cmsdk_mps2_an521_s.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ /* Core interrupts */ .long Reset_Handler /* Reset Handler */ @@ -273,7 +273,7 @@ Reset_Handler: mrs r0, control /* Get control value */ orr r0, r0, #2 /* Select switch to PSP */ msr control, r0 - ldr r0, =__initial_sp + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit msr psp, r0 #ifndef __START diff --git a/platform/ext/target/mps2/an521/partition/flash_layout.h b/platform/ext/target/mps2/an521/partition/flash_layout.h index c77f012aba..4f30ad5645 100644 --- a/platform/ext/target/mps2/an521/partition/flash_layout.h +++ b/platform/ext/target/mps2/an521/partition/flash_layout.h @@ -116,4 +116,15 @@ #define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET #define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE +/* FIXME: Use SRAM2 memory to store RW data */ +#define S_RAM_ALIAS_BASE (0x38000000) +#define NS_RAM_ALIAS_BASE (0x28000000) + +/* Shared data area between bootloader and runtime firmware. + * Shared data area is allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE +#define BOOT_TFM_SHARED_DATA_SIZE 0x400 + #endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/mps2/an521/partition/region_defs.h b/platform/ext/target/mps2/an521/partition/region_defs.h index 22b7b0d864..4de8db12f8 100644 --- a/platform/ext/target/mps2/an521/partition/region_defs.h +++ b/platform/ext/target/mps2/an521/partition/region_defs.h @@ -22,6 +22,18 @@ #define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE #define TOTAL_RAM_SIZE (0x00200000) /* 2 MB */ +#define BL2_HEAP_SIZE 0x0001000 +#define BL2_MSP_STACK_SIZE 0x0001000 + +#define S_HEAP_SIZE 0x0001000 +#define S_MSP_STACK_SIZE_INIT 0x0000400 +#define S_MSP_STACK_SIZE 0x0000800 +#define S_PSP_STACK_SIZE 0x0000800 + +#define NS_HEAP_SIZE 0x0001000 +#define NS_MSP_STACK_SIZE 0x0000400 +#define NS_PSP_STACK_SIZE 0x0000C00 + /* * MPC granularity is 128 KB on AN521 Castor MPS2 FPGA image. Alignment * of partitions is defined in accordance with this constraint. @@ -73,10 +85,6 @@ #define S_ROM_ALIAS_BASE (0x10000000) #define NS_ROM_ALIAS_BASE (0x00000000) -/* FIXME: Use SRAM2 memory to store RW data */ -#define S_RAM_ALIAS_BASE (0x38000000) -#define NS_RAM_ALIAS_BASE (0x28000000) - /* Alias definitions for secure and non-secure areas*/ #define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + x) #define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + x) diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct b/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct index b6c231058b..c954dc28d6 100755 --- a/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct +++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_bl2.sct @@ -30,7 +30,17 @@ LR_CODE BL2_CODE_START { .ANY (+RO) ; app code that gets copied from Flash to SRAM } - ER_DATA BL2_DATA_START BL2_DATA_SIZE { + TFM_SHARED_DATA BL2_DATA_START ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + ER_DATA +0 BL2_DATA_SIZE { .ANY (+ZI +RW) } + + /* MSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL2_HEAP_SIZE { + } } diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_ns.sct b/platform/ext/target/musca_a/Device/Source/armclang/musca_ns.sct index 87ca3e3fa6..b9d15fabae 100644 --- a/platform/ext/target/musca_a/Device/Source/armclang/musca_ns.sct +++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_ns.sct @@ -27,5 +27,16 @@ LR_CODE NS_CODE_START { ER_DATA NS_DATA_START NS_DATA_SIZE { .ANY (+ZI +RW) } + + /* MSP */ + ARM_LIB_STACK_MSP +0 ALIGN 32 EMPTY NS_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY NS_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY NS_HEAP_SIZE { + } } diff --git a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct index 2552c76c85..184383eead 100755 --- a/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct +++ b/platform/ext/target/musca_a/Device/Source/armclang/musca_s.sct @@ -28,7 +28,22 @@ LR_CODE S_CODE_START { #if TFM_LVL == 1 - ER_TFM_DATA S_DATA_START S_DATA_SIZE { + /* Shared area between BL2 and runtime to exchange data */ + TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + /* MSP */ + ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { + } + + ER_TFM_DATA +0 S_DATA_SIZE { .ANY (+RW +ZI) } @@ -101,7 +116,22 @@ LR_CODE S_CODE_START { } #endif /* TFM_PARTITION_TEST_SECURE_SERVICES */ - ER_TFM_DATA S_DATA_START S_DATA_SIZE { + /* Shared area between BL2 and runtime to exchange data */ + TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + /* MSP */ + ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { + } + + ER_TFM_DATA +0 S_DATA_SIZE { .ANY (+RW +ZI) } diff --git a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s index 8b035c68f8..3ed69d626c 100755 --- a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s +++ b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_bl2.s @@ -26,24 +26,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000800 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT Stack_Mem -Stack_Mem SPACE Stack_Size -__initial_msp -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -53,7 +36,7 @@ __heap_limit EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD __initial_msp ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -262,29 +245,4 @@ $handler_name PROC ALIGN -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ENDIF - - ALIGN - END diff --git a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s index 6d1e8f9589..23c5227265 100755 --- a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s +++ b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_ns.s @@ -26,24 +26,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT Stack_Mem -Stack_Mem SPACE Stack_Size -__initial_msp -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -53,7 +36,7 @@ __heap_limit EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD __initial_msp ; Top of Stack + DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -160,7 +143,7 @@ Reset_Handler PROC IMPORT __main MRS R0, control ; Get control value ORR R0, R0, #1 ; Select switch to unprivilage mode - ORR R0, R0, #2 ; Select switch to PSP, which will be set by __user_initial_stackheap + ORR R0, R0, #2 ; Select switch to PSP MSR control, R0 LDR R0, =__main BX R0 @@ -258,29 +241,4 @@ $handler_name PROC ALIGN -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ENDIF - - ALIGN - END diff --git a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s index 7d17298612..bff2a82191 100755 --- a/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s +++ b/platform/ext/target/musca_a/Device/Source/armclang/startup_cmsdk_musca_s.s @@ -26,26 +26,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000800 - - AREA STACK, NOINIT, READWRITE, ALIGN=7 - EXPORT Stack_Mem -Stack_Mem SPACE Stack_Size -__initial_msp -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - EXPORT Stack_top -Stack_top EQU __initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -55,7 +36,7 @@ __heap_limit EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD __initial_msp ; Top of Stack + DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -165,7 +146,7 @@ Reset_Handler PROC LDR R0, =SystemInit BLX R0 MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP, which will be set by __user_initial_stackheap + ORR R0, R0, #2 ; Select switch to PSP MSR control, R0 LDR R0, =__main BX R0 @@ -268,29 +249,4 @@ $handler_name PROC ALIGN -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ENDIF - - ALIGN - END diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_bl2.ld b/platform/ext/target/musca_a/Device/Source/gcc/musca_bl2.ld index 9285e6d082..ec3b908c19 100644 --- a/platform/ext/target/musca_a/Device/Source/gcc/musca_bl2.ld +++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_bl2.ld @@ -29,9 +29,8 @@ MEMORY RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE } -__heap_size__ = 0x00010000; -__psp_stack_size__ = 0x00000800; -__msp_stack_size__ = 0x00000800; +__heap_size__ = BL2_HEAP_SIZE; +__msp_stack_size__ = BL2_MSP_STACK_SIZE; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a) @@ -144,6 +143,13 @@ SECTIONS __etext = .; + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM + Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data); + Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data); + .data : AT (__etext) { __data_start__ = .; @@ -190,35 +196,14 @@ SECTIONS bss_size = __bss_end__ - __bss_start__; - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - .psp_stack : - { - . = ALIGN(8); - KEEP(*(.psp_stack*)) - . += __psp_stack_size__; - } > RAM - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : + .msp_stack : ALIGN(32) { - . = ALIGN(8); - KEEP(*(.psp_stack*)) . += __msp_stack_size__; } > RAM - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); - .heap : + .heap : ALIGN(8) { - . = ALIGN(8); __end__ = .; PROVIDE(end = .); __HeapBase = .; @@ -227,5 +212,5 @@ SECTIONS __heap_limit = .; /* Add for _sbrk */ } > RAM - PROVIDE( __stack = __initial_msp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_ns.ld b/platform/ext/target/musca_a/Device/Source/gcc/musca_ns.ld index 81a92c7087..7ca4cbfc8b 100644 --- a/platform/ext/target/musca_a/Device/Source/gcc/musca_ns.ld +++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_ns.ld @@ -28,9 +28,9 @@ MEMORY RAM (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00000C00; -__msp_stack_size__ = 0x00000400; +__heap_size__ = NS_HEAP_SIZE; +__psp_stack_size__ = NS_PSP_STACK_SIZE; +__msp_stack_size__ = NS_MSP_STACK_SIZE; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a) @@ -161,35 +161,21 @@ SECTIONS bss_size = __bss_end__ - __bss_start__; - .heap (COPY): + .msp_stack : ALIGN(32) { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; + . += __msp_stack_size__; } > RAM + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); - .psp_stack : + .psp_stack : ALIGN(32) { - . = ALIGN(8); - KEEP(*(.psp_stack*)) . += __psp_stack_size__; } > RAM - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : - { - . = ALIGN(8); - KEEP(*(.psp_stack*)) - . += __msp_stack_size__; - } > RAM - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); - .heap : + .heap : ALIGN(8) { - . = ALIGN(8); __end__ = .; PROVIDE(end = .); __HeapBase = .; @@ -198,5 +184,5 @@ SECTIONS __heap_limit = .; /* Add for _sbrk */ } > RAM - PROVIDE(__stack = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld index 156247c836..53a73371a1 100644 --- a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld +++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld @@ -31,9 +31,9 @@ MEMORY VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00000800; -__msp_stack_size__ = 0x00000800; +__heap_size__ = S_HEAP_SIZE; +__psp_stack_size__ = S_PSP_STACK_SIZE; +__msp_init_stack_size__ = S_MSP_STACK_SIZE_INIT; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a) @@ -356,6 +356,28 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH + /* shared_data and msp_stack are overlapping on purpose when + * msp_stack is extended until the beginning of RAM, when shared_date + * was read out by partitions + */ + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM AT> FLASH + + .msp_stack : ALIGN(32) + { + . += __msp_init_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .psp_stack : ALIGN(32) + { + . += __psp_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + #if TFM_LVL == 1 .TFM_SECURE_STACK : ALIGN(128) @@ -683,19 +705,6 @@ SECTIONS Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); - .psp_stack : ALIGN(128) - { - . += __psp_stack_size__; - } > RAM AT> FLASH - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : ALIGN(128) - { - . += __msp_stack_size__; - } > RAM AT> FLASH - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); - /* * Place the CMSE Veneers (containing the SG instruction) after the code, in a * separate 32 bytes aligned region so that the SAU can programmed to just set @@ -714,6 +723,5 @@ SECTIONS Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = __initial_sp); - PROVIDE(Stack_top = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template index 8a837f40b8..738344d8dc 100644 --- a/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template +++ b/platform/ext/target/musca_a/Device/Source/gcc/musca_s.ld.template @@ -31,9 +31,9 @@ MEMORY VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00000800; -__msp_stack_size__ = 0x00000800; +__heap_size__ = S_HEAP_SIZE; +__psp_stack_size__ = S_PSP_STACK_SIZE; +__msp_init_stack_size__ = S_MSP_STACK_SIZE_INIT; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a) @@ -215,6 +215,28 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH + /* shared_data and msp_stack are overlapping on purpose when + * msp_stack is extended until the beginning of RAM, when shared_date + * was read out by partitions + */ + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM AT> FLASH + + .msp_stack : ALIGN(32) + { + . += __msp_init_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .psp_stack : ALIGN(32) + { + . += __psp_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + #if TFM_LVL == 1 .TFM_SECURE_STACK : ALIGN(128) @@ -364,19 +386,6 @@ SECTIONS Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); - .psp_stack : ALIGN(128) - { - . += __psp_stack_size__; - } > RAM AT> FLASH - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : ALIGN(128) - { - . += __msp_stack_size__; - } > RAM AT> FLASH - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); - /* * Place the CMSE Veneers (containing the SG instruction) after the code, in a * separate 32 bytes aligned region so that the SAU can programmed to just set @@ -395,6 +404,5 @@ SECTIONS Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = __initial_sp); - PROVIDE(Stack_top = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S index 32d21735d4..06b06fd37b 100644 --- a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S +++ b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_bl2.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -258,9 +258,6 @@ not_the_core_to_run_on: bl SystemInit - ldr r0, =__initial_sp - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S index 43db00bf27..299cd5f275 100644 --- a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S +++ b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_ns.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -252,7 +252,7 @@ Reset_Handler: orr r0, r0, #1 /* Select switch to unprivilage mode */ orr r0, r0, #2 /* Select switch to PSP */ msr control, r0 - ldr r0, =__initial_sp + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit msr psp, r0 #ifndef __START diff --git a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S index 576795a573..152d64c802 100644 --- a/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S +++ b/platform/ext/target/musca_a/Device/Source/gcc/startup_cmsdk_musca_s.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -254,7 +254,7 @@ Reset_Handler: mrs r0, control /* Get control value */ orr r0, r0, #2 /* Select switch to PSP */ msr control, r0 - ldr r0, =__initial_sp + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit msr psp, r0 #ifndef __START diff --git a/platform/ext/target/musca_a/partition/flash_layout.h b/platform/ext/target/musca_a/partition/flash_layout.h index 3f1d1ce902..b6bab4f29f 100755 --- a/platform/ext/target/musca_a/partition/flash_layout.h +++ b/platform/ext/target/musca_a/partition/flash_layout.h @@ -137,4 +137,15 @@ #define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET #define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE +/* FIXME: Use SRAM2 memory to store RW data */ +#define S_RAM_ALIAS_BASE (0x30000000) +#define NS_RAM_ALIAS_BASE (0x20000000) + +/* Shared data area between bootloader and runtime firmware. + * Shared data area is allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE +#define BOOT_TFM_SHARED_DATA_SIZE 0x400 + #endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/musca_a/partition/region_defs.h b/platform/ext/target/musca_a/partition/region_defs.h index b45d40d645..d88e898cd7 100755 --- a/platform/ext/target/musca_a/partition/region_defs.h +++ b/platform/ext/target/musca_a/partition/region_defs.h @@ -22,6 +22,18 @@ #define TOTAL_ROM_SIZE (0x00200000) /* 2 MB */ #define TOTAL_RAM_SIZE (0x00020000) /* 128KB */ +#define BL2_HEAP_SIZE 0x0001000 +#define BL2_MSP_STACK_SIZE 0x0001000 + +#define S_HEAP_SIZE 0x0001000 +#define S_MSP_STACK_SIZE_INIT 0x0000400 +#define S_MSP_STACK_SIZE 0x0000800 +#define S_PSP_STACK_SIZE 0x0000800 + +#define NS_HEAP_SIZE 0x0001000 +#define NS_MSP_STACK_SIZE 0x0000400 +#define NS_PSP_STACK_SIZE 0x0000C00 + /* * MPC granularity is 128 KB on Musca. Alignment * of partitions is defined in accordance with this constraint. diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/musca_bl2.sct b/platform/ext/target/musca_b1/Device/Source/armclang/musca_bl2.sct index 16ebeacdb3..d7101f4fd0 100644 --- a/platform/ext/target/musca_b1/Device/Source/armclang/musca_bl2.sct +++ b/platform/ext/target/musca_b1/Device/Source/armclang/musca_bl2.sct @@ -24,7 +24,17 @@ LR_CODE BL2_CODE_START { .ANY (+RO) } - ER_DATA BL2_DATA_START BL2_DATA_SIZE { + TFM_SHARED_DATA BL2_DATA_START ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + ER_DATA +0 BL2_DATA_SIZE { .ANY (+ZI +RW) } + + /* MSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL2_HEAP_SIZE { + } } diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/musca_ns.sct b/platform/ext/target/musca_b1/Device/Source/armclang/musca_ns.sct index 87ca3e3fa6..b9d15fabae 100644 --- a/platform/ext/target/musca_b1/Device/Source/armclang/musca_ns.sct +++ b/platform/ext/target/musca_b1/Device/Source/armclang/musca_ns.sct @@ -27,5 +27,16 @@ LR_CODE NS_CODE_START { ER_DATA NS_DATA_START NS_DATA_SIZE { .ANY (+ZI +RW) } + + /* MSP */ + ARM_LIB_STACK_MSP +0 ALIGN 32 EMPTY NS_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY NS_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY NS_HEAP_SIZE { + } } diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct b/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct index 5af3a77526..fe8e6ecb6e 100644 --- a/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct +++ b/platform/ext/target/musca_b1/Device/Source/armclang/musca_s.sct @@ -28,7 +28,22 @@ LR_CODE S_CODE_START { #if TFM_LVL == 1 - ER_TFM_DATA S_DATA_START S_DATA_SIZE { + /* Shared area between BL2 and runtime to exchange data */ + TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + /* MSP */ + ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { + } + + ER_TFM_DATA +0 { .ANY (+RW +ZI) } @@ -101,7 +116,22 @@ LR_CODE S_CODE_START { } #endif /* TFM_PARTITION_TEST_SECURE_SERVICES */ - ER_TFM_DATA S_DATA_START S_DATA_SIZE { + /* Shared area between BL2 and runtime to exchange data */ + TFM_SHARED_DATA S_DATA_START ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE { + } + + /* MSP */ + ARM_LIB_STACK_MSP S_DATA_START ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE { + } + + /* PSP */ + ARM_LIB_STACK +0 ALIGN 32 EMPTY S_PSP_STACK_SIZE { + } + + ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE { + } + + ER_TFM_DATA +0 { .ANY (+RW +ZI) } diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_bl2.s b/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_bl2.s index cbc0603cc0..9241cf4c35 100644 --- a/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_bl2.s +++ b/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_bl2.s @@ -26,24 +26,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000800 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT Stack_Mem -Stack_Mem SPACE Stack_Size -__initial_msp -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -53,7 +36,7 @@ __heap_limit EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD __initial_msp ; Top of Stack + DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -262,29 +245,4 @@ $handler_name PROC ALIGN -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ENDIF - - ALIGN - END diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_ns.s b/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_ns.s index a4268c56d3..8c1cc5a9f5 100644 --- a/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_ns.s +++ b/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_ns.s @@ -26,24 +26,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT Stack_Mem -Stack_Mem SPACE Stack_Size -__initial_msp -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -53,7 +36,7 @@ __heap_limit EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD __initial_msp ; Top of Stack + DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -160,7 +143,7 @@ Reset_Handler PROC IMPORT __main MRS R0, control ; Get control value ORR R0, R0, #1 ; Select switch to unprivilage mode - ORR R0, R0, #2 ; Select switch to PSP, which will be set by __user_initial_stackheap + ORR R0, R0, #2 ; Select switch to PSP MSR control, R0 LDR R0, =__main BX R0 @@ -258,29 +241,4 @@ $handler_name PROC ALIGN -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ENDIF - - ALIGN - END diff --git a/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_s.s b/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_s.s index a9c0e98be9..7a9fdb1330 100644 --- a/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_s.s +++ b/platform/ext/target/musca_b1/Device/Source/armclang/startup_cmsdk_musca_s.s @@ -26,26 +26,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00001000 -MSP_STACK_SIZE EQU 0x00000800 - - AREA STACK, NOINIT, READWRITE, ALIGN=7 - EXPORT Stack_Mem -Stack_Mem SPACE Stack_Size -__initial_msp -__initial_sp EQU __initial_msp - MSP_STACK_SIZE - EXPORT Stack_top -Stack_top EQU __initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit + IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Vector Table Mapped to Address 0 at Reset @@ -55,7 +36,7 @@ __heap_limit EXPORT __Vectors_Size __Vectors ;Core Interrupts - DCD __initial_msp ; Top of Stack + DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -165,7 +146,7 @@ Reset_Handler PROC LDR R0, =SystemInit BLX R0 MRS R0, control ; Get control value - ORR R0, R0, #2 ; Select switch to PSP, which will be set by __user_initial_stackheap + ORR R0, R0, #2 ; Select switch to PSP MSR control, R0 LDR R0, =__main BX R0 @@ -268,29 +249,4 @@ $handler_name PROC ALIGN -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, = __initial_sp - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ENDIF - - ALIGN - END diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/musca_bl2.ld b/platform/ext/target/musca_b1/Device/Source/gcc/musca_bl2.ld index 86f9f5cf1b..c3ab95028c 100644 --- a/platform/ext/target/musca_b1/Device/Source/gcc/musca_bl2.ld +++ b/platform/ext/target/musca_b1/Device/Source/gcc/musca_bl2.ld @@ -28,9 +28,8 @@ MEMORY RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE } -__heap_size__ = 0x00010000; -__psp_stack_size__ = 0x00000800; -__msp_stack_size__ = 0x00000800; +__heap_size__ = BL2_HEAP_SIZE; +__msp_stack_size__ = BL2_MSP_STACK_SIZE; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a) @@ -115,6 +114,13 @@ SECTIONS __etext = .; + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM + Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data); + Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data); + .data : AT (__etext) { __data_start__ = .; @@ -161,33 +167,13 @@ SECTIONS bss_size = __bss_end__ - __bss_start__; - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - .psp_stack : + .msp_stack : ALIGN(32) { - . = ALIGN(8); - KEEP(*(.psp_stack*)) - . += __psp_stack_size__; - } > RAM - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : - { - . = ALIGN(8); - KEEP(*(.psp_stack*)) . += __msp_stack_size__; } > RAM - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); - .heap : + .heap : ALIGN(8) { . = ALIGN(8); __end__ = .; @@ -198,5 +184,5 @@ SECTIONS __heap_limit = .; /* Add for _sbrk */ } > RAM - PROVIDE( __stack = __initial_msp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/musca_ns.ld b/platform/ext/target/musca_b1/Device/Source/gcc/musca_ns.ld index 76fe881f31..ad174c839d 100644 --- a/platform/ext/target/musca_b1/Device/Source/gcc/musca_ns.ld +++ b/platform/ext/target/musca_b1/Device/Source/gcc/musca_ns.ld @@ -28,9 +28,9 @@ MEMORY RAM (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00000C00; -__msp_stack_size__ = 0x00000400; +__heap_size__ = NS_HEAP_SIZE; +__psp_stack_size__ = NS_PSP_STACK_SIZE; +__msp_stack_size__ = NS_MSP_STACK_SIZE; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a) @@ -161,33 +161,20 @@ SECTIONS bss_size = __bss_end__ - __bss_start__; - .heap (COPY): + .msp_stack : ALIGN(32) { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; + . += __msp_stack_size__; } > RAM + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); - .psp_stack : + .psp_stack : ALIGN(32) { - . = ALIGN(8); - KEEP(*(.psp_stack*)) . += __psp_stack_size__; } > RAM - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : - { - . = ALIGN(8); - KEEP(*(.psp_stack*)) - . += __msp_stack_size__; - } > RAM - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); - .heap : + .heap : ALIGN(8) { . = ALIGN(8); __end__ = .; @@ -198,5 +185,5 @@ SECTIONS __heap_limit = .; /* Add for _sbrk */ } > RAM - PROVIDE(__stack = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld index 2545230fdb..7cc9551f36 100644 --- a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld +++ b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld @@ -31,9 +31,9 @@ MEMORY VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00000800; -__msp_stack_size__ = 0x00000800; +__heap_size__ = S_HEAP_SIZE; +__psp_stack_size__ = S_PSP_STACK_SIZE; +__msp_init_stack_size__ = S_MSP_STACK_SIZE_INIT; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a) @@ -356,6 +356,28 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH + /* shared_data and msp_stack are overlapping on purpose when + * msp_stack is extended until the beginning of RAM, when shared_date + * was read out by partitions + */ + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM AT> FLASH + + .msp_stack : ALIGN(32) + { + . += __msp_init_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .psp_stack : ALIGN(32) + { + . += __psp_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + #if TFM_LVL == 1 .TFM_SECURE_STACK : ALIGN(128) @@ -683,19 +705,6 @@ SECTIONS Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); - .psp_stack : ALIGN(128) - { - . += __psp_stack_size__; - } > RAM AT> FLASH - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : ALIGN(128) - { - . += __msp_stack_size__; - } > RAM AT> FLASH - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); - /* * Place the CMSE Veneers (containing the SG instruction) after the code, in a * separate 32 bytes aligned region so that the SAU can programmed to just set @@ -714,6 +723,5 @@ SECTIONS Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = __initial_sp); - PROVIDE(Stack_top = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template index e92c20cda3..b5dbc1fda3 100644 --- a/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template +++ b/platform/ext/target/musca_b1/Device/Source/gcc/musca_s.ld.template @@ -31,9 +31,9 @@ MEMORY VENEERS (rx) : ORIGIN = CMSE_VENEER_REGION_START, LENGTH = CMSE_VENEER_REGION_SIZE } -__heap_size__ = 0x00001000; -__psp_stack_size__ = 0x00000800; -__msp_stack_size__ = 0x00000800; +__heap_size__ = S_HEAP_SIZE; +__psp_stack_size__ = S_PSP_STACK_SIZE; +__msp_init_stack_size__ = S_MSP_STACK_SIZE_INIT; /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a libc_nano.a) @@ -215,6 +215,28 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH + /* shared_data and msp_stack are overlapping on purpose when + * msp_stack is extended until the beginning of RAM, when shared_date + * was read out by partitions + */ + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM AT> FLASH + + .msp_stack : ALIGN(32) + { + . += __msp_init_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .psp_stack : ALIGN(32) + { + . += __psp_stack_size__; + } > RAM AT> FLASH + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack); + #if TFM_LVL == 1 .TFM_SECURE_STACK : ALIGN(128) @@ -364,19 +386,6 @@ SECTIONS Image$$TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); Image$$TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); - .psp_stack : ALIGN(128) - { - . += __psp_stack_size__; - } > RAM AT> FLASH - __initial_sp = ADDR(.psp_stack) + SIZEOF(.psp_stack); - Stack_Mem = ADDR(.psp_stack); - - .msp_stack : ALIGN(128) - { - . += __msp_stack_size__; - } > RAM AT> FLASH - __initial_msp = ADDR(.msp_stack) + SIZEOF(.msp_stack); - /* * Place the CMSE Veneers (containing the SG instruction) after the code, in a * separate 32 bytes aligned region so that the SAU can programmed to just set @@ -395,6 +404,5 @@ SECTIONS Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; #endif /* BL2 */ - PROVIDE(__stack = __initial_sp); - PROVIDE(Stack_top = __initial_sp); + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); } diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_bl2.S b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_bl2.S index 32d21735d4..06b06fd37b 100644 --- a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_bl2.S +++ b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_bl2.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -258,9 +258,6 @@ not_the_core_to_run_on: bl SystemInit - ldr r0, =__initial_sp - msr psp, r0 - #ifndef __START #define __START _start #endif diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_ns.S b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_ns.S index 43db00bf27..299cd5f275 100644 --- a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_ns.S +++ b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_ns.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -252,7 +252,7 @@ Reset_Handler: orr r0, r0, #1 /* Select switch to unprivilage mode */ orr r0, r0, #2 /* Select switch to PSP */ msr control, r0 - ldr r0, =__initial_sp + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit msr psp, r0 #ifndef __START diff --git a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_s.S b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_s.S index 576795a573..152d64c802 100644 --- a/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_s.S +++ b/platform/ext/target/musca_b1/Device/Source/gcc/startup_cmsdk_musca_s.S @@ -24,7 +24,7 @@ .align 2 .globl __Vectors __Vectors: - .long __initial_msp /* Top of Stack */ + .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler */ .long HardFault_Handler /* Hard Fault Handler */ @@ -254,7 +254,7 @@ Reset_Handler: mrs r0, control /* Get control value */ orr r0, r0, #2 /* Select switch to PSP */ msr control, r0 - ldr r0, =__initial_sp + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit msr psp, r0 #ifndef __START diff --git a/platform/ext/target/musca_b1/partition/flash_layout.h b/platform/ext/target/musca_b1/partition/flash_layout.h index 24be932649..527dec5359 100644 --- a/platform/ext/target/musca_b1/partition/flash_layout.h +++ b/platform/ext/target/musca_b1/partition/flash_layout.h @@ -121,4 +121,15 @@ #define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET #define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE +/* FIXME: Use SRAM2 memory to store RW data */ +#define S_RAM_ALIAS_BASE (0x30000000) +#define NS_RAM_ALIAS_BASE (0x20000000) + +/* Shared data area between bootloader and runtime firmware. + * Shared data area is allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE +#define BOOT_TFM_SHARED_DATA_SIZE 0x400 + #endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/musca_b1/partition/region_defs.h b/platform/ext/target/musca_b1/partition/region_defs.h index b6b7c9ac76..f85be1b82d 100644 --- a/platform/ext/target/musca_b1/partition/region_defs.h +++ b/platform/ext/target/musca_b1/partition/region_defs.h @@ -22,8 +22,21 @@ #define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE #define TOTAL_RAM_SIZE (0x00080000) /* 512 KB */ -/* MPC granularity is 128 KB on Musca-B1. Alignment of partitions is defined in - * accordance with this constraint. +#define BL2_HEAP_SIZE 0x0001000 +#define BL2_MSP_STACK_SIZE 0x0001000 + +#define S_HEAP_SIZE 0x0001000 +#define S_MSP_STACK_SIZE_INIT 0x0000400 +#define S_MSP_STACK_SIZE 0x0000800 +#define S_PSP_STACK_SIZE 0x0000800 + +#define NS_HEAP_SIZE 0x0001000 +#define NS_MSP_STACK_SIZE 0x0000400 +#define NS_PSP_STACK_SIZE 0x0000C00 + +/* + * MPC granularity is 128 KB on Musca. Alignment + * of partitions is defined in accordance with this constraint. */ #ifdef BL2 #ifndef LINK_TO_SECONDARY_PARTITION diff --git a/secure_fw/core/tfm_core.c b/secure_fw/core/tfm_core.c index 4066f3ad18..68c5e23b77 100644 --- a/secure_fw/core/tfm_core.c +++ b/secure_fw/core/tfm_core.c @@ -199,9 +199,10 @@ int main(void) tfm_spm_partition_set_state(TFM_SP_CORE_ID, SPM_PARTITION_STATE_RUNNING); - extern uint32_t Stack_Mem[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; + uint32_t psp_stack_bottom = (uint32_t)Image$$ARM_LIB_STACK$$ZI$$Base; - __set_PSPLIM((uint32_t)Stack_Mem); + __set_PSPLIM(psp_stack_bottom); if (tfm_spm_partition_init() != SPM_ERR_OK) { /* Certain systems might refuse to boot altogether if partitions fail diff --git a/secure_fw/core/tfm_secure_api.c b/secure_fw/core/tfm_secure_api.c index 8f7404735f..d3a0f952ba 100644 --- a/secure_fw/core/tfm_secure_api.c +++ b/secure_fw/core/tfm_secure_api.c @@ -300,8 +300,10 @@ static int32_t tfm_return_from_partition(uint32_t *excReturn) (struct tfm_exc_stack_t *)ret_part_data->stack_ptr); *excReturn = ret_part_data->lr; __set_PSP(ret_part_data->stack_ptr); - extern uint32_t Stack_Mem[]; - __set_PSPLIM((uint32_t)Stack_Mem); + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; + uint32_t psp_stack_bottom = (uint32_t)Image$$ARM_LIB_STACK$$ZI$$Base; + __set_PSPLIM(psp_stack_bottom); + } #else /* Restore caller context */ diff --git a/secure_fw/spm/spm_api.c b/secure_fw/spm/spm_api.c index 83d44144d3..b17ee99d4a 100644 --- a/secure_fw/spm/spm_api.c +++ b/secure_fw/spm/spm_api.c @@ -83,8 +83,10 @@ enum spm_err_t tfm_spm_db_init(void) /* For the non secure Execution environment */ #if TFM_LVL != 1 - extern uint32_t Stack_Mem[]; - extern uint32_t Stack_top[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[]; + uint32_t psp_stack_bottom = (uint32_t)Image$$ARM_LIB_STACK$$ZI$$Base; + uint32_t psp_stack_top = (uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit; #endif if (g_spm_partition_db.partition_count >= SPM_MAX_PARTITIONS) { return SPM_ERR_INVALID_CONFIG; @@ -95,12 +97,12 @@ enum spm_err_t tfm_spm_db_init(void) part_ptr->static_data.partition_flags = 0; #if TFM_LVL != 1 - part_ptr->memory_data.stack_bottom = (uint32_t)Stack_Mem; - part_ptr->memory_data.stack_top = (uint32_t)Stack_top; + part_ptr->memory_data.stack_bottom = psp_stack_bottom; + part_ptr->memory_data.stack_top = psp_stack_top; /* Since RW, ZI and stack are configured as one MPU region, configure - * RW start address to Stack_Mem to get RW access to stack + * RW start address to psp_stack_bottom to get RW access to stack */ - part_ptr->memory_data.rw_start = (uint32_t)Stack_Mem; + part_ptr->memory_data.rw_start = psp_stack_bottom; #endif part_ptr->runtime_data.partition_state = SPM_PARTITION_STATE_UNINIT; -- cgit v1.2.3