diff options
author | Raef Coles <raef.coles@arm.com> | 2023-01-13 16:12:24 +0000 |
---|---|---|
committer | Anton Komlev <Anton.Komlev@arm.com> | 2023-02-06 16:58:30 +0100 |
commit | dd7a2f26418d8ade13d45139c2750444478e23f8 (patch) | |
tree | fe89aba2efec5756067b48d30e792c769e2f44e7 | |
parent | 9c4d9d93b151c83b60a5b7c9aabccc6f175c8104 (diff) | |
download | trusted-firmware-m-dd7a2f26418d8ade13d45139c2750444478e23f8.tar.gz |
RSS: Alter RAM layout
To allow BL2 code segments larger than 64KiB. Move some data into DTCM,
and rearrange runtime data/code segments to get a contiguous 128KiB area
to map BL2 code into. Increase the size of BL2 code to 96KiB.
Change-Id: Ibd5b637cbbda9c30104444e96273c0314586869a
Signed-off-by: Raef Coles <raef.coles@arm.com>
3 files changed, 85 insertions, 56 deletions
diff --git a/platform/ext/target/arm/rss/common/partition/flash_layout.h b/platform/ext/target/arm/rss/common/partition/flash_layout.h index 25cb7dfa6f..36985ae1a1 100644 --- a/platform/ext/target/arm/rss/common/partition/flash_layout.h +++ b/platform/ext/target/arm/rss/common/partition/flash_layout.h @@ -161,13 +161,19 @@ #define NON_SECURE_IMAGE_MAX_SIZE FLASH_SIC_TABLE_SIZE #endif /* !RSS_XIP */ +#if !defined(RSS_XIP) && \ + FLASH_BL2_PARTITION_SIZE + FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE \ + > VM0_SIZE + VM1_SIZE +#error Partition sizes are too large to load into RSS SRAM +#endif + /* Image load addresses used by imgtool.py */ #ifdef RSS_XIP -#define S_IMAGE_LOAD_ADDRESS (VM0_BASE_S + BOOT_TFM_SHARED_DATA_SIZE) +#define S_IMAGE_LOAD_ADDRESS (VM0_BASE_S + FLASH_BL2_PARTITION_SIZE) #define NS_IMAGE_LOAD_ADDRESS (S_IMAGE_LOAD_ADDRESS + \ FLASH_SIC_TABLE_SIZE) #else -#define S_IMAGE_LOAD_ADDRESS (VM0_BASE_S + VM0_SIZE - FLASH_S_PARTITION_SIZE) +#define S_IMAGE_LOAD_ADDRESS (VM0_BASE_S) #define NS_IMAGE_LOAD_ADDRESS (VM1_BASE_S + VM1_SIZE - FLASH_NS_PARTITION_SIZE) #endif diff --git a/platform/ext/target/arm/rss/common/partition/region_defs.h b/platform/ext/target/arm/rss/common/partition/region_defs.h index eedb600b46..d3ea17a6fe 100644 --- a/platform/ext/target/arm/rss/common/partition/region_defs.h +++ b/platform/ext/target/arm/rss/common/partition/region_defs.h @@ -21,44 +21,65 @@ #include "platform_base_address.h" /* RSS memory layout is as follows during BL1 - * |--------------------------------------------------------- - * VM0 | BOOT_SHARED | BL1_2_CODE | BL1_1_DATA | BL1_2_DATA | - * |--------------------------------------------------------- - * |--------------------------------------------------------- - * VM1 | BL2_CODE | - * |--------------------------------------------------------- + * |----------------------------------------| + * DTCM | BOOT_SHARED | BL1_1_DATA | BL1_2_DATA | + * |----------------------------------------| + * + * |----------------------------------------| + * ITCM | BL1_2_CODE | | + * |----------------------------------------| + * + * |--------------------------------------------------------- + * VM0 | | + * |--------------------------------------------------------- + * |--------------------------------------------------------- + * VM1 | | + * |--------------------------------------------------------- * * If the size of VM0 and VM1 are larger than 64KiB, the size of BL1 code/data * and BL2 code can be increased to fill the extra space. * * RSS memory layout is as follows during BL2 - * |--------------------------------------------------------- - * VM0 | BOOT_SHARED | ?XIP tables | BL2_DATA | - * |--------------------------------------------------------- - * |--------------------------------------------------------- - * VM1 | BL2_CODE | - * |--------------------------------------------------------- + * |----------------------------------------| + * DTCM | BOOT_SHARED | | + * |----------------------------------------| + * + * |--------------------------------------------------------- + * VM0 | BL2_CODE | + * |--------------------------------------------------------- + * |--------------------------------------------------------- + * VM1 | BL2_CODE | XIP tables | BL2_DATA | + * |--------------------------------------------------------- * - * If the size of VM0 and VM1 are larger than 64KiB, the size of BL2 code and - * data can be increased to fill the extra space. + * If the size of VM0 and VM1 are larger than 64KiB, the size of BL2 code can be + * increased to fill the extra space. Note that BL2 code is aligned to the start + * of S_DATA, so under non-XIP mode it will not start at the beginning of VM0. * * RSS memory layout is as follows during Runtime with XIP mode enabled - * |--------------------------------------------------------- - * VM0 | BOOT_SHARED+S_DATA | - * |--------------------------------------------------------- - * |--------------------------------------------------------- - * VM1 | S_DATA | NS_DATA | - * |--------------------------------------------------------- + * |----------------------------------------| + * DTCM | BOOT_SHARED | | + * |----------------------------------------| + * + * |--------------------------------------------------------- + * VM0 | S_DATA | + * |--------------------------------------------------------- + * |--------------------------------------------------------- + * VM1 | S_DATA | NS_DATA | + * |--------------------------------------------------------- * * RSS memory layout is as follows during Runtime with XIP mode disabled. Note * that each SRAM must be at least 512KiB in this mode (64KiB data and 384KiB * code, for each of secure and non-secure). - * |-----------------------------------------------------------------------| - * VM0 | BOOT_SHARED+S_DATA | S_CODE | - * |-----------------------------------------------------------------------| - * |-----------------------------------------------------------------------| - * VM1 | NS_DATA | NS_CODE | - * |-----------------------------------------------------------------------| + * |----------------------------------------| + * DTCM | BOOT_SHARED | | + * |----------------------------------------| + * + * |----------------------------------------------------------------------| + * VM0 | S_CODE | S_DATA | + * |----------------------------------------------------------------------| + * |----------------------------------------------------------------------| + * VM1 | NS_DATA | NS_CODE | + * |----------------------------------------------------------------------| */ #define BL1_1_HEAP_SIZE (0x0001000) @@ -118,11 +139,12 @@ #define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) /* Secure Data stored in VM0. Size defined in flash layout */ -#define S_DATA_START (VM0_BASE_S) #ifdef RSS_XIP -#define S_DATA_SIZE (VM0_SIZE + VM1_SIZE / 2) +#define S_DATA_START (VM0_BASE_S) +#define S_DATA_SIZE (VM0_SIZE + (VM1_SIZE / 2)) #else -#define S_DATA_SIZE (VM0_SIZE - FLASH_S_PARTITION_SIZE) +#define S_DATA_START (VM0_BASE_S + FLASH_S_PARTITION_SIZE) +#define S_DATA_SIZE (VM0_SIZE - FLASH_S_PARTITION_SIZE) #endif /* RSS_XIP */ #define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) @@ -135,12 +157,12 @@ #define NS_CODE_START (RSS_RUNTIME_NS_XIP_BASE_NS) #define NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE) #else -#define NS_CODE_START (VM1_BASE_NS + NS_DATA_SIZE + BL2_HEADER_SIZE) +#define NS_CODE_START (NS_DATA_START + NS_DATA_SIZE) #define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) #endif /* RSS_XIP */ #define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) -/* Non-Secure Data stored after secure data, or in VM1. */ +/* Non-Secure Data stored after secure data, or in VM1 if not in XIP mode. */ #ifdef RSS_XIP #define NS_DATA_START (VM0_BASE_NS + S_DATA_SIZE) #define NS_DATA_SIZE ((VM0_SIZE + VM1_SIZE) - S_DATA_SIZE) @@ -171,43 +193,44 @@ #define PROVISIONING_DATA_SIZE (0x2400) /* 9 KB */ #define PROVISIONING_DATA_LIMIT (PROVISIONING_DATA_START + PROVISIONING_DATA_SIZE - 1) -/* BL1_2 executes from VM0, leaving space for the shared data */ -#define BL1_2_CODE_START (VM0_BASE_S + BOOT_TFM_SHARED_DATA_SIZE) +/* BL1_2 is in the ITCM */ +#define BL1_2_CODE_START (ITCM_BASE_S) #define BL1_2_CODE_SIZE (0x2000) /* 8 KiB */ #define BL1_2_CODE_LIMIT (BL1_2_CODE_START + BL1_2_CODE_SIZE - 1) -/* BL2 executes from VM1 */ -#define BL2_IMAGE_START (VM1_BASE_S) +/* BL2 is aligned to the start of the combined secure/non-secure data region */ +#define BL2_IMAGE_START (S_DATA_START) #define BL2_CODE_START (BL2_IMAGE_START + BL1_HEADER_SIZE) #define BL2_CODE_SIZE (IMAGE_BL2_CODE_SIZE) #define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) -/* BL1 data is in VM0 */ -#define BL1_1_DATA_START (BL1_2_CODE_START + BL1_2_CODE_SIZE) -#define BL1_1_DATA_SIZE ((VM0_SIZE - BOOT_TFM_SHARED_DATA_SIZE \ - - BL1_2_CODE_SIZE) / 2) +#if FLASH_BL2_PARTITION_SIZE + BL2_DATA_SIZE + XIP_TABLE_SIZE > VM0_SIZE + VM1_SIZE +#error FLASH_BL2_PARTITION_SIZE + BL2_DATA_SIZE + 2 * FLASH_SIC_TABLE_SIZE is too large to fit in RSS SRAM +#endif + +/* BL1 data is in DTCM */ +#define BL1_1_DATA_START (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE) +#define BL1_1_DATA_SIZE ((DTCM_SIZE - BOOT_TFM_SHARED_DATA_SIZE) / 2) #define BL1_1_DATA_LIMIT (BL1_1_DATA_START + BL1_1_DATA_SIZE - 1) #define BL1_2_DATA_START (BL1_1_DATA_START + BL1_1_DATA_SIZE) -#define BL1_2_DATA_SIZE ((VM0_SIZE - BOOT_TFM_SHARED_DATA_SIZE \ - - BL1_2_CODE_SIZE) / 2) +#define BL1_2_DATA_SIZE ((DTCM_SIZE - BOOT_TFM_SHARED_DATA_SIZE) / 2) #define BL1_2_DATA_LIMIT (BL1_2_DATA_START + BL1_2_DATA_SIZE - 1) -/* XIP data go after the reserved space for boot_data */ -#define BL2_XIP_TABLES_START (VM0_BASE_S + BOOT_TFM_SHARED_DATA_SIZE) -#define BL2_XIP_TABLES_SIZE (0x5000) /* 20 KiB */ +/* XIP data goes after the BL2 image */ +#define BL2_XIP_TABLES_START (BL2_IMAGE_START + FLASH_BL2_PARTITION_SIZE) +#define BL2_XIP_TABLES_SIZE (FLASH_SIC_TABLE_SIZE * 2) #define BL2_XIP_TABLES_LIMIT (BL2_XIP_TABLES_START + BL2_XIP_TABLES_SIZE - 1) -/* BL2 data is in VM0, in the same space as BL1 data */ +/* BL2 data is after the code. TODO FIXME this should be in DTCM once the CC3XX + * runtime driver supports DMA remapping. + */ #define BL2_DATA_START (BL2_XIP_TABLES_START + BL2_XIP_TABLES_SIZE) -#define BL2_DATA_SIZE (VM0_SIZE - BL2_XIP_TABLES_SIZE \ - - BOOT_TFM_SHARED_DATA_SIZE) +#define BL2_DATA_SIZE (DTCM_SIZE - BOOT_TFM_SHARED_DATA_SIZE) #define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) -/* Store boot data is in the start of VM0. It overlaps with the secure data - * region - */ -#define BOOT_TFM_SHARED_DATA_BASE VM0_BASE_S +/* Store boot data at the start of the DTCM. */ +#define BOOT_TFM_SHARED_DATA_BASE DTCM_BASE_S #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) diff --git a/platform/ext/target/arm/rss/tc/host_flash_layout.h b/platform/ext/target/arm/rss/tc/host_flash_layout.h index b3d108ce8b..f667920b86 100644 --- a/platform/ext/target/arm/rss/tc/host_flash_layout.h +++ b/platform/ext/target/arm/rss/tc/host_flash_layout.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,7 +19,7 @@ /* Sizes of a images */ -#define FLASH_BL2_PARTITION_SIZE (0x10000) /* BL2 partition: 128 KiB */ +#define FLASH_BL2_PARTITION_SIZE (0x18000) /* BL2 partition: 96 KiB */ #define FLASH_S_PARTITION_SIZE (0x60000) /* S partition: 384 KiB */ #define FLASH_NS_PARTITION_SIZE (0x60000) /* NS partition: 384 KiB */ #define FLASH_AP_PARTITION_SIZE (0x80000) /* AP partition: 512 KiB */ @@ -29,7 +29,7 @@ /* Each table contains a bit less that 8KiB of HTR and 2KiB of mcuboot headers. * The spare space in the 8KiB is used for decryption IVs. */ -#define FLASH_SIC_TABLE_SIZE (0xA000) /* 10KiB */ +#define FLASH_SIC_TABLE_SIZE (0x2800) /* 10KiB */ #endif /* RSS_XIP */ /* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */ |