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authorMichel Jaouen <michel.jaouen@st.com>2020-07-23 14:13:02 +0200
committerMichel Jaouen <michel.jaouen@st.com>2020-08-13 11:13:09 +0200
commit6242cf598819975ddb53a95b80412e498a6f34f5 (patch)
treed6cf4f64f6747453582bdc44c609f3b5195c67c7
parent664d13644d15f2bbcae791647200a7c89ce65676 (diff)
downloadtrusted-firmware-m-6242cf598819975ddb53a95b80412e498a6f34f5.tar.gz
Platform: stm32l5xx: Add ARMCLANG and IAR support
Factorize startup file in c for all compiler and the stm32l5xx boards. Change-Id: I06c9aa57211f6cbc9055a15c8eb2a96c89b81dd8 Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_bl2.sct54
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_ns.sct44
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_bl2.S430
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_ns.S417
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_s.S426
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_bl2.S431
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_ns.S418
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_s.S427
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_bl2.icf42
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_flash_ns.icf34
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_bl2.c337
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_ns.c351
-rw-r--r--platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_s.c361
-rw-r--r--platform/ext/target/stm/stm32l5xx/bl2/boot_hal.c38
-rw-r--r--platform/ext/target/stm/stm32l5xx/boards/nucleo_l552ze_q/flash_layout.h4
-rw-r--r--platform/ext/target/stm/stm32l5xx/boards/scripts/armclang/preprocess.sh20
-rw-r--r--platform/ext/target/stm/stm32l5xx/boards/scripts/gcc/preprocess.sh20
-rw-r--r--platform/ext/target/stm/stm32l5xx/boards/scripts/iar/preprocess.sh20
-rw-r--r--[-rwxr-xr-x]platform/ext/target/stm/stm32l5xx/boards/scripts/postbuild.sh3
-rw-r--r--platform/ext/target/stm/stm32l5xx/boards/stm32l562e_dk/flash_layout.h4
-rw-r--r--platform/ext/target/stm/stm32l5xx/nucleo_l552ze_q.cmake41
-rw-r--r--platform/ext/target/stm/stm32l5xx/secure/system_stm32l5xx.c4
-rw-r--r--platform/ext/target/stm/stm32l5xx/secure/target_cfg.c5
-rw-r--r--platform/ext/target/stm/stm32l5xx/stm32l562e_dk.cmake37
-rw-r--r--platform/ext/target/stm/stm32l5xx/stm32l5xx.cmake24
25 files changed, 1389 insertions, 2603 deletions
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_bl2.sct b/platform/ext/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_bl2.sct
new file mode 100644
index 0000000000..3b7b5a1bea
--- /dev/null
+++ b/platform/ext/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_bl2.sct
@@ -0,0 +1,54 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "region_defs.h"
+
+LR_CODE BL2_CODE_START {
+
+ ER_CODE (BL2_CODE_START) FIXED (BL2_CODE_SIZE) {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_NOHDP_CODE (BL2_NOHDP_CODE_START) FIXED (BL2_NOHDP_CODE_SIZE) {
+ *(.BL2_NoHdp_Code)
+ mpu_armv8m_drv.o (+RO)
+ }
+
+ ER_DATA (BL2_DATA_START) {
+ .ANY (+ZI +RW)
+ }
+
+ /* MSP */
+ ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE {
+ }
+
+ ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL2_HEAP_SIZE {
+ }
+ /* This empty, zero long execution region is here to mark the limit address
+ * of the last execution region that is allocated in SRAM.
+ */
+ SRAM_WATERMARK +0 EMPTY 0x0 {
+ }
+
+ /* Make sure that the sections allocated in the SRAM does not exceed the
+ * size of the SRAM available.
+ */
+ ScatterAssert(ImageLimit(SRAM_WATERMARK) <= BL2_DATA_START + BL2_DATA_SIZE)
+
+}
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_ns.sct b/platform/ext/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_ns.sct
new file mode 100644
index 0000000000..d38a305144
--- /dev/null
+++ b/platform/ext/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_ns.sct
@@ -0,0 +1,44 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "region_defs.h"
+
+LR_CODE NS_CODE_START {
+ ER_CODE NS_CODE_START NS_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_DATA_NO_INIT NS_DATA_START UNINIT NS_NO_INIT_DATA_SIZE {
+ *(.bss.NoInit)
+ }
+ ER_DATA (NS_DATA_START + NS_NO_INIT_DATA_SIZE) (NS_DATA_SIZE - NS_NO_INIT_DATA_SIZE) {
+ .ANY (+ZI +RW)
+ }
+ /* MSP */
+ ARM_LIB_STACK_MSP +0 ALIGN 32 EMPTY NS_MSP_STACK_SIZE {
+ }
+
+ /* PSP */
+ ARM_LIB_STACK +0 ALIGN 32 EMPTY NS_PSP_STACK_SIZE {
+ }
+
+ ARM_LIB_HEAP +0 ALIGN 8 EMPTY NS_HEAP_SIZE {
+ }
+}
+
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_bl2.S b/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_bl2.S
deleted file mode 100644
index 393bf92ba1..0000000000
--- a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_bl2.S
+++ /dev/null
@@ -1,430 +0,0 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.base
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
-
- /* Core interrupts */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long WWDG_IRQHandler /* Window WatchDog */
- .long PVD_PVM_IRQHandler /* PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */
- .long RTC_IRQHandler /* RTC non-secure interrupts through the EXTI line */
- .long RTC_IRQHandler_S /* RRTC secure interrupts through the EXTI line */
- .long TAMP_IRQHandler /* RTamper non-secure interrupts through the EXTI line */
- .long TAMP_IRQHandler_S /* RTamper secure interrupts through the EXTI line */
- .long FLASH_IRQHandler /* RFLASH non-secure interrupts */
- .long FLASH_IRQHandler_S /* RFLASH secure global interrupts */
- .long SERR_IRQHandler /* RSecure Error interrupts */
- .long RCC_IRQHandler /* RRCC non-secure global interrupts */
- .long RCC_IRQHandler_S /* RRCC secure global interrupts */
- .long EXTI0_IRQHandler /* REXTI Line0 */
- .long EXTI1_IRQHandler /* REXTI Line1 */
- .long EXTI2_IRQHandler /* REXTI Line2 */
- .long EXTI3_IRQHandler /* REXTI Line3 */
- .long EXTI4_IRQHandler /* REXTI Line4 */
- .long EXTI5_IRQHandler /* REXTI Line5 */
- .long EXTI6_IRQHandler /* REXTI Line6 */
- .long EXTI7_IRQHandler /* REXTI Line7 */
- .long EXTI8_IRQHandler /* REXTI Line8 */
- .long EXTI9_IRQHandler /* REXTI Line9 */
- .long EXTI10_IRQHandler /* EXTI Line10 */
- .long EXTI11_IRQHandler /* EXTI Line11 */
- .long EXTI12_IRQHandler /* EXTI Line12 */
- .long EXTI13_IRQHandler /* EXTI Line13 */
- .long EXTI14_IRQHandler /* EXTI Line14 */
- .long EXTI15_IRQHandler /* EXTI Line15 */
- .long DMAMUX1_IRQHandler /* DMAMUX1 non-secure */
- .long DMAMUX1_IRQHandler_S /* DMAMUX1 secure */
- .long DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
- .long DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
- .long DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
- .long DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
- .long DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
- .long DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
- .long DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
- .long DMA1_Channel8_IRQHandler /* DMA1 Channel 8 */
- .long ADC1_2_IRQHandler /* ADC1 & ADC2 */
- .long DAC_IRQHandler /* DAC1&2 underrun errors */
- .long FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
- .long FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
- .long TIM1_BRK_IRQHandler /* TIM1 Break */
- .long TIM1_UP_IRQHandler /* TIM1 Update */
- .long TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
- .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .long TIM2_IRQHandler /* TIM2 */
- .long TIM3_IRQHandler /* TIM3 */
- .long TIM4_IRQHandler /* TIM4 */
- .long TIM5_IRQHandler /* TIM5 */
- .long TIM6_IRQHandler /* TIM6 */
- .long TIM7_IRQHandler /* TIM7 */
- .long TIM8_BRK_IRQHandler /* TIM8 Break */
- .long TIM8_UP_IRQHandler /* TIM8 Update */
- .long TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
- .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .long I2C1_EV_IRQHandler /* I2C1 Event */
- .long I2C1_ER_IRQHandler /* I2C1 Error */
- .long I2C2_EV_IRQHandler /* I2C2 Event */
- .long I2C2_ER_IRQHandler /* I2C2 Error */
- .long SPI1_IRQHandler /* SPI1 */
- .long SPI2_IRQHandler /* SPI2 */
- .long USART1_IRQHandler /* USART1 */
- .long USART2_IRQHandler /* USART2 */
- .long USART3_IRQHandler /* USART3 */
- .long UART4_IRQHandler /* UART4 */
- .long UART5_IRQHandler /* UART5 */
- .long LPUART1_IRQHandler /* LP UART1 */
- .long LPTIM1_IRQHandler /* LP TIM1 */
- .long LPTIM2_IRQHandler /* LP TIM2 */
- .long TIM15_IRQHandler /* TIM15 */
- .long TIM16_IRQHandler /* TIM16 */
- .long TIM17_IRQHandler /* TIM17 */
- .long COMP_IRQHandler /* COMP1&2 */
- .long USB_FS_IRQHandler /* USB FS */
- .long CRS_IRQHandler /* CRS */
- .long FMC_IRQHandler /* FMC */
- .long OCTOSPI1_IRQHandler /* OctoSPI1 global interrupt */
- .long 0 /* Reserved */
- .long SDMMC1_IRQHandler /* SDMMC1 */
- .long 0 /* Reserved */
- .long DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
- .long DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
- .long DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
- .long DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
- .long DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
- .long DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
- .long DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
- .long DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
- .long I2C3_EV_IRQHandler /* I2C3 event */
- .long I2C3_ER_IRQHandler /* I2C3 error */
- .long SAI1_IRQHandler /* Serial Audio Interface 1 global interrupt */
- .long SAI2_IRQHandler /* Serial Audio Interface 2 global interrupt */
- .long TSC_IRQHandler /* Touch Sense Controller global interrupt */
- .long 0 /* Reserved */
- .long RNG_IRQHandler /* RNG global interrupt */
- .long FPU_IRQHandler /* FPU */
- .long HASH_IRQHandler /* HASH global interrupt */
- .long 0 /* Reserved */
- .long LPTIM3_IRQHandler /* LP TIM3 */
- .long SPI3_IRQHandler /* SPI3 */
- .long I2C4_ER_IRQHandler /* I2C4 error */
- .long I2C4_EV_IRQHandler /* I2C4 event */
- .long DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */
- .long DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */
- .long DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */
- .long DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */
- .long UCPD1_IRQHandler /* UCPD1 */
- .long ICACHE_IRQHandler /* ICACHE */
- .long OTFDEC1_IRQHandler /* OTFDEC1 */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- blt .L_loop0_0_done
- ldr r0, [r1, r3]
- str r0, [r2, r3]
- b .L_loop0_0
-
-.L_loop0_0_done:
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
- subs r3, r2
- ble .L_loop1_done
-
-.L_loop1:
- subs r3, #4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .L_loop1
-
-.L_loop1_done:
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- blt .L_loop2_0_done
- str r0, [r1, r2]
- b .L_loop2_0
-.L_loop2_0_done:
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-
- subs r2, r1
- ble .L_loop3_done
-
-.L_loop3:
- subs r2, #4
- str r0, [r1, r2]
- bgt .L_loop3
-.L_loop3_done:
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- bl SystemInit
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- /* Core interrupts */
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WWDG_IRQHandler
- def_irq_handler PVD_PVM_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler RTC_IRQHandler_S
- def_irq_handler TAMP_IRQHandler
- def_irq_handler TAMP_IRQHandler_S
- def_irq_handler FLASH_IRQHandler
- def_irq_handler FLASH_IRQHandler_S
- def_irq_handler SERR_IRQHandler
- def_irq_handler RCC_IRQHandler
- def_irq_handler RCC_IRQHandler_S
- def_irq_handler EXTI0_IRQHandler
- def_irq_handler EXTI1_IRQHandler
- def_irq_handler EXTI2_IRQHandler
- def_irq_handler EXTI3_IRQHandler
- def_irq_handler EXTI4_IRQHandler
- def_irq_handler EXTI5_IRQHandler
- def_irq_handler EXTI6_IRQHandler
- def_irq_handler EXTI7_IRQHandler
- def_irq_handler EXTI8_IRQHandler
- def_irq_handler EXTI9_IRQHandler
- def_irq_handler EXTI10_IRQHandler
- def_irq_handler EXTI11_IRQHandler
- def_irq_handler EXTI12_IRQHandler
- def_irq_handler EXTI13_IRQHandler
- def_irq_handler EXTI14_IRQHandler
- def_irq_handler EXTI15_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler_S
- def_irq_handler DMA1_Channel1_IRQHandler
- def_irq_handler DMA1_Channel2_IRQHandler
- def_irq_handler DMA1_Channel3_IRQHandler
- def_irq_handler DMA1_Channel4_IRQHandler
- def_irq_handler DMA1_Channel5_IRQHandler
- def_irq_handler DMA1_Channel6_IRQHandler
- def_irq_handler DMA1_Channel7_IRQHandler
- def_irq_handler DMA1_Channel8_IRQHandler
- def_irq_handler ADC1_2_IRQHandler
- def_irq_handler DAC_IRQHandler
- def_irq_handler FDCAN1_IT0_IRQHandler
- def_irq_handler FDCAN1_IT1_IRQHandler
- def_irq_handler TIM1_BRK_IRQHandler
- def_irq_handler TIM1_UP_IRQHandler
- def_irq_handler TIM1_TRG_COM_IRQHandler
- def_irq_handler TIM1_CC_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler TIM3_IRQHandler
- def_irq_handler TIM4_IRQHandler
- def_irq_handler TIM5_IRQHandler
- def_irq_handler TIM6_IRQHandler
- def_irq_handler TIM7_IRQHandler
- def_irq_handler TIM8_BRK_IRQHandler
- def_irq_handler TIM8_UP_IRQHandler
- def_irq_handler TIM8_TRG_COM_IRQHandler
- def_irq_handler TIM8_CC_IRQHandler
- def_irq_handler I2C1_EV_IRQHandler
- def_irq_handler I2C1_ER_IRQHandler
- def_irq_handler I2C2_EV_IRQHandler
- def_irq_handler I2C2_ER_IRQHandler
- def_irq_handler SPI1_IRQHandler
- def_irq_handler SPI2_IRQHandler
- def_irq_handler USART1_IRQHandler
- def_irq_handler USART2_IRQHandler
- def_irq_handler USART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler UART5_IRQHandler
- def_irq_handler LPUART1_IRQHandler
- def_irq_handler LPTIM1_IRQHandler
- def_irq_handler LPTIM2_IRQHandler
- def_irq_handler TIM15_IRQHandler
- def_irq_handler TIM16_IRQHandler
- def_irq_handler TIM17_IRQHandler
- def_irq_handler COMP_IRQHandler
- def_irq_handler USB_FS_IRQHandler
- def_irq_handler CRS_IRQHandler
- def_irq_handler FMC_IRQHandler
- def_irq_handler OCTOSPI1_IRQHandler
- def_irq_handler SDMMC1_IRQHandler
- def_irq_handler DMA2_Channel1_IRQHandler
- def_irq_handler DMA2_Channel2_IRQHandler
- def_irq_handler DMA2_Channel3_IRQHandler
- def_irq_handler DMA2_Channel4_IRQHandler
- def_irq_handler DMA2_Channel5_IRQHandler
- def_irq_handler DMA2_Channel6_IRQHandler
- def_irq_handler DMA2_Channel7_IRQHandler
- def_irq_handler DMA2_Channel8_IRQHandler
- def_irq_handler I2C3_EV_IRQHandler
- def_irq_handler I2C3_ER_IRQHandler
- def_irq_handler SAI1_IRQHandler
- def_irq_handler SAI2_IRQHandler
- def_irq_handler TSC_IRQHandler
- def_irq_handler RNG_IRQHandler
- def_irq_handler FPU_IRQHandler
- def_irq_handler HASH_IRQHandler
- def_irq_handler LPTIM3_IRQHandler
- def_irq_handler SPI3_IRQHandler
- def_irq_handler I2C4_ER_IRQHandler
- def_irq_handler I2C4_EV_IRQHandler
- def_irq_handler DFSDM1_FLT0_IRQHandler
- def_irq_handler DFSDM1_FLT1_IRQHandler
- def_irq_handler DFSDM1_FLT2_IRQHandler
- def_irq_handler DFSDM1_FLT3_IRQHandler
- def_irq_handler UCPD1_IRQHandler
- def_irq_handler ICACHE_IRQHandler
- def_irq_handler OTFDEC1_IRQHandler
-
- .end
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_ns.S b/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_ns.S
deleted file mode 100644
index 0911fbf676..0000000000
--- a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_ns.S
+++ /dev/null
@@ -1,417 +0,0 @@
-;/*
-; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long WWDG_IRQHandler /* Window WatchDog */
- .long PVD_PVM_IRQHandler /* PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */
- .long RTC_IRQHandler /* RTC non-secure interrupts through the EXTI line */
- .long RTC_IRQHandler_S /* RRTC secure interrupts through the EXTI line */
- .long TAMP_IRQHandler /* RTamper non-secure interrupts through the EXTI line */
- .long TAMP_IRQHandler_S /* RTamper secure interrupts through the EXTI line */
- .long FLASH_IRQHandler /* RFLASH non-secure interrupts */
- .long FLASH_IRQHandler_S /* RFLASH secure global interrupts */
- .long SERR_IRQHandler /* RSecure Error interrupts */
- .long RCC_IRQHandler /* RRCC non-secure global interrupts */
- .long RCC_IRQHandler_S /* RRCC secure global interrupts */
- .long EXTI0_IRQHandler /* REXTI Line0 */
- .long EXTI1_IRQHandler /* REXTI Line1 */
- .long EXTI2_IRQHandler /* REXTI Line2 */
- .long EXTI3_IRQHandler /* REXTI Line3 */
- .long EXTI4_IRQHandler /* REXTI Line4 */
- .long EXTI5_IRQHandler /* REXTI Line5 */
- .long EXTI6_IRQHandler /* REXTI Line6 */
- .long EXTI7_IRQHandler /* REXTI Line7 */
- .long EXTI8_IRQHandler /* REXTI Line8 */
- .long EXTI9_IRQHandler /* REXTI Line9 */
- .long EXTI10_IRQHandler /* EXTI Line10 */
- .long EXTI11_IRQHandler /* EXTI Line11 */
- .long EXTI12_IRQHandler /* EXTI Line12 */
- .long EXTI13_IRQHandler /* EXTI Line13 */
- .long EXTI14_IRQHandler /* EXTI Line14 */
- .long EXTI15_IRQHandler /* EXTI Line15 */
- .long DMAMUX1_IRQHandler /* DMAMUX1 non-secure */
- .long DMAMUX1_IRQHandler_S /* DMAMUX1 secure */
- .long DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
- .long DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
- .long DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
- .long DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
- .long DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
- .long DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
- .long DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
- .long DMA1_Channel8_IRQHandler /* DMA1 Channel 8 */
- .long ADC1_2_IRQHandler /* ADC1 & ADC2 */
- .long DAC_IRQHandler /* DAC1&2 underrun errors */
- .long FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
- .long FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
- .long TIM1_BRK_IRQHandler /* TIM1 Break */
- .long TIM1_UP_IRQHandler /* TIM1 Update */
- .long TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
- .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .long TIM2_IRQHandler /* TIM2 */
- .long TIM3_IRQHandler /* TIM3 */
- .long TIM4_IRQHandler /* TIM4 */
- .long TIM5_IRQHandler /* TIM5 */
- .long TIM6_IRQHandler /* TIM6 */
- .long TIM7_IRQHandler /* TIM7 */
- .long TIM8_BRK_IRQHandler /* TIM8 Break */
- .long TIM8_UP_IRQHandler /* TIM8 Update */
- .long TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
- .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .long I2C1_EV_IRQHandler /* I2C1 Event */
- .long I2C1_ER_IRQHandler /* I2C1 Error */
- .long I2C2_EV_IRQHandler /* I2C2 Event */
- .long I2C2_ER_IRQHandler /* I2C2 Error */
- .long SPI1_IRQHandler /* SPI1 */
- .long SPI2_IRQHandler /* SPI2 */
- .long USART1_IRQHandler /* USART1 */
- .long USART2_IRQHandler /* USART2 */
- .long USART3_IRQHandler /* USART3 */
- .long UART4_IRQHandler /* UART4 */
- .long UART5_IRQHandler /* UART5 */
- .long LPUART1_IRQHandler /* LP UART1 */
- .long LPTIM1_IRQHandler /* LP TIM1 */
- .long LPTIM2_IRQHandler /* LP TIM2 */
- .long TIM15_IRQHandler /* TIM15 */
- .long TIM16_IRQHandler /* TIM16 */
- .long TIM17_IRQHandler /* TIM17 */
- .long COMP_IRQHandler /* COMP1&2 */
- .long USB_FS_IRQHandler /* USB FS */
- .long CRS_IRQHandler /* CRS */
- .long FMC_IRQHandler /* FMC */
- .long OCTOSPI1_IRQHandler /* OctoSPI1 global interrupt */
- .long 0 /* Reserved */
- .long SDMMC1_IRQHandler /* SDMMC1 */
- .long 0 /* Reserved */
- .long DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
- .long DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
- .long DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
- .long DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
- .long DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
- .long DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
- .long DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
- .long DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
- .long I2C3_EV_IRQHandler /* I2C3 event */
- .long I2C3_ER_IRQHandler /* I2C3 error */
- .long SAI1_IRQHandler /* Serial Audio Interface 1 global interrupt */
- .long SAI2_IRQHandler /* Serial Audio Interface 2 global interrupt */
- .long TSC_IRQHandler /* Touch Sense Controller global interrupt */
- .long 0 /* Reserved */
- .long RNG_IRQHandler /* RNG global interrupt */
- .long FPU_IRQHandler /* FPU */
- .long HASH_IRQHandler /* HASH global interrupt */
- .long 0 /* Reserved */
- .long LPTIM3_IRQHandler /* LP TIM3 */
- .long SPI3_IRQHandler /* SPI3 */
- .long I2C4_ER_IRQHandler /* I2C4 error */
- .long I2C4_EV_IRQHandler /* I2C4 event */
- .long DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */
- .long DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */
- .long DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */
- .long DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */
- .long UCPD1_IRQHandler /* UCPD1 */
- .long ICACHE_IRQHandler /* ICACHE */
- .long OTFDEC1_IRQHandler /* OTFDEC1 */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- bl SystemInit
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WWDG_IRQHandler
- def_irq_handler PVD_PVM_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler RTC_IRQHandler_S
- def_irq_handler TAMP_IRQHandler
- def_irq_handler TAMP_IRQHandler_S
- def_irq_handler FLASH_IRQHandler
- def_irq_handler FLASH_IRQHandler_S
- def_irq_handler SERR_IRQHandler
- def_irq_handler RCC_IRQHandler
- def_irq_handler RCC_IRQHandler_S
- def_irq_handler EXTI0_IRQHandler
- def_irq_handler EXTI1_IRQHandler
- def_irq_handler EXTI2_IRQHandler
- def_irq_handler EXTI3_IRQHandler
- def_irq_handler EXTI4_IRQHandler
- def_irq_handler EXTI5_IRQHandler
- def_irq_handler EXTI6_IRQHandler
- def_irq_handler EXTI7_IRQHandler
- def_irq_handler EXTI8_IRQHandler
- def_irq_handler EXTI9_IRQHandler
- def_irq_handler EXTI10_IRQHandler
- def_irq_handler EXTI11_IRQHandler
- def_irq_handler EXTI12_IRQHandler
- def_irq_handler EXTI13_IRQHandler
- def_irq_handler EXTI14_IRQHandler
- def_irq_handler EXTI15_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler_S
- def_irq_handler DMA1_Channel1_IRQHandler
- def_irq_handler DMA1_Channel2_IRQHandler
- def_irq_handler DMA1_Channel3_IRQHandler
- def_irq_handler DMA1_Channel4_IRQHandler
- def_irq_handler DMA1_Channel5_IRQHandler
- def_irq_handler DMA1_Channel6_IRQHandler
- def_irq_handler DMA1_Channel7_IRQHandler
- def_irq_handler DMA1_Channel8_IRQHandler
- def_irq_handler ADC1_2_IRQHandler
- def_irq_handler DAC_IRQHandler
- def_irq_handler FDCAN1_IT0_IRQHandler
- def_irq_handler FDCAN1_IT1_IRQHandler
- def_irq_handler TIM1_BRK_IRQHandler
- def_irq_handler TIM1_UP_IRQHandler
- def_irq_handler TIM1_TRG_COM_IRQHandler
- def_irq_handler TIM1_CC_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler TIM3_IRQHandler
- def_irq_handler TIM4_IRQHandler
- def_irq_handler TIM5_IRQHandler
- def_irq_handler TIM6_IRQHandler
- def_irq_handler TIM7_IRQHandler
- def_irq_handler TIM8_BRK_IRQHandler
- def_irq_handler TIM8_UP_IRQHandler
- def_irq_handler TIM8_TRG_COM_IRQHandler
- def_irq_handler TIM8_CC_IRQHandler
- def_irq_handler I2C1_EV_IRQHandler
- def_irq_handler I2C1_ER_IRQHandler
- def_irq_handler I2C2_EV_IRQHandler
- def_irq_handler I2C2_ER_IRQHandler
- def_irq_handler SPI1_IRQHandler
- def_irq_handler SPI2_IRQHandler
- def_irq_handler USART1_IRQHandler
- def_irq_handler USART2_IRQHandler
- def_irq_handler USART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler UART5_IRQHandler
- def_irq_handler LPUART1_IRQHandler
- def_irq_handler LPTIM1_IRQHandler
- def_irq_handler LPTIM2_IRQHandler
- def_irq_handler TIM15_IRQHandler
- def_irq_handler TIM16_IRQHandler
- def_irq_handler TIM17_IRQHandler
- def_irq_handler COMP_IRQHandler
- def_irq_handler USB_FS_IRQHandler
- def_irq_handler CRS_IRQHandler
- def_irq_handler FMC_IRQHandler
- def_irq_handler OCTOSPI1_IRQHandler
- def_irq_handler SDMMC1_IRQHandler
- def_irq_handler DMA2_Channel1_IRQHandler
- def_irq_handler DMA2_Channel2_IRQHandler
- def_irq_handler DMA2_Channel3_IRQHandler
- def_irq_handler DMA2_Channel4_IRQHandler
- def_irq_handler DMA2_Channel5_IRQHandler
- def_irq_handler DMA2_Channel6_IRQHandler
- def_irq_handler DMA2_Channel7_IRQHandler
- def_irq_handler DMA2_Channel8_IRQHandler
- def_irq_handler I2C3_EV_IRQHandler
- def_irq_handler I2C3_ER_IRQHandler
- def_irq_handler SAI1_IRQHandler
- def_irq_handler SAI2_IRQHandler
- def_irq_handler TSC_IRQHandler
- def_irq_handler AES_IRQHandler
- def_irq_handler RNG_IRQHandler
- def_irq_handler FPU_IRQHandler
- def_irq_handler HASH_IRQHandler
- def_irq_handler LPTIM3_IRQHandler
- def_irq_handler SPI3_IRQHandler
- def_irq_handler I2C4_ER_IRQHandler
- def_irq_handler I2C4_EV_IRQHandler
- def_irq_handler DFSDM1_FLT0_IRQHandler
- def_irq_handler DFSDM1_FLT1_IRQHandler
- def_irq_handler DFSDM1_FLT2_IRQHandler
- def_irq_handler DFSDM1_FLT3_IRQHandler
- def_irq_handler UCPD1_IRQHandler
- def_irq_handler ICACHE_IRQHandler
- def_irq_handler OTFDEC1_IRQHandler
-
- .end
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_s.S b/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_s.S
deleted file mode 100644
index 60a857e2f5..0000000000
--- a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_s.S
+++ /dev/null
@@ -1,426 +0,0 @@
-;/*
-; * Copyright (c) 2009-2019 Arm Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
-/* Core interrupts */
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long WWDG_IRQHandler /* Window WatchDog */
- .long PVD_PVM_IRQHandler /* PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */
- .long RTC_IRQHandler /* RTC non-secure interrupts through the EXTI line */
- .long RTC_IRQHandler_S /* RRTC secure interrupts through the EXTI line */
- .long TAMP_IRQHandler /* RTamper non-secure interrupts through the EXTI line */
- .long TAMP_IRQHandler_S /* RTamper secure interrupts through the EXTI line */
- .long FLASH_IRQHandler /* RFLASH non-secure interrupts */
- .long FLASH_IRQHandler_S /* RFLASH secure global interrupts */
- .long SERR_IRQHandler /* RSecure Error interrupts */
- .long RCC_IRQHandler /* RRCC non-secure global interrupts */
- .long RCC_IRQHandler_S /* RRCC secure global interrupts */
- .long EXTI0_IRQHandler /* REXTI Line0 */
- .long EXTI1_IRQHandler /* REXTI Line1 */
- .long EXTI2_IRQHandler /* REXTI Line2 */
- .long EXTI3_IRQHandler /* REXTI Line3 */
- .long EXTI4_IRQHandler /* REXTI Line4 */
- .long EXTI5_IRQHandler /* REXTI Line5 */
- .long EXTI6_IRQHandler /* REXTI Line6 */
- .long EXTI7_IRQHandler /* REXTI Line7 */
- .long EXTI8_IRQHandler /* REXTI Line8 */
- .long EXTI9_IRQHandler /* REXTI Line9 */
- .long EXTI10_IRQHandler /* EXTI Line10 */
- .long EXTI11_IRQHandler /* EXTI Line11 */
- .long EXTI12_IRQHandler /* EXTI Line12 */
- .long EXTI13_IRQHandler /* EXTI Line13 */
- .long EXTI14_IRQHandler /* EXTI Line14 */
- .long EXTI15_IRQHandler /* EXTI Line15 */
- .long DMAMUX1_IRQHandler /* DMAMUX1 non-secure */
- .long DMAMUX1_IRQHandler_S /* DMAMUX1 secure */
- .long DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
- .long DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
- .long DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
- .long DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
- .long DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
- .long DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
- .long DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
- .long DMA1_Channel8_IRQHandler /* DMA1 Channel 8 */
- .long ADC1_2_IRQHandler /* ADC1 & ADC2 */
- .long DAC_IRQHandler /* DAC1&2 underrun errors */
- .long FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
- .long FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
- .long TIM1_BRK_IRQHandler /* TIM1 Break */
- .long TIM1_UP_IRQHandler /* TIM1 Update */
- .long TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
- .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .long TIM2_IRQHandler /* TIM2 */
- .long TIM3_IRQHandler /* TIM3 */
- .long TIM4_IRQHandler /* TIM4 */
- .long TIM5_IRQHandler /* TIM5 */
- .long TIM6_IRQHandler /* TIM6 */
- .long TIM7_IRQHandler /* TIM7 */
- .long TIM8_BRK_IRQHandler /* TIM8 Break */
- .long TIM8_UP_IRQHandler /* TIM8 Update */
- .long TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
- .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .long I2C1_EV_IRQHandler /* I2C1 Event */
- .long I2C1_ER_IRQHandler /* I2C1 Error */
- .long I2C2_EV_IRQHandler /* I2C2 Event */
- .long I2C2_ER_IRQHandler /* I2C2 Error */
- .long SPI1_IRQHandler /* SPI1 */
- .long SPI2_IRQHandler /* SPI2 */
- .long USART1_IRQHandler /* USART1 */
- .long USART2_IRQHandler /* USART2 */
- .long USART3_IRQHandler /* USART3 */
- .long UART4_IRQHandler /* UART4 */
- .long UART5_IRQHandler /* UART5 */
- .long LPUART1_IRQHandler /* LP UART1 */
- .long LPTIM1_IRQHandler /* LP TIM1 */
- .long LPTIM2_IRQHandler /* LP TIM2 */
- .long TIM15_IRQHandler /* TIM15 */
- .long TIM16_IRQHandler /* TIM16 */
- .long TIM17_IRQHandler /* TIM17 */
- .long COMP_IRQHandler /* COMP1&2 */
- .long USB_FS_IRQHandler /* USB FS */
- .long CRS_IRQHandler /* CRS */
- .long FMC_IRQHandler /* FMC */
- .long OCTOSPI1_IRQHandler /* OctoSPI1 global interrupt */
- .long 0 /* Reserved */
- .long SDMMC1_IRQHandler /* SDMMC1 */
- .long 0 /* Reserved */
- .long DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
- .long DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
- .long DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
- .long DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
- .long DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
- .long DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
- .long DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
- .long DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
- .long I2C3_EV_IRQHandler /* I2C3 event */
- .long I2C3_ER_IRQHandler /* I2C3 error */
- .long SAI1_IRQHandler /* Serial Audio Interface 1 global interrupt */
- .long SAI2_IRQHandler /* Serial Audio Interface 2 global interrupt */
- .long TSC_IRQHandler /* Touch Sense Controller global interrupt */
- .long 0 /* Reserved */
- .long RNG_IRQHandler /* RNG global interrupt */
- .long FPU_IRQHandler /* FPU */
- .long HASH_IRQHandler /* HASH global interrupt */
- .long 0 /* Reserved */
- .long LPTIM3_IRQHandler /* LP TIM3 */
- .long SPI3_IRQHandler /* SPI3 */
- .long I2C4_ER_IRQHandler /* I2C4 error */
- .long I2C4_EV_IRQHandler /* I2C4 event */
- .long DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */
- .long DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */
- .long DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */
- .long DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */
- .long UCPD1_IRQHandler /* UCPD1 */
- .long ICACHE_IRQHandler /* ICACHE */
- .long OTFDEC1_IRQHandler /* OTFDEC1 */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- cpsid i /* Disable IRQs */
- bl SystemInit
-
- mrs r0, control /* Get control value */
- orr r0, r0, #2 /* Select switch to PSP */
- msr control, r0
- ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
- msr psp, r0
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WWDG_IRQHandler
- def_irq_handler PVD_PVM_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler RTC_IRQHandler_S
- def_irq_handler TAMP_IRQHandler
- def_irq_handler TAMP_IRQHandler_S
- def_irq_handler FLASH_IRQHandler
- def_irq_handler FLASH_IRQHandler_S
- def_irq_handler SERR_IRQHandler
- def_irq_handler RCC_IRQHandler
- def_irq_handler RCC_IRQHandler_S
- def_irq_handler EXTI0_IRQHandler
- def_irq_handler EXTI1_IRQHandler
- def_irq_handler EXTI2_IRQHandler
- def_irq_handler EXTI3_IRQHandler
- def_irq_handler EXTI4_IRQHandler
- def_irq_handler EXTI5_IRQHandler
- def_irq_handler EXTI6_IRQHandler
- def_irq_handler EXTI7_IRQHandler
- def_irq_handler EXTI8_IRQHandler
- def_irq_handler EXTI9_IRQHandler
- def_irq_handler EXTI10_IRQHandler
- def_irq_handler EXTI11_IRQHandler
- def_irq_handler EXTI12_IRQHandler
- def_irq_handler EXTI13_IRQHandler
- def_irq_handler EXTI14_IRQHandler
- def_irq_handler EXTI15_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler_S
- def_irq_handler DMA1_Channel1_IRQHandler
- def_irq_handler DMA1_Channel2_IRQHandler
- def_irq_handler DMA1_Channel3_IRQHandler
- def_irq_handler DMA1_Channel4_IRQHandler
- def_irq_handler DMA1_Channel5_IRQHandler
- def_irq_handler DMA1_Channel6_IRQHandler
- def_irq_handler DMA1_Channel7_IRQHandler
- def_irq_handler DMA1_Channel8_IRQHandler
- def_irq_handler ADC1_2_IRQHandler
- def_irq_handler DAC_IRQHandler
- def_irq_handler FDCAN1_IT0_IRQHandler
- def_irq_handler FDCAN1_IT1_IRQHandler
- def_irq_handler TIM1_BRK_IRQHandler
- def_irq_handler TIM1_UP_IRQHandler
- def_irq_handler TIM1_TRG_COM_IRQHandler
- def_irq_handler TIM1_CC_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler TIM3_IRQHandler
- def_irq_handler TIM4_IRQHandler
- def_irq_handler TIM5_IRQHandler
- def_irq_handler TIM6_IRQHandler
- def_irq_handler TIM7_IRQHandler
- def_irq_handler TIM8_BRK_IRQHandler
- def_irq_handler TIM8_UP_IRQHandler
- def_irq_handler TIM8_TRG_COM_IRQHandler
- def_irq_handler TIM8_CC_IRQHandler
- def_irq_handler I2C1_EV_IRQHandler
- def_irq_handler I2C1_ER_IRQHandler
- def_irq_handler I2C2_EV_IRQHandler
- def_irq_handler I2C2_ER_IRQHandler
- def_irq_handler SPI1_IRQHandler
- def_irq_handler SPI2_IRQHandler
- def_irq_handler USART1_IRQHandler
- def_irq_handler USART2_IRQHandler
- def_irq_handler USART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler UART5_IRQHandler
- def_irq_handler LPUART1_IRQHandler
- def_irq_handler LPTIM1_IRQHandler
- def_irq_handler LPTIM2_IRQHandler
- def_irq_handler TIM15_IRQHandler
- def_irq_handler TIM16_IRQHandler
- def_irq_handler TIM17_IRQHandler
- def_irq_handler COMP_IRQHandler
- def_irq_handler USB_FS_IRQHandler
- def_irq_handler CRS_IRQHandler
- def_irq_handler FMC_IRQHandler
- def_irq_handler OCTOSPI1_IRQHandler
- def_irq_handler SDMMC1_IRQHandler
- def_irq_handler DMA2_Channel1_IRQHandler
- def_irq_handler DMA2_Channel2_IRQHandler
- def_irq_handler DMA2_Channel3_IRQHandler
- def_irq_handler DMA2_Channel4_IRQHandler
- def_irq_handler DMA2_Channel5_IRQHandler
- def_irq_handler DMA2_Channel6_IRQHandler
- def_irq_handler DMA2_Channel7_IRQHandler
- def_irq_handler DMA2_Channel8_IRQHandler
- def_irq_handler I2C3_EV_IRQHandler
- def_irq_handler I2C3_ER_IRQHandler
- def_irq_handler SAI1_IRQHandler
- def_irq_handler SAI2_IRQHandler
- def_irq_handler TSC_IRQHandler
- def_irq_handler AES_IRQHandler
- def_irq_handler RNG_IRQHandler
- def_irq_handler FPU_IRQHandler
- def_irq_handler HASH_IRQHandler
- def_irq_handler LPTIM3_IRQHandler
- def_irq_handler SPI3_IRQHandler
- def_irq_handler I2C4_ER_IRQHandler
- def_irq_handler I2C4_EV_IRQHandler
- def_irq_handler DFSDM1_FLT0_IRQHandler
- def_irq_handler DFSDM1_FLT1_IRQHandler
- def_irq_handler DFSDM1_FLT2_IRQHandler
- def_irq_handler DFSDM1_FLT3_IRQHandler
- def_irq_handler UCPD1_IRQHandler
- def_irq_handler ICACHE_IRQHandler
- def_irq_handler OTFDEC1_IRQHandler
-
- .end
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_bl2.S b/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_bl2.S
deleted file mode 100644
index 01c591560b..0000000000
--- a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_bl2.S
+++ /dev/null
@@ -1,431 +0,0 @@
-;/*
-; * Copyright (c) 2009-2018 ARM Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.base
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
-
- /* Core interrupts */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long WWDG_IRQHandler /* Window WatchDog */
- .long PVD_PVM_IRQHandler /* PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */
- .long RTC_IRQHandler /* RTC non-secure interrupts through the EXTI line */
- .long RTC_IRQHandler_S /* RRTC secure interrupts through the EXTI line */
- .long TAMP_IRQHandler /* RTamper non-secure interrupts through the EXTI line */
- .long TAMP_IRQHandler_S /* RTamper secure interrupts through the EXTI line */
- .long FLASH_IRQHandler /* RFLASH non-secure interrupts */
- .long FLASH_IRQHandler_S /* RFLASH secure global interrupts */
- .long SERR_IRQHandler /* RSecure Error interrupts */
- .long RCC_IRQHandler /* RRCC non-secure global interrupts */
- .long RCC_IRQHandler_S /* RRCC secure global interrupts */
- .long EXTI0_IRQHandler /* REXTI Line0 */
- .long EXTI1_IRQHandler /* REXTI Line1 */
- .long EXTI2_IRQHandler /* REXTI Line2 */
- .long EXTI3_IRQHandler /* REXTI Line3 */
- .long EXTI4_IRQHandler /* REXTI Line4 */
- .long EXTI5_IRQHandler /* REXTI Line5 */
- .long EXTI6_IRQHandler /* REXTI Line6 */
- .long EXTI7_IRQHandler /* REXTI Line7 */
- .long EXTI8_IRQHandler /* REXTI Line8 */
- .long EXTI9_IRQHandler /* REXTI Line9 */
- .long EXTI10_IRQHandler /* EXTI Line10 */
- .long EXTI11_IRQHandler /* EXTI Line11 */
- .long EXTI12_IRQHandler /* EXTI Line12 */
- .long EXTI13_IRQHandler /* EXTI Line13 */
- .long EXTI14_IRQHandler /* EXTI Line14 */
- .long EXTI15_IRQHandler /* EXTI Line15 */
- .long DMAMUX1_IRQHandler /* DMAMUX1 non-secure */
- .long DMAMUX1_IRQHandler_S /* DMAMUX1 secure */
- .long DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
- .long DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
- .long DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
- .long DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
- .long DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
- .long DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
- .long DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
- .long DMA1_Channel8_IRQHandler /* DMA1 Channel 8 */
- .long ADC1_2_IRQHandler /* ADC1 & ADC2 */
- .long DAC_IRQHandler /* DAC1&2 underrun errors */
- .long FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
- .long FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
- .long TIM1_BRK_IRQHandler /* TIM1 Break */
- .long TIM1_UP_IRQHandler /* TIM1 Update */
- .long TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
- .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .long TIM2_IRQHandler /* TIM2 */
- .long TIM3_IRQHandler /* TIM3 */
- .long TIM4_IRQHandler /* TIM4 */
- .long TIM5_IRQHandler /* TIM5 */
- .long TIM6_IRQHandler /* TIM6 */
- .long TIM7_IRQHandler /* TIM7 */
- .long TIM8_BRK_IRQHandler /* TIM8 Break */
- .long TIM8_UP_IRQHandler /* TIM8 Update */
- .long TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
- .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .long I2C1_EV_IRQHandler /* I2C1 Event */
- .long I2C1_ER_IRQHandler /* I2C1 Error */
- .long I2C2_EV_IRQHandler /* I2C2 Event */
- .long I2C2_ER_IRQHandler /* I2C2 Error */
- .long SPI1_IRQHandler /* SPI1 */
- .long SPI2_IRQHandler /* SPI2 */
- .long USART1_IRQHandler /* USART1 */
- .long USART2_IRQHandler /* USART2 */
- .long USART3_IRQHandler /* USART3 */
- .long UART4_IRQHandler /* UART4 */
- .long UART5_IRQHandler /* UART5 */
- .long LPUART1_IRQHandler /* LP UART1 */
- .long LPTIM1_IRQHandler /* LP TIM1 */
- .long LPTIM2_IRQHandler /* LP TIM2 */
- .long TIM15_IRQHandler /* TIM15 */
- .long TIM16_IRQHandler /* TIM16 */
- .long TIM17_IRQHandler /* TIM17 */
- .long COMP_IRQHandler /* COMP1&2 */
- .long USB_FS_IRQHandler /* USB FS */
- .long CRS_IRQHandler /* CRS */
- .long FMC_IRQHandler /* FMC */
- .long OCTOSPI1_IRQHandler /* OctoSPI1 global interrupt */
- .long 0 /* Reserved */
- .long SDMMC1_IRQHandler /* SDMMC1 */
- .long 0 /* Reserved */
- .long DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
- .long DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
- .long DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
- .long DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
- .long DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
- .long DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
- .long DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
- .long DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
- .long I2C3_EV_IRQHandler /* I2C3 event */
- .long I2C3_ER_IRQHandler /* I2C3 error */
- .long SAI1_IRQHandler /* Serial Audio Interface 1 global interrupt */
- .long SAI2_IRQHandler /* Serial Audio Interface 2 global interrupt */
- .long TSC_IRQHandler /* Touch Sense Controller global interrupt */
- .long AES_IRQHandler /* AES global interrupt */
- .long RNG_IRQHandler /* RNG global interrupt */
- .long FPU_IRQHandler /* FPU */
- .long HASH_IRQHandler /* HASH global interrupt */
- .long PKA_IRQHandler /* PKA global interrupt */
- .long LPTIM3_IRQHandler /* LP TIM3 */
- .long SPI3_IRQHandler /* SPI3 */
- .long I2C4_ER_IRQHandler /* I2C4 error */
- .long I2C4_EV_IRQHandler /* I2C4 event */
- .long DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */
- .long DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */
- .long DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */
- .long DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */
- .long UCPD1_IRQHandler /* UCPD1 */
- .long ICACHE_IRQHandler /* ICACHE */
- .long OTFDEC1_IRQHandler /* OTFDEC1 */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- blt .L_loop0_0_done
- ldr r0, [r1, r3]
- str r0, [r2, r3]
- b .L_loop0_0
-
-.L_loop0_0_done:
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
- subs r3, r2
- ble .L_loop1_done
-
-.L_loop1:
- subs r3, #4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .L_loop1
-
-.L_loop1_done:
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- blt .L_loop2_0_done
- str r0, [r1, r2]
- b .L_loop2_0
-.L_loop2_0_done:
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-
- subs r2, r1
- ble .L_loop3_done
-
-.L_loop3:
- subs r2, #4
- str r0, [r1, r2]
- bgt .L_loop3
-.L_loop3_done:
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- bl SystemInit
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WWDG_IRQHandler
- def_irq_handler PVD_PVM_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler RTC_IRQHandler_S
- def_irq_handler TAMP_IRQHandler
- def_irq_handler TAMP_IRQHandler_S
- def_irq_handler FLASH_IRQHandler
- def_irq_handler FLASH_IRQHandler_S
- def_irq_handler SERR_IRQHandler
- def_irq_handler RCC_IRQHandler
- def_irq_handler RCC_IRQHandler_S
- def_irq_handler EXTI0_IRQHandler
- def_irq_handler EXTI1_IRQHandler
- def_irq_handler EXTI2_IRQHandler
- def_irq_handler EXTI3_IRQHandler
- def_irq_handler EXTI4_IRQHandler
- def_irq_handler EXTI5_IRQHandler
- def_irq_handler EXTI6_IRQHandler
- def_irq_handler EXTI7_IRQHandler
- def_irq_handler EXTI8_IRQHandler
- def_irq_handler EXTI9_IRQHandler
- def_irq_handler EXTI10_IRQHandler
- def_irq_handler EXTI11_IRQHandler
- def_irq_handler EXTI12_IRQHandler
- def_irq_handler EXTI13_IRQHandler
- def_irq_handler EXTI14_IRQHandler
- def_irq_handler EXTI15_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler_S
- def_irq_handler DMA1_Channel1_IRQHandler
- def_irq_handler DMA1_Channel2_IRQHandler
- def_irq_handler DMA1_Channel3_IRQHandler
- def_irq_handler DMA1_Channel4_IRQHandler
- def_irq_handler DMA1_Channel5_IRQHandler
- def_irq_handler DMA1_Channel6_IRQHandler
- def_irq_handler DMA1_Channel7_IRQHandler
- def_irq_handler DMA1_Channel8_IRQHandler
- def_irq_handler ADC1_2_IRQHandler
- def_irq_handler DAC_IRQHandler
- def_irq_handler FDCAN1_IT0_IRQHandler
- def_irq_handler FDCAN1_IT1_IRQHandler
- def_irq_handler TIM1_BRK_IRQHandler
- def_irq_handler TIM1_UP_IRQHandler
- def_irq_handler TIM1_TRG_COM_IRQHandler
- def_irq_handler TIM1_CC_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler TIM3_IRQHandler
- def_irq_handler TIM4_IRQHandler
- def_irq_handler TIM5_IRQHandler
- def_irq_handler TIM6_IRQHandler
- def_irq_handler TIM7_IRQHandler
- def_irq_handler TIM8_BRK_IRQHandler
- def_irq_handler TIM8_UP_IRQHandler
- def_irq_handler TIM8_TRG_COM_IRQHandler
- def_irq_handler TIM8_CC_IRQHandler
- def_irq_handler I2C1_EV_IRQHandler
- def_irq_handler I2C1_ER_IRQHandler
- def_irq_handler I2C2_EV_IRQHandler
- def_irq_handler I2C2_ER_IRQHandler
- def_irq_handler SPI1_IRQHandler
- def_irq_handler SPI2_IRQHandler
- def_irq_handler USART1_IRQHandler
- def_irq_handler USART2_IRQHandler
- def_irq_handler USART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler UART5_IRQHandler
- def_irq_handler LPUART1_IRQHandler
- def_irq_handler LPTIM1_IRQHandler
- def_irq_handler LPTIM2_IRQHandler
- def_irq_handler TIM15_IRQHandler
- def_irq_handler TIM16_IRQHandler
- def_irq_handler TIM17_IRQHandler
- def_irq_handler COMP_IRQHandler
- def_irq_handler USB_FS_IRQHandler
- def_irq_handler CRS_IRQHandler
- def_irq_handler FMC_IRQHandler
- def_irq_handler OCTOSPI1_IRQHandler
- def_irq_handler SDMMC1_IRQHandler
- def_irq_handler DMA2_Channel1_IRQHandler
- def_irq_handler DMA2_Channel2_IRQHandler
- def_irq_handler DMA2_Channel3_IRQHandler
- def_irq_handler DMA2_Channel4_IRQHandler
- def_irq_handler DMA2_Channel5_IRQHandler
- def_irq_handler DMA2_Channel6_IRQHandler
- def_irq_handler DMA2_Channel7_IRQHandler
- def_irq_handler DMA2_Channel8_IRQHandler
- def_irq_handler I2C3_EV_IRQHandler
- def_irq_handler I2C3_ER_IRQHandler
- def_irq_handler SAI1_IRQHandler
- def_irq_handler SAI2_IRQHandler
- def_irq_handler TSC_IRQHandler
- def_irq_handler AES_IRQHandler
- def_irq_handler RNG_IRQHandler
- def_irq_handler FPU_IRQHandler
- def_irq_handler HASH_IRQHandler
- def_irq_handler PKA_IRQHandler
- def_irq_handler LPTIM3_IRQHandler
- def_irq_handler SPI3_IRQHandler
- def_irq_handler I2C4_ER_IRQHandler
- def_irq_handler I2C4_EV_IRQHandler
- def_irq_handler DFSDM1_FLT0_IRQHandler
- def_irq_handler DFSDM1_FLT1_IRQHandler
- def_irq_handler DFSDM1_FLT2_IRQHandler
- def_irq_handler DFSDM1_FLT3_IRQHandler
- def_irq_handler UCPD1_IRQHandler
- def_irq_handler ICACHE_IRQHandler
- def_irq_handler OTFDEC1_IRQHandler
-
- .end
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_ns.S b/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_ns.S
deleted file mode 100644
index 18bd49cac6..0000000000
--- a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_ns.S
+++ /dev/null
@@ -1,418 +0,0 @@
-;/*
-; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long WWDG_IRQHandler /* Window WatchDog */
- .long PVD_PVM_IRQHandler /* PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */
- .long RTC_IRQHandler /* RTC non-secure interrupts through the EXTI line */
- .long RTC_IRQHandler_S /* RRTC secure interrupts through the EXTI line */
- .long TAMP_IRQHandler /* RTamper non-secure interrupts through the EXTI line */
- .long TAMP_IRQHandler_S /* RTamper secure interrupts through the EXTI line */
- .long FLASH_IRQHandler /* RFLASH non-secure interrupts */
- .long FLASH_IRQHandler_S /* RFLASH secure global interrupts */
- .long SERR_IRQHandler /* RSecure Error interrupts */
- .long RCC_IRQHandler /* RRCC non-secure global interrupts */
- .long RCC_IRQHandler_S /* RRCC secure global interrupts */
- .long EXTI0_IRQHandler /* REXTI Line0 */
- .long EXTI1_IRQHandler /* REXTI Line1 */
- .long EXTI2_IRQHandler /* REXTI Line2 */
- .long EXTI3_IRQHandler /* REXTI Line3 */
- .long EXTI4_IRQHandler /* REXTI Line4 */
- .long EXTI5_IRQHandler /* REXTI Line5 */
- .long EXTI6_IRQHandler /* REXTI Line6 */
- .long EXTI7_IRQHandler /* REXTI Line7 */
- .long EXTI8_IRQHandler /* REXTI Line8 */
- .long EXTI9_IRQHandler /* REXTI Line9 */
- .long EXTI10_IRQHandler /* EXTI Line10 */
- .long EXTI11_IRQHandler /* EXTI Line11 */
- .long EXTI12_IRQHandler /* EXTI Line12 */
- .long EXTI13_IRQHandler /* EXTI Line13 */
- .long EXTI14_IRQHandler /* EXTI Line14 */
- .long EXTI15_IRQHandler /* EXTI Line15 */
- .long DMAMUX1_IRQHandler /* DMAMUX1 non-secure */
- .long DMAMUX1_IRQHandler_S /* DMAMUX1 secure */
- .long DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
- .long DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
- .long DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
- .long DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
- .long DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
- .long DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
- .long DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
- .long DMA1_Channel8_IRQHandler /* DMA1 Channel 8 */
- .long ADC1_2_IRQHandler /* ADC1 & ADC2 */
- .long DAC_IRQHandler /* DAC1&2 underrun errors */
- .long FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
- .long FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
- .long TIM1_BRK_IRQHandler /* TIM1 Break */
- .long TIM1_UP_IRQHandler /* TIM1 Update */
- .long TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
- .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .long TIM2_IRQHandler /* TIM2 */
- .long TIM3_IRQHandler /* TIM3 */
- .long TIM4_IRQHandler /* TIM4 */
- .long TIM5_IRQHandler /* TIM5 */
- .long TIM6_IRQHandler /* TIM6 */
- .long TIM7_IRQHandler /* TIM7 */
- .long TIM8_BRK_IRQHandler /* TIM8 Break */
- .long TIM8_UP_IRQHandler /* TIM8 Update */
- .long TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
- .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .long I2C1_EV_IRQHandler /* I2C1 Event */
- .long I2C1_ER_IRQHandler /* I2C1 Error */
- .long I2C2_EV_IRQHandler /* I2C2 Event */
- .long I2C2_ER_IRQHandler /* I2C2 Error */
- .long SPI1_IRQHandler /* SPI1 */
- .long SPI2_IRQHandler /* SPI2 */
- .long USART1_IRQHandler /* USART1 */
- .long USART2_IRQHandler /* USART2 */
- .long USART3_IRQHandler /* USART3 */
- .long UART4_IRQHandler /* UART4 */
- .long UART5_IRQHandler /* UART5 */
- .long LPUART1_IRQHandler /* LP UART1 */
- .long LPTIM1_IRQHandler /* LP TIM1 */
- .long LPTIM2_IRQHandler /* LP TIM2 */
- .long TIM15_IRQHandler /* TIM15 */
- .long TIM16_IRQHandler /* TIM16 */
- .long TIM17_IRQHandler /* TIM17 */
- .long COMP_IRQHandler /* COMP1&2 */
- .long USB_FS_IRQHandler /* USB FS */
- .long CRS_IRQHandler /* CRS */
- .long FMC_IRQHandler /* FMC */
- .long OCTOSPI1_IRQHandler /* OctoSPI1 global interrupt */
- .long 0 /* Reserved */
- .long SDMMC1_IRQHandler /* SDMMC1 */
- .long 0 /* Reserved */
- .long DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
- .long DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
- .long DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
- .long DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
- .long DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
- .long DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
- .long DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
- .long DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
- .long I2C3_EV_IRQHandler /* I2C3 event */
- .long I2C3_ER_IRQHandler /* I2C3 error */
- .long SAI1_IRQHandler /* Serial Audio Interface 1 global interrupt */
- .long SAI2_IRQHandler /* Serial Audio Interface 2 global interrupt */
- .long TSC_IRQHandler /* Touch Sense Controller global interrupt */
- .long AES_IRQHandler /* AES global interrupt */
- .long RNG_IRQHandler /* RNG global interrupt */
- .long FPU_IRQHandler /* FPU */
- .long HASH_IRQHandler /* HASH global interrupt */
- .long PKA_IRQHandler /* PKA global interrupt */
- .long LPTIM3_IRQHandler /* LP TIM3 */
- .long SPI3_IRQHandler /* SPI3 */
- .long I2C4_ER_IRQHandler /* I2C4 error */
- .long I2C4_EV_IRQHandler /* I2C4 event */
- .long DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */
- .long DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */
- .long DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */
- .long DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */
- .long UCPD1_IRQHandler /* UCPD1 */
- .long ICACHE_IRQHandler /* ICACHE */
- .long OTFDEC1_IRQHandler /* OTFDEC1 */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- bl SystemInit
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WWDG_IRQHandler
- def_irq_handler PVD_PVM_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler RTC_IRQHandler_S
- def_irq_handler TAMP_IRQHandler
- def_irq_handler TAMP_IRQHandler_S
- def_irq_handler FLASH_IRQHandler
- def_irq_handler FLASH_IRQHandler_S
- def_irq_handler SERR_IRQHandler
- def_irq_handler RCC_IRQHandler
- def_irq_handler RCC_IRQHandler_S
- def_irq_handler EXTI0_IRQHandler
- def_irq_handler EXTI1_IRQHandler
- def_irq_handler EXTI2_IRQHandler
- def_irq_handler EXTI3_IRQHandler
- def_irq_handler EXTI4_IRQHandler
- def_irq_handler EXTI5_IRQHandler
- def_irq_handler EXTI6_IRQHandler
- def_irq_handler EXTI7_IRQHandler
- def_irq_handler EXTI8_IRQHandler
- def_irq_handler EXTI9_IRQHandler
- def_irq_handler EXTI10_IRQHandler
- def_irq_handler EXTI11_IRQHandler
- def_irq_handler EXTI12_IRQHandler
- def_irq_handler EXTI13_IRQHandler
- def_irq_handler EXTI14_IRQHandler
- def_irq_handler EXTI15_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler_S
- def_irq_handler DMA1_Channel1_IRQHandler
- def_irq_handler DMA1_Channel2_IRQHandler
- def_irq_handler DMA1_Channel3_IRQHandler
- def_irq_handler DMA1_Channel4_IRQHandler
- def_irq_handler DMA1_Channel5_IRQHandler
- def_irq_handler DMA1_Channel6_IRQHandler
- def_irq_handler DMA1_Channel7_IRQHandler
- def_irq_handler DMA1_Channel8_IRQHandler
- def_irq_handler ADC1_2_IRQHandler
- def_irq_handler DAC_IRQHandler
- def_irq_handler FDCAN1_IT0_IRQHandler
- def_irq_handler FDCAN1_IT1_IRQHandler
- def_irq_handler TIM1_BRK_IRQHandler
- def_irq_handler TIM1_UP_IRQHandler
- def_irq_handler TIM1_TRG_COM_IRQHandler
- def_irq_handler TIM1_CC_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler TIM3_IRQHandler
- def_irq_handler TIM4_IRQHandler
- def_irq_handler TIM5_IRQHandler
- def_irq_handler TIM6_IRQHandler
- def_irq_handler TIM7_IRQHandler
- def_irq_handler TIM8_BRK_IRQHandler
- def_irq_handler TIM8_UP_IRQHandler
- def_irq_handler TIM8_TRG_COM_IRQHandler
- def_irq_handler TIM8_CC_IRQHandler
- def_irq_handler I2C1_EV_IRQHandler
- def_irq_handler I2C1_ER_IRQHandler
- def_irq_handler I2C2_EV_IRQHandler
- def_irq_handler I2C2_ER_IRQHandler
- def_irq_handler SPI1_IRQHandler
- def_irq_handler SPI2_IRQHandler
- def_irq_handler USART1_IRQHandler
- def_irq_handler USART2_IRQHandler
- def_irq_handler USART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler UART5_IRQHandler
- def_irq_handler LPUART1_IRQHandler
- def_irq_handler LPTIM1_IRQHandler
- def_irq_handler LPTIM2_IRQHandler
- def_irq_handler TIM15_IRQHandler
- def_irq_handler TIM16_IRQHandler
- def_irq_handler TIM17_IRQHandler
- def_irq_handler COMP_IRQHandler
- def_irq_handler USB_FS_IRQHandler
- def_irq_handler CRS_IRQHandler
- def_irq_handler FMC_IRQHandler
- def_irq_handler OCTOSPI1_IRQHandler
- def_irq_handler SDMMC1_IRQHandler
- def_irq_handler DMA2_Channel1_IRQHandler
- def_irq_handler DMA2_Channel2_IRQHandler
- def_irq_handler DMA2_Channel3_IRQHandler
- def_irq_handler DMA2_Channel4_IRQHandler
- def_irq_handler DMA2_Channel5_IRQHandler
- def_irq_handler DMA2_Channel6_IRQHandler
- def_irq_handler DMA2_Channel7_IRQHandler
- def_irq_handler DMA2_Channel8_IRQHandler
- def_irq_handler I2C3_EV_IRQHandler
- def_irq_handler I2C3_ER_IRQHandler
- def_irq_handler SAI1_IRQHandler
- def_irq_handler SAI2_IRQHandler
- def_irq_handler TSC_IRQHandler
- def_irq_handler AES_IRQHandler
- def_irq_handler RNG_IRQHandler
- def_irq_handler FPU_IRQHandler
- def_irq_handler HASH_IRQHandler
- def_irq_handler PKA_IRQHandler
- def_irq_handler LPTIM3_IRQHandler
- def_irq_handler SPI3_IRQHandler
- def_irq_handler I2C4_ER_IRQHandler
- def_irq_handler I2C4_EV_IRQHandler
- def_irq_handler DFSDM1_FLT0_IRQHandler
- def_irq_handler DFSDM1_FLT1_IRQHandler
- def_irq_handler DFSDM1_FLT2_IRQHandler
- def_irq_handler DFSDM1_FLT3_IRQHandler
- def_irq_handler UCPD1_IRQHandler
- def_irq_handler ICACHE_IRQHandler
- def_irq_handler OTFDEC1_IRQHandler
-
- .end
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_s.S b/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_s.S
deleted file mode 100644
index dd1747c3d1..0000000000
--- a/platform/ext/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_s.S
+++ /dev/null
@@ -1,427 +0,0 @@
-;/*
-; * Copyright (c) 2009-2019 Arm Limited
-; *
-; * Licensed under the Apache License, Version 2.0 (the "License");
-; * you may not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * http://www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an "AS IS" BASIS,
-; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; *
-; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
-; */
-
- .syntax unified
- .arch armv8-m.main
-
- .section .vectors
- .align 2
- .globl __Vectors
-__Vectors:
-/* Core interrupts */
- .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long SecureFault_Handler /* Secure Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* Core interrupts */
- .long WWDG_IRQHandler /* Window WatchDog */
- .long PVD_PVM_IRQHandler /* PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */
- .long RTC_IRQHandler /* RTC non-secure interrupts through the EXTI line */
- .long RTC_IRQHandler_S /* RRTC secure interrupts through the EXTI line */
- .long TAMP_IRQHandler /* RTamper non-secure interrupts through the EXTI line */
- .long TAMP_IRQHandler_S /* RTamper secure interrupts through the EXTI line */
- .long FLASH_IRQHandler /* RFLASH non-secure interrupts */
- .long FLASH_IRQHandler_S /* RFLASH secure global interrupts */
- .long SERR_IRQHandler /* RSecure Error interrupts */
- .long RCC_IRQHandler /* RRCC non-secure global interrupts */
- .long RCC_IRQHandler_S /* RRCC secure global interrupts */
- .long EXTI0_IRQHandler /* REXTI Line0 */
- .long EXTI1_IRQHandler /* REXTI Line1 */
- .long EXTI2_IRQHandler /* REXTI Line2 */
- .long EXTI3_IRQHandler /* REXTI Line3 */
- .long EXTI4_IRQHandler /* REXTI Line4 */
- .long EXTI5_IRQHandler /* REXTI Line5 */
- .long EXTI6_IRQHandler /* REXTI Line6 */
- .long EXTI7_IRQHandler /* REXTI Line7 */
- .long EXTI8_IRQHandler /* REXTI Line8 */
- .long EXTI9_IRQHandler /* REXTI Line9 */
- .long EXTI10_IRQHandler /* EXTI Line10 */
- .long EXTI11_IRQHandler /* EXTI Line11 */
- .long EXTI12_IRQHandler /* EXTI Line12 */
- .long EXTI13_IRQHandler /* EXTI Line13 */
- .long EXTI14_IRQHandler /* EXTI Line14 */
- .long EXTI15_IRQHandler /* EXTI Line15 */
- .long DMAMUX1_IRQHandler /* DMAMUX1 non-secure */
- .long DMAMUX1_IRQHandler_S /* DMAMUX1 secure */
- .long DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
- .long DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
- .long DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
- .long DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
- .long DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
- .long DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
- .long DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
- .long DMA1_Channel8_IRQHandler /* DMA1 Channel 8 */
- .long ADC1_2_IRQHandler /* ADC1 & ADC2 */
- .long DAC_IRQHandler /* DAC1&2 underrun errors */
- .long FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
- .long FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
- .long TIM1_BRK_IRQHandler /* TIM1 Break */
- .long TIM1_UP_IRQHandler /* TIM1 Update */
- .long TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
- .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .long TIM2_IRQHandler /* TIM2 */
- .long TIM3_IRQHandler /* TIM3 */
- .long TIM4_IRQHandler /* TIM4 */
- .long TIM5_IRQHandler /* TIM5 */
- .long TIM6_IRQHandler /* TIM6 */
- .long TIM7_IRQHandler /* TIM7 */
- .long TIM8_BRK_IRQHandler /* TIM8 Break */
- .long TIM8_UP_IRQHandler /* TIM8 Update */
- .long TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
- .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .long I2C1_EV_IRQHandler /* I2C1 Event */
- .long I2C1_ER_IRQHandler /* I2C1 Error */
- .long I2C2_EV_IRQHandler /* I2C2 Event */
- .long I2C2_ER_IRQHandler /* I2C2 Error */
- .long SPI1_IRQHandler /* SPI1 */
- .long SPI2_IRQHandler /* SPI2 */
- .long USART1_IRQHandler /* USART1 */
- .long USART2_IRQHandler /* USART2 */
- .long USART3_IRQHandler /* USART3 */
- .long UART4_IRQHandler /* UART4 */
- .long UART5_IRQHandler /* UART5 */
- .long LPUART1_IRQHandler /* LP UART1 */
- .long LPTIM1_IRQHandler /* LP TIM1 */
- .long LPTIM2_IRQHandler /* LP TIM2 */
- .long TIM15_IRQHandler /* TIM15 */
- .long TIM16_IRQHandler /* TIM16 */
- .long TIM17_IRQHandler /* TIM17 */
- .long COMP_IRQHandler /* COMP1&2 */
- .long USB_FS_IRQHandler /* USB FS */
- .long CRS_IRQHandler /* CRS */
- .long FMC_IRQHandler /* FMC */
- .long OCTOSPI1_IRQHandler /* OctoSPI1 global interrupt */
- .long 0 /* Reserved */
- .long SDMMC1_IRQHandler /* SDMMC1 */
- .long 0 /* Reserved */
- .long DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
- .long DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
- .long DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
- .long DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
- .long DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
- .long DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
- .long DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
- .long DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
- .long I2C3_EV_IRQHandler /* I2C3 event */
- .long I2C3_ER_IRQHandler /* I2C3 error */
- .long SAI1_IRQHandler /* Serial Audio Interface 1 global interrupt */
- .long SAI2_IRQHandler /* Serial Audio Interface 2 global interrupt */
- .long TSC_IRQHandler /* Touch Sense Controller global interrupt */
- .long AES_IRQHandler /* AES global interrupt */
- .long RNG_IRQHandler /* RNG global interrupt */
- .long FPU_IRQHandler /* FPU */
- .long HASH_IRQHandler /* HASH global interrupt */
- .long PKA_IRQHandler /* PKA global interrupt */
- .long LPTIM3_IRQHandler /* LP TIM3 */
- .long SPI3_IRQHandler /* SPI3 */
- .long I2C4_ER_IRQHandler /* I2C4 error */
- .long I2C4_EV_IRQHandler /* I2C4 event */
- .long DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */
- .long DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */
- .long DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */
- .long DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */
- .long UCPD1_IRQHandler /* UCPD1 */
- .long ICACHE_IRQHandler /* ICACHE */
- .long OTFDEC1_IRQHandler /* OTFDEC1 */
-
- .size __Vectors, . - __Vectors
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of triplets, each of which specify:
- * offset 0: LMA of start of a section to copy from
- * offset 4: VMA of start of a section to copy to
- * offset 8: size of the section to copy. Must be multiply of 4
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r4, =__copy_table_start__
- ldr r5, =__copy_table_end__
-
-.L_loop0:
- cmp r4, r5
- bge .L_loop0_done
- ldr r1, [r4]
- ldr r2, [r4, #4]
- ldr r3, [r4, #8]
-
-.L_loop0_0:
- subs r3, #4
- ittt ge
- ldrge r0, [r1, r3]
- strge r0, [r2, r3]
- bge .L_loop0_0
-
- adds r4, #12
- b .L_loop0
-
-.L_loop0_done:
-#else
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/* Multiple sections scheme.
- *
- * Between symbol address __copy_table_start__ and __copy_table_end__,
- * there are array of tuples specifying:
- * offset 0: Start of a BSS section
- * offset 4: Size of this BSS section. Must be multiply of 4
- */
- ldr r3, =__zero_table_start__
- ldr r4, =__zero_table_end__
-
-.L_loop2:
- cmp r3, r4
- bge .L_loop2_done
- ldr r1, [r3]
- ldr r2, [r3, #4]
- movs r0, 0
-
-.L_loop2_0:
- subs r2, #4
- itt ge
- strge r0, [r1, r2]
- bge .L_loop2_0
-
- adds r3, #8
- b .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
- cpsid i /* Disable IRQs */
- bl SystemInit
-
- mrs r0, control /* Get control value */
- orr r0, r0, #2 /* Select switch to PSP */
- msr control, r0
- ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
- msr psp, r0
-
-#ifndef __START
-#define __START _start
-#endif
- bl __START
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
-
-/* Macro to define default handlers. */
- .macro def_irq_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- \handler_name:
- b \handler_name
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
- def_irq_handler SecureFault_Handler
- def_irq_handler SVC_Handler
- def_irq_handler DebugMon_Handler
- def_irq_handler PendSV_Handler
- def_irq_handler SysTick_Handler
- def_irq_handler WWDG_IRQHandler
- def_irq_handler PVD_PVM_IRQHandler
- def_irq_handler RTC_IRQHandler
- def_irq_handler RTC_IRQHandler_S
- def_irq_handler TAMP_IRQHandler
- def_irq_handler TAMP_IRQHandler_S
- def_irq_handler FLASH_IRQHandler
- def_irq_handler FLASH_IRQHandler_S
- def_irq_handler SERR_IRQHandler
- def_irq_handler RCC_IRQHandler
- def_irq_handler RCC_IRQHandler_S
- def_irq_handler EXTI0_IRQHandler
- def_irq_handler EXTI1_IRQHandler
- def_irq_handler EXTI2_IRQHandler
- def_irq_handler EXTI3_IRQHandler
- def_irq_handler EXTI4_IRQHandler
- def_irq_handler EXTI5_IRQHandler
- def_irq_handler EXTI6_IRQHandler
- def_irq_handler EXTI7_IRQHandler
- def_irq_handler EXTI8_IRQHandler
- def_irq_handler EXTI9_IRQHandler
- def_irq_handler EXTI10_IRQHandler
- def_irq_handler EXTI11_IRQHandler
- def_irq_handler EXTI12_IRQHandler
- def_irq_handler EXTI13_IRQHandler
- def_irq_handler EXTI14_IRQHandler
- def_irq_handler EXTI15_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler
- def_irq_handler DMAMUX1_IRQHandler_S
- def_irq_handler DMA1_Channel1_IRQHandler
- def_irq_handler DMA1_Channel2_IRQHandler
- def_irq_handler DMA1_Channel3_IRQHandler
- def_irq_handler DMA1_Channel4_IRQHandler
- def_irq_handler DMA1_Channel5_IRQHandler
- def_irq_handler DMA1_Channel6_IRQHandler
- def_irq_handler DMA1_Channel7_IRQHandler
- def_irq_handler DMA1_Channel8_IRQHandler
- def_irq_handler ADC1_2_IRQHandler
- def_irq_handler DAC_IRQHandler
- def_irq_handler FDCAN1_IT0_IRQHandler
- def_irq_handler FDCAN1_IT1_IRQHandler
- def_irq_handler TIM1_BRK_IRQHandler
- def_irq_handler TIM1_UP_IRQHandler
- def_irq_handler TIM1_TRG_COM_IRQHandler
- def_irq_handler TIM1_CC_IRQHandler
- def_irq_handler TIM2_IRQHandler
- def_irq_handler TIM3_IRQHandler
- def_irq_handler TIM4_IRQHandler
- def_irq_handler TIM5_IRQHandler
- def_irq_handler TIM6_IRQHandler
- def_irq_handler TIM7_IRQHandler
- def_irq_handler TIM8_BRK_IRQHandler
- def_irq_handler TIM8_UP_IRQHandler
- def_irq_handler TIM8_TRG_COM_IRQHandler
- def_irq_handler TIM8_CC_IRQHandler
- def_irq_handler I2C1_EV_IRQHandler
- def_irq_handler I2C1_ER_IRQHandler
- def_irq_handler I2C2_EV_IRQHandler
- def_irq_handler I2C2_ER_IRQHandler
- def_irq_handler SPI1_IRQHandler
- def_irq_handler SPI2_IRQHandler
- def_irq_handler USART1_IRQHandler
- def_irq_handler USART2_IRQHandler
- def_irq_handler USART3_IRQHandler
- def_irq_handler UART4_IRQHandler
- def_irq_handler UART5_IRQHandler
- def_irq_handler LPUART1_IRQHandler
- def_irq_handler LPTIM1_IRQHandler
- def_irq_handler LPTIM2_IRQHandler
- def_irq_handler TIM15_IRQHandler
- def_irq_handler TIM16_IRQHandler
- def_irq_handler TIM17_IRQHandler
- def_irq_handler COMP_IRQHandler
- def_irq_handler USB_FS_IRQHandler
- def_irq_handler CRS_IRQHandler
- def_irq_handler FMC_IRQHandler
- def_irq_handler OCTOSPI1_IRQHandler
- def_irq_handler SDMMC1_IRQHandler
- def_irq_handler DMA2_Channel1_IRQHandler
- def_irq_handler DMA2_Channel2_IRQHandler
- def_irq_handler DMA2_Channel3_IRQHandler
- def_irq_handler DMA2_Channel4_IRQHandler
- def_irq_handler DMA2_Channel5_IRQHandler
- def_irq_handler DMA2_Channel6_IRQHandler
- def_irq_handler DMA2_Channel7_IRQHandler
- def_irq_handler DMA2_Channel8_IRQHandler
- def_irq_handler I2C3_EV_IRQHandler
- def_irq_handler I2C3_ER_IRQHandler
- def_irq_handler SAI1_IRQHandler
- def_irq_handler SAI2_IRQHandler
- def_irq_handler TSC_IRQHandler
- def_irq_handler AES_IRQHandler
- def_irq_handler RNG_IRQHandler
- def_irq_handler FPU_IRQHandler
- def_irq_handler HASH_IRQHandler
- def_irq_handler PKA_IRQHandler
- def_irq_handler LPTIM3_IRQHandler
- def_irq_handler SPI3_IRQHandler
- def_irq_handler I2C4_ER_IRQHandler
- def_irq_handler I2C4_EV_IRQHandler
- def_irq_handler DFSDM1_FLT0_IRQHandler
- def_irq_handler DFSDM1_FLT1_IRQHandler
- def_irq_handler DFSDM1_FLT2_IRQHandler
- def_irq_handler DFSDM1_FLT3_IRQHandler
- def_irq_handler UCPD1_IRQHandler
- def_irq_handler ICACHE_IRQHandler
- def_irq_handler OTFDEC1_IRQHandler
-
- .end
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_bl2.icf b/platform/ext/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_bl2.icf
new file mode 100644
index 0000000000..85688dd68c
--- /dev/null
+++ b/platform/ext/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_bl2.icf
@@ -0,0 +1,42 @@
+#include "region_defs.h"
+
+do not initialize { section .noinit };
+initialize by copy with packing = none { readwrite };
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly
+ };
+
+define block LR_CODE with fixed order, maximum size = BL2_CODE_SIZE {block ER_CODE};
+place at address BL2_CODE_START {block LR_CODE};
+
+define block ER_NOHDP_CODE with fixed order, alignment = 8 {
+ readonly section .BL2_NoHdp_Code,
+ readonly object mpu_armv8m_drv.o};
+
+define block LR_NOHDP_CODE with fixed order, maximum size = BL2_NOHDP_CODE_SIZE {block ER_NOHDP_CODE};
+place at address BL2_NOHDP_CODE_START {block LR_NOHDP_CODE};
+
+define block ER_DATA with alignment = 32 {readwrite};
+define block ARM_LIB_STACK with alignment = 32, size = BL2_MSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = BL2_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+keep {block ER_DATA, block ARM_LIB_STACK,
+ block HEAP, block ARM_LIB_HEAP};
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block DATA with fixed order, maximum size = BL2_DATA_SIZE {
+ block ER_DATA,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL
+};
+
+place at address BL2_DATA_START {block DATA};
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_flash_ns.icf b/platform/ext/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_flash_ns.icf
new file mode 100644
index 0000000000..bab5ae4ed6
--- /dev/null
+++ b/platform/ext/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_flash_ns.icf
@@ -0,0 +1,34 @@
+#include "region_defs.h"
+
+
+define block ER_CODE with fixed order, alignment = 8 {
+ section .intvec,
+ readonly};
+define block LR_CODE with fixed order, maximum size = NS_CODE_SIZE {block ER_CODE};
+place at address NS_CODE_START {block LR_CODE};
+
+define block ER_DATA with alignment = 8 {readwrite};
+define block ARM_LIB_STACK_MSP with alignment = 32, size = NS_MSP_STACK_SIZE { };
+define block ARM_LIB_STACK with alignment = 32, size = NS_PSP_STACK_SIZE { };
+define block HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define block ARM_LIB_HEAP with alignment = 8, size = NS_HEAP_SIZE { };
+define overlay HEAP_OVL {block HEAP};
+define overlay HEAP_OVL {block ARM_LIB_HEAP};
+keep {block ARM_LIB_STACK_MSP, block ARM_LIB_STACK,
+ block HEAP, block ARM_LIB_HEAP};
+
+do not initialize { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+define block DATA with fixed order, maximum size = NS_DATA_SIZE {
+ block ER_DATA,
+ block ARM_LIB_STACK_MSP,
+ block ARM_LIB_STACK,
+ overlay HEAP_OVL
+};
+place at address NS_DATA_START {block DATA};
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_bl2.c b/platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_bl2.c
new file mode 100644
index 0000000000..db11f3d330
--- /dev/null
+++ b/platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_bl2.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#include "cmsis.h"
+#include "region.h"
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Reset_Handler (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+#define DEFAULT_IRQ_HANDLER(handler_name) \
+void handler_name(void); \
+__WEAK void handler_name(void) { \
+ while(1); \
+}
+
+/* Exceptions */
+DEFAULT_IRQ_HANDLER(NMI_Handler)
+DEFAULT_IRQ_HANDLER(HardFault_Handler)
+DEFAULT_IRQ_HANDLER(MemManage_Handler)
+DEFAULT_IRQ_HANDLER(BusFault_Handler)
+DEFAULT_IRQ_HANDLER(UsageFault_Handler)
+DEFAULT_IRQ_HANDLER(SecureFault_Handler)
+DEFAULT_IRQ_HANDLER(SVC_Handler)
+DEFAULT_IRQ_HANDLER(DebugMon_Handler)
+DEFAULT_IRQ_HANDLER(PendSV_Handler)
+DEFAULT_IRQ_HANDLER(SysTick_Handler)
+
+DEFAULT_IRQ_HANDLER(WWDG_IRQHandler)
+DEFAULT_IRQ_HANDLER(PVD_PVM_IRQHandler)
+DEFAULT_IRQ_HANDLER(RTC_IRQHandler)
+DEFAULT_IRQ_HANDLER(RTC_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(TAMP_IRQHandler)
+DEFAULT_IRQ_HANDLER(TAMP_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(FLASH_IRQHandler)
+DEFAULT_IRQ_HANDLER(FLASH_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(SERR_IRQHandler)
+DEFAULT_IRQ_HANDLER(RCC_IRQHandler)
+DEFAULT_IRQ_HANDLER(RCC_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(EXTI0_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI2_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI3_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI4_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI5_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI6_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI7_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI8_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI9_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI10_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI11_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI12_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI13_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI14_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI15_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMAMUX1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMAMUX1_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(DMA1_Channel1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel3_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel4_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel5_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel6_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel7_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel8_IRQHandler)
+DEFAULT_IRQ_HANDLER(ADC1_2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DAC_IRQHandler)
+DEFAULT_IRQ_HANDLER(FDCAN1_IT0_IRQHandler)
+DEFAULT_IRQ_HANDLER(FDCAN1_IT1_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_BRK_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_UP_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_TRG_COM_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_CC_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM2_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM3_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM4_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM5_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM6_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM7_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_BRK_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_UP_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_TRG_COM_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_CC_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C1_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C1_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C2_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C2_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(SPI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(SPI2_IRQHandler)
+DEFAULT_IRQ_HANDLER(USART1_IRQHandler)
+DEFAULT_IRQ_HANDLER(USART2_IRQHandler)
+DEFAULT_IRQ_HANDLER(USART3_IRQHandler)
+DEFAULT_IRQ_HANDLER(UART4_IRQHandler)
+DEFAULT_IRQ_HANDLER(UART5_IRQHandler)
+DEFAULT_IRQ_HANDLER(LPUART1_IRQHandler)
+DEFAULT_IRQ_HANDLER(LPTIM1_IRQHandler)
+DEFAULT_IRQ_HANDLER(LPTIM2_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM15_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM16_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM17_IRQHandler)
+DEFAULT_IRQ_HANDLER(COMP_IRQHandler)
+DEFAULT_IRQ_HANDLER(USB_FS_IRQHandler)
+DEFAULT_IRQ_HANDLER(CRS_IRQHandler)
+DEFAULT_IRQ_HANDLER(FMC_IRQHandler)
+DEFAULT_IRQ_HANDLER(OCTOSPI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(SDMMC1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel3_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel4_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel5_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel6_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel7_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel8_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C3_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C3_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(SAI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(SAI2_IRQHandler)
+DEFAULT_IRQ_HANDLER(TSC_IRQHandler)
+#ifdef STM32L562xx
+DEFAULT_IRQ_HANDLER(AES_IRQHandler)
+#endif
+DEFAULT_IRQ_HANDLER(RNG_IRQHandler)
+DEFAULT_IRQ_HANDLER(FPU_IRQHandler)
+DEFAULT_IRQ_HANDLER(HASH_IRQHandler)
+#ifdef STM32L562xx
+DEFAULT_IRQ_HANDLER(PKA_IRQHandler)
+#endif
+DEFAULT_IRQ_HANDLER(LPTIM3_IRQHandler)
+DEFAULT_IRQ_HANDLER(SPI3_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C4_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C4_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT0_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT3_IRQHandler)
+DEFAULT_IRQ_HANDLER(UCPD1_IRQHandler)
+DEFAULT_IRQ_HANDLER(ICACHE_IRQHandler)
+DEFAULT_IRQ_HANDLER(OTFDEC1_IRQHandler)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
+ (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14: NMI Handler */
+ HardFault_Handler, /* -13: Hard Fault Handler */
+ MemManage_Handler, /* -12: MPU Fault Handler */
+ BusFault_Handler, /* -11: Bus Fault Handler */
+ UsageFault_Handler, /* -10: Usage Fault Handler */
+ SecureFault_Handler, /* -9: Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5: SVCall Handler */
+ DebugMon_Handler, /* -4: Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2: PendSV Handler */
+ SysTick_Handler, /* -1: SysTick Handler */
+ WWDG_IRQHandler, /* 0: Window WatchDog */
+ PVD_PVM_IRQHandler, /* 1: PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */
+ RTC_IRQHandler, /* 2: RTC non-secure interrupts through the EXTI line */
+ RTC_IRQHandler_S, /* 3: RRTC secure interrupts through the EXTI line */
+ TAMP_IRQHandler, /* 4: RTamper non-secure interrupts through the EXTI line */
+ TAMP_IRQHandler_S, /* 5: RTamper secure interrupts through the EXTI line */
+ FLASH_IRQHandler, /* 6: RFLASH non-secure interrupts */
+ FLASH_IRQHandler_S, /* 7: RFLASH secure global interrupts */
+ SERR_IRQHandler, /* 8: RSecure Error interrupts */
+ RCC_IRQHandler, /* 9: RRCC non-secure global interrupts */
+ RCC_IRQHandler_S, /* 10: RRCC secure global interrupts */
+ EXTI0_IRQHandler, /* 11: REXTI Line0 */
+ EXTI1_IRQHandler, /* 12: REXTI Line1 */
+ EXTI2_IRQHandler, /* 13: REXTI Line2 */
+ EXTI3_IRQHandler, /* 14: REXTI Line3 */
+ EXTI4_IRQHandler, /* 15: REXTI Line4 */
+ EXTI5_IRQHandler, /* 16: REXTI Line5 */
+ EXTI6_IRQHandler, /* 17: REXTI Line6 */
+ EXTI7_IRQHandler, /* 18: REXTI Line7 */
+ EXTI8_IRQHandler, /* 19: REXTI Line8 */
+ EXTI9_IRQHandler, /* 20: REXTI Line9 */
+ EXTI10_IRQHandler, /* 21: EXTI Line10 */
+ EXTI11_IRQHandler, /* 22: EXTI Line11 */
+ EXTI12_IRQHandler, /* 23: EXTI Line12 */
+ EXTI13_IRQHandler, /* 24: EXTI Line13 */
+ EXTI14_IRQHandler, /* 25: EXTI Line14 */
+ EXTI15_IRQHandler, /* 26: EXTI Line15 */
+ DMAMUX1_IRQHandler, /* 27: DMAMUX1 non-secure */
+ DMAMUX1_IRQHandler_S, /* 28: DMAMUX1 secure */
+ DMA1_Channel1_IRQHandler, /* 29: DMA1 Channel 1 */
+ DMA1_Channel2_IRQHandler, /* 30: DMA1 Channel 2 */
+ DMA1_Channel3_IRQHandler, /* 31: DMA1 Channel 3 */
+ DMA1_Channel4_IRQHandler, /* 32: DMA1 Channel 4 */
+ DMA1_Channel5_IRQHandler, /* 33: DMA1 Channel 5 */
+ DMA1_Channel6_IRQHandler, /* 34: DMA1 Channel 6 */
+ DMA1_Channel7_IRQHandler, /* 35: DMA1 Channel 7 */
+ DMA1_Channel8_IRQHandler, /* 36: DMA1 Channel 8 */
+ ADC1_2_IRQHandler, /* 37: ADC1 & ADC2 */
+ DAC_IRQHandler, /* 38: DAC1&2 underrun errors */
+ FDCAN1_IT0_IRQHandler, /* 39: FDCAN1 Interrupt 0 */
+ FDCAN1_IT1_IRQHandler, /* 40: FDCAN1 Interrupt 1 */
+ TIM1_BRK_IRQHandler, /* 41: TIM1 Break */
+ TIM1_UP_IRQHandler, /* 42: TIM1 Update */
+ TIM1_TRG_COM_IRQHandler, /* 43: TIM1 Trigger and Commutation */
+ TIM1_CC_IRQHandler, /* 44: TIM1 Capture Compare */
+ TIM2_IRQHandler, /* 45: TIM2 */
+ TIM3_IRQHandler, /* 46: TIM3 */
+ TIM4_IRQHandler, /* 47: TIM4 */
+ TIM5_IRQHandler, /* 48: TIM5 */
+ TIM6_IRQHandler, /* 49: TIM6 */
+ TIM7_IRQHandler, /* 50: TIM7 */
+ TIM8_BRK_IRQHandler, /* 51: TIM8 Break */
+ TIM8_UP_IRQHandler, /* 52: TIM8 Update */
+ TIM8_TRG_COM_IRQHandler, /* 53: TIM8 Trigger and Commutation */
+ TIM8_CC_IRQHandler, /* 54: TIM8 Capture Compare */
+ I2C1_EV_IRQHandler, /* 55: I2C1 Event */
+ I2C1_ER_IRQHandler, /* 56: I2C1 Error */
+ I2C2_EV_IRQHandler, /* 57: I2C2 Event */
+ I2C2_ER_IRQHandler, /* 58: I2C2 Error */
+ SPI1_IRQHandler, /* 59: SPI1 */
+ SPI2_IRQHandler, /* 60: SPI2 */
+ USART1_IRQHandler, /* 61: USART1 */
+ USART2_IRQHandler, /* 62: USART2 */
+ USART3_IRQHandler, /* 63: USART3 */
+ UART4_IRQHandler, /* 64: UART4 */
+ UART5_IRQHandler, /* 65: UART5 */
+ LPUART1_IRQHandler, /* 66: LP UART1 */
+ LPTIM1_IRQHandler, /* 67: LP TIM1 */
+ LPTIM2_IRQHandler, /* 68: LP TIM2 */
+ TIM15_IRQHandler, /* 69: TIM15 */
+ TIM16_IRQHandler, /* 70: TIM16 */
+ TIM17_IRQHandler, /* 71: TIM17 */
+ COMP_IRQHandler, /* 72: COMP1&2 */
+ USB_FS_IRQHandler, /* 73: USB FS */
+ CRS_IRQHandler, /* 74: CRS */
+ FMC_IRQHandler, /* 75: FMC */
+ OCTOSPI1_IRQHandler, /* 76: OctoSPI1 global interrupt */
+ 0, /* 77: Reserved */
+ SDMMC1_IRQHandler, /* 78: SDMMC1 */
+ 0, /* 79: Reserved */
+ DMA2_Channel1_IRQHandler, /* 80: DMA2 Channel 1 */
+ DMA2_Channel2_IRQHandler, /* 81: DMA2 Channel 2 */
+ DMA2_Channel3_IRQHandler, /* 82: DMA2 Channel 3 */
+ DMA2_Channel4_IRQHandler, /* 83: DMA2 Channel 4 */
+ DMA2_Channel5_IRQHandler, /* 84: DMA2 Channel 5 */
+ DMA2_Channel6_IRQHandler, /* 85: DMA2 Channel 6 */
+ DMA2_Channel7_IRQHandler, /* 86: DMA2 Channel 7 */
+ DMA2_Channel8_IRQHandler, /* 87: DMA2 Channel 8 */
+ I2C3_EV_IRQHandler, /* 88: I2C3 event */
+ I2C3_ER_IRQHandler, /* 89: I2C3 error */
+ SAI1_IRQHandler, /* 90: Serial Audio Interface 1 global interrupt */
+ SAI2_IRQHandler, /* 91: Serial Audio Interface 2 global interrupt */
+ TSC_IRQHandler, /* 92: Touch Sense Controller global interrupt */
+#ifdef STM32L562xx
+ AES_IRQHandler, /* 93: AES global interrupt */
+#else
+ 0, /* 93: Reserved */
+#endif
+ RNG_IRQHandler, /* 94: RNG global interrupt */
+ FPU_IRQHandler, /* 95: FPU */
+ HASH_IRQHandler, /* 96: HASH global interrupt */
+#ifdef STM32L562xx
+ PKA_IRQHandler, /* 97: PKA global interrupt */
+#else
+ 0, /* 97: Reserved */
+#endif
+ LPTIM3_IRQHandler, /* 98: LP TIM3 */
+ SPI3_IRQHandler, /* 99: SPI3 */
+ I2C4_ER_IRQHandler, /* 100: I2C4 error */
+ I2C4_EV_IRQHandler, /* 101: I2C4 event */
+ DFSDM1_FLT0_IRQHandler, /* 102: DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQHandler, /* 103: DFSDM1 Filter 1 global Interrupt */
+ DFSDM1_FLT2_IRQHandler, /* 104: DFSDM1 Filter 2 global Interrupt */
+ DFSDM1_FLT3_IRQHandler, /* 105: DFSDM1 Filter 3 global Interrupt */
+ UCPD1_IRQHandler, /* 106: UCPD1 */
+ ICACHE_IRQHandler, /* 107: ICACHE */
+ OTFDEC1_IRQHandler /* 108: OTFDEC1 */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_ns.c b/platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_ns.c
new file mode 100644
index 0000000000..831793b7f7
--- /dev/null
+++ b/platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_ns.c
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#include "cmsis.h"
+#include "region.h"
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit)
+#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base)
+
+extern uint32_t __MSP_INITIAL_SP;
+extern uint32_t __MSP_STACK_LIMIT;
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Reset_Handler (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+#define DEFAULT_IRQ_HANDLER(handler_name) \
+void handler_name(void); \
+__WEAK void handler_name(void) { \
+ while(1); \
+}
+
+/* Exceptions */
+DEFAULT_IRQ_HANDLER(NMI_Handler)
+DEFAULT_IRQ_HANDLER(HardFault_Handler)
+DEFAULT_IRQ_HANDLER(MemManage_Handler)
+DEFAULT_IRQ_HANDLER(BusFault_Handler)
+DEFAULT_IRQ_HANDLER(UsageFault_Handler)
+DEFAULT_IRQ_HANDLER(SecureFault_Handler)
+DEFAULT_IRQ_HANDLER(SVC_Handler)
+DEFAULT_IRQ_HANDLER(DebugMon_Handler)
+DEFAULT_IRQ_HANDLER(PendSV_Handler)
+DEFAULT_IRQ_HANDLER(SysTick_Handler)
+
+DEFAULT_IRQ_HANDLER(WWDG_IRQHandler)
+DEFAULT_IRQ_HANDLER(PVD_PVM_IRQHandler)
+DEFAULT_IRQ_HANDLER(RTC_IRQHandler)
+DEFAULT_IRQ_HANDLER(RTC_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(TAMP_IRQHandler)
+DEFAULT_IRQ_HANDLER(TAMP_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(FLASH_IRQHandler)
+DEFAULT_IRQ_HANDLER(FLASH_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(SERR_IRQHandler)
+DEFAULT_IRQ_HANDLER(RCC_IRQHandler)
+DEFAULT_IRQ_HANDLER(RCC_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(EXTI0_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI2_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI3_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI4_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI5_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI6_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI7_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI8_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI9_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI10_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI11_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI12_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI13_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI14_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI15_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMAMUX1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMAMUX1_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(DMA1_Channel1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel3_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel4_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel5_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel6_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel7_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel8_IRQHandler)
+DEFAULT_IRQ_HANDLER(ADC1_2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DAC_IRQHandler)
+DEFAULT_IRQ_HANDLER(FDCAN1_IT0_IRQHandler)
+DEFAULT_IRQ_HANDLER(FDCAN1_IT1_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_BRK_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_UP_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_TRG_COM_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_CC_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM2_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM3_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM4_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM5_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM6_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM7_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_BRK_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_UP_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_TRG_COM_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_CC_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C1_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C1_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C2_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C2_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(SPI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(SPI2_IRQHandler)
+DEFAULT_IRQ_HANDLER(USART1_IRQHandler)
+DEFAULT_IRQ_HANDLER(USART2_IRQHandler)
+DEFAULT_IRQ_HANDLER(USART3_IRQHandler)
+DEFAULT_IRQ_HANDLER(UART4_IRQHandler)
+DEFAULT_IRQ_HANDLER(UART5_IRQHandler)
+DEFAULT_IRQ_HANDLER(LPUART1_IRQHandler)
+DEFAULT_IRQ_HANDLER(LPTIM1_IRQHandler)
+DEFAULT_IRQ_HANDLER(LPTIM2_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM15_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM16_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM17_IRQHandler)
+DEFAULT_IRQ_HANDLER(COMP_IRQHandler)
+DEFAULT_IRQ_HANDLER(USB_FS_IRQHandler)
+DEFAULT_IRQ_HANDLER(CRS_IRQHandler)
+DEFAULT_IRQ_HANDLER(FMC_IRQHandler)
+DEFAULT_IRQ_HANDLER(OCTOSPI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(SDMMC1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel3_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel4_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel5_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel6_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel7_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel8_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C3_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C3_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(SAI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(SAI2_IRQHandler)
+DEFAULT_IRQ_HANDLER(TSC_IRQHandler)
+#ifdef STM32L562xx
+DEFAULT_IRQ_HANDLER(AES_IRQHandler)
+#endif
+DEFAULT_IRQ_HANDLER(RNG_IRQHandler)
+DEFAULT_IRQ_HANDLER(FPU_IRQHandler)
+DEFAULT_IRQ_HANDLER(HASH_IRQHandler)
+#ifdef STM32L562xx
+DEFAULT_IRQ_HANDLER(PKA_IRQHandler)
+#endif
+DEFAULT_IRQ_HANDLER(LPTIM3_IRQHandler)
+DEFAULT_IRQ_HANDLER(SPI3_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C4_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C4_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT0_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT3_IRQHandler)
+DEFAULT_IRQ_HANDLER(UCPD1_IRQHandler)
+DEFAULT_IRQ_HANDLER(ICACHE_IRQHandler)
+DEFAULT_IRQ_HANDLER(OTFDEC1_IRQHandler)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
+ (pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14: NMI Handler */
+ HardFault_Handler, /* -13: Hard Fault Handler */
+ MemManage_Handler, /* -12: MPU Fault Handler */
+ BusFault_Handler, /* -11: Bus Fault Handler */
+ UsageFault_Handler, /* -10: Usage Fault Handler */
+ SecureFault_Handler, /* -9: Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5: SVCall Handler */
+ DebugMon_Handler, /* -4: Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2: PendSV Handler */
+ SysTick_Handler, /* -1: SysTick Handler */
+ WWDG_IRQHandler, /* 0: Window WatchDog */
+ PVD_PVM_IRQHandler, /* 1: PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */
+ RTC_IRQHandler, /* 2: RTC non-secure interrupts through the EXTI line */
+ RTC_IRQHandler_S, /* 3: RRTC secure interrupts through the EXTI line */
+ TAMP_IRQHandler, /* 4: RTamper non-secure interrupts through the EXTI line */
+ TAMP_IRQHandler_S, /* 5: RTamper secure interrupts through the EXTI line */
+ FLASH_IRQHandler, /* 6: RFLASH non-secure interrupts */
+ FLASH_IRQHandler_S, /* 7: RFLASH secure global interrupts */
+ SERR_IRQHandler, /* 8: RSecure Error interrupts */
+ RCC_IRQHandler, /* 9: RRCC non-secure global interrupts */
+ RCC_IRQHandler_S, /* 10: RRCC secure global interrupts */
+ EXTI0_IRQHandler, /* 11: REXTI Line0 */
+ EXTI1_IRQHandler, /* 12: REXTI Line1 */
+ EXTI2_IRQHandler, /* 13: REXTI Line2 */
+ EXTI3_IRQHandler, /* 14: REXTI Line3 */
+ EXTI4_IRQHandler, /* 15: REXTI Line4 */
+ EXTI5_IRQHandler, /* 16: REXTI Line5 */
+ EXTI6_IRQHandler, /* 17: REXTI Line6 */
+ EXTI7_IRQHandler, /* 18: REXTI Line7 */
+ EXTI8_IRQHandler, /* 19: REXTI Line8 */
+ EXTI9_IRQHandler, /* 20: REXTI Line9 */
+ EXTI10_IRQHandler, /* 21: EXTI Line10 */
+ EXTI11_IRQHandler, /* 22: EXTI Line11 */
+ EXTI12_IRQHandler, /* 23: EXTI Line12 */
+ EXTI13_IRQHandler, /* 24: EXTI Line13 */
+ EXTI14_IRQHandler, /* 25: EXTI Line14 */
+ EXTI15_IRQHandler, /* 26: EXTI Line15 */
+ DMAMUX1_IRQHandler, /* 27: DMAMUX1 non-secure */
+ DMAMUX1_IRQHandler_S, /* 28: DMAMUX1 secure */
+ DMA1_Channel1_IRQHandler, /* 29: DMA1 Channel 1 */
+ DMA1_Channel2_IRQHandler, /* 30: DMA1 Channel 2 */
+ DMA1_Channel3_IRQHandler, /* 31: DMA1 Channel 3 */
+ DMA1_Channel4_IRQHandler, /* 32: DMA1 Channel 4 */
+ DMA1_Channel5_IRQHandler, /* 33: DMA1 Channel 5 */
+ DMA1_Channel6_IRQHandler, /* 34: DMA1 Channel 6 */
+ DMA1_Channel7_IRQHandler, /* 35: DMA1 Channel 7 */
+ DMA1_Channel8_IRQHandler, /* 36: DMA1 Channel 8 */
+ ADC1_2_IRQHandler, /* 37: ADC1 & ADC2 */
+ DAC_IRQHandler, /* 38: DAC1&2 underrun errors */
+ FDCAN1_IT0_IRQHandler, /* 39: FDCAN1 Interrupt 0 */
+ FDCAN1_IT1_IRQHandler, /* 40: FDCAN1 Interrupt 1 */
+ TIM1_BRK_IRQHandler, /* 41: TIM1 Break */
+ TIM1_UP_IRQHandler, /* 42: TIM1 Update */
+ TIM1_TRG_COM_IRQHandler, /* 43: TIM1 Trigger and Commutation */
+ TIM1_CC_IRQHandler, /* 44: TIM1 Capture Compare */
+ TIM2_IRQHandler, /* 45: TIM2 */
+ TIM3_IRQHandler, /* 46: TIM3 */
+ TIM4_IRQHandler, /* 47: TIM4 */
+ TIM5_IRQHandler, /* 48: TIM5 */
+ TIM6_IRQHandler, /* 49: TIM6 */
+ TIM7_IRQHandler, /* 50: TIM7 */
+ TIM8_BRK_IRQHandler, /* 51: TIM8 Break */
+ TIM8_UP_IRQHandler, /* 52: TIM8 Update */
+ TIM8_TRG_COM_IRQHandler, /* 53: TIM8 Trigger and Commutation */
+ TIM8_CC_IRQHandler, /* 54: TIM8 Capture Compare */
+ I2C1_EV_IRQHandler, /* 55: I2C1 Event */
+ I2C1_ER_IRQHandler, /* 56: I2C1 Error */
+ I2C2_EV_IRQHandler, /* 57: I2C2 Event */
+ I2C2_ER_IRQHandler, /* 58: I2C2 Error */
+ SPI1_IRQHandler, /* 59: SPI1 */
+ SPI2_IRQHandler, /* 60: SPI2 */
+ USART1_IRQHandler, /* 61: USART1 */
+ USART2_IRQHandler, /* 62: USART2 */
+ USART3_IRQHandler, /* 63: USART3 */
+ UART4_IRQHandler, /* 64: UART4 */
+ UART5_IRQHandler, /* 65: UART5 */
+ LPUART1_IRQHandler, /* 66: LP UART1 */
+ LPTIM1_IRQHandler, /* 67: LP TIM1 */
+ LPTIM2_IRQHandler, /* 68: LP TIM2 */
+ TIM15_IRQHandler, /* 69: TIM15 */
+ TIM16_IRQHandler, /* 70: TIM16 */
+ TIM17_IRQHandler, /* 71: TIM17 */
+ COMP_IRQHandler, /* 72: COMP1&2 */
+ USB_FS_IRQHandler, /* 73: USB FS */
+ CRS_IRQHandler, /* 74: CRS */
+ FMC_IRQHandler, /* 75: FMC */
+ OCTOSPI1_IRQHandler, /* 76: OctoSPI1 global interrupt */
+ 0, /* 77: Reserved */
+ SDMMC1_IRQHandler, /* 78: SDMMC1 */
+ 0, /* 79: Reserved */
+ DMA2_Channel1_IRQHandler, /* 80: DMA2 Channel 1 */
+ DMA2_Channel2_IRQHandler, /* 81: DMA2 Channel 2 */
+ DMA2_Channel3_IRQHandler, /* 82: DMA2 Channel 3 */
+ DMA2_Channel4_IRQHandler, /* 83: DMA2 Channel 4 */
+ DMA2_Channel5_IRQHandler, /* 84: DMA2 Channel 5 */
+ DMA2_Channel6_IRQHandler, /* 85: DMA2 Channel 6 */
+ DMA2_Channel7_IRQHandler, /* 86: DMA2 Channel 7 */
+ DMA2_Channel8_IRQHandler, /* 87: DMA2 Channel 8 */
+ I2C3_EV_IRQHandler, /* 88: I2C3 event */
+ I2C3_ER_IRQHandler, /* 89: I2C3 error */
+ SAI1_IRQHandler, /* 90: Serial Audio Interface 1 global interrupt */
+ SAI2_IRQHandler, /* 91: Serial Audio Interface 2 global interrupt */
+ TSC_IRQHandler, /* 92: Touch Sense Controller global interrupt */
+#ifdef STM32L562xx
+ AES_IRQHandler, /* 93: AES global interrupt */
+#else
+ 0, /* 93: Reserved */
+#endif
+ RNG_IRQHandler, /* 94: RNG global interrupt */
+ FPU_IRQHandler, /* 95: FPU */
+ HASH_IRQHandler, /* 96: HASH global interrupt */
+#ifdef STM32L562xx
+ PKA_IRQHandler, /* 97: PKA global interrupt */
+#else
+ 0, /* 97: Reserved */
+#endif
+ LPTIM3_IRQHandler, /* 98: LP TIM3 */
+ SPI3_IRQHandler, /* 99: SPI3 */
+ I2C4_ER_IRQHandler, /* 100: I2C4 error */
+ I2C4_EV_IRQHandler, /* 101: I2C4 event */
+ DFSDM1_FLT0_IRQHandler, /* 102: DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQHandler, /* 103: DFSDM1 Filter 1 global Interrupt */
+ DFSDM1_FLT2_IRQHandler, /* 104: DFSDM1 Filter 2 global Interrupt */
+ DFSDM1_FLT3_IRQHandler, /* 105: DFSDM1 Filter 3 global Interrupt */
+ UCPD1_IRQHandler, /* 106: UCPD1 */
+ ICACHE_IRQHandler, /* 107: ICACHE */
+ OTFDEC1_IRQHandler /* 108: OTFDEC1 */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT));
+
+ SystemInit(); /* CMSIS System Initialization */
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+ __ASM volatile("MRS R0, control\n" /* Get control value */
+ "ORR R0, R0, #1\n" /* Select switch to unprivilage mode */
+ "ORR R0, R0, #2\n" /* Select switch to PSP */
+ "MSR control, R0\n" /* Load control register */
+ :
+ :
+ : "r0");
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
diff --git a/platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_s.c b/platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_s.c
new file mode 100644
index 0000000000..8c7869585f
--- /dev/null
+++ b/platform/ext/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_s.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#include "cmsis.h"
+#include "region.h"
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit)
+#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base)
+
+extern uint32_t __MSP_INITIAL_SP;
+extern uint32_t __MSP_STACK_LIMIT;
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Reset_Handler (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+#define DEFAULT_IRQ_HANDLER(handler_name) \
+void handler_name(void); \
+__WEAK void handler_name(void) { \
+ while(1); \
+}
+
+/* Exceptions */
+DEFAULT_IRQ_HANDLER(NMI_Handler)
+DEFAULT_IRQ_HANDLER(HardFault_Handler)
+DEFAULT_IRQ_HANDLER(MemManage_Handler)
+DEFAULT_IRQ_HANDLER(BusFault_Handler)
+DEFAULT_IRQ_HANDLER(UsageFault_Handler)
+DEFAULT_IRQ_HANDLER(SecureFault_Handler)
+DEFAULT_IRQ_HANDLER(SVC_Handler)
+DEFAULT_IRQ_HANDLER(DebugMon_Handler)
+DEFAULT_IRQ_HANDLER(PendSV_Handler)
+DEFAULT_IRQ_HANDLER(SysTick_Handler)
+
+DEFAULT_IRQ_HANDLER(WWDG_IRQHandler)
+DEFAULT_IRQ_HANDLER(PVD_PVM_IRQHandler)
+DEFAULT_IRQ_HANDLER(RTC_IRQHandler)
+DEFAULT_IRQ_HANDLER(RTC_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(TAMP_IRQHandler)
+DEFAULT_IRQ_HANDLER(TAMP_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(FLASH_IRQHandler)
+DEFAULT_IRQ_HANDLER(FLASH_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(SERR_IRQHandler)
+DEFAULT_IRQ_HANDLER(RCC_IRQHandler)
+DEFAULT_IRQ_HANDLER(RCC_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(EXTI0_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI2_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI3_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI4_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI5_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI6_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI7_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI8_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI9_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI10_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI11_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI12_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI13_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI14_IRQHandler)
+DEFAULT_IRQ_HANDLER(EXTI15_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMAMUX1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMAMUX1_IRQHandler_S)
+DEFAULT_IRQ_HANDLER(DMA1_Channel1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel3_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel4_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel5_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel6_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel7_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA1_Channel8_IRQHandler)
+DEFAULT_IRQ_HANDLER(ADC1_2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DAC_IRQHandler)
+DEFAULT_IRQ_HANDLER(FDCAN1_IT0_IRQHandler)
+DEFAULT_IRQ_HANDLER(FDCAN1_IT1_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_BRK_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_UP_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_TRG_COM_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM1_CC_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM2_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM3_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM4_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM5_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM6_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM7_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_BRK_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_UP_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_TRG_COM_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM8_CC_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C1_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C1_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C2_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C2_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(SPI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(SPI2_IRQHandler)
+DEFAULT_IRQ_HANDLER(USART1_IRQHandler)
+DEFAULT_IRQ_HANDLER(USART2_IRQHandler)
+DEFAULT_IRQ_HANDLER(USART3_IRQHandler)
+DEFAULT_IRQ_HANDLER(UART4_IRQHandler)
+DEFAULT_IRQ_HANDLER(UART5_IRQHandler)
+DEFAULT_IRQ_HANDLER(LPUART1_IRQHandler)
+DEFAULT_IRQ_HANDLER(LPTIM1_IRQHandler)
+DEFAULT_IRQ_HANDLER(LPTIM2_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM15_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM16_IRQHandler)
+DEFAULT_IRQ_HANDLER(TIM17_IRQHandler)
+DEFAULT_IRQ_HANDLER(COMP_IRQHandler)
+DEFAULT_IRQ_HANDLER(USB_FS_IRQHandler)
+DEFAULT_IRQ_HANDLER(CRS_IRQHandler)
+DEFAULT_IRQ_HANDLER(FMC_IRQHandler)
+DEFAULT_IRQ_HANDLER(OCTOSPI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(SDMMC1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel3_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel4_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel5_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel6_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel7_IRQHandler)
+DEFAULT_IRQ_HANDLER(DMA2_Channel8_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C3_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C3_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(SAI1_IRQHandler)
+DEFAULT_IRQ_HANDLER(SAI2_IRQHandler)
+DEFAULT_IRQ_HANDLER(TSC_IRQHandler)
+#ifdef STM32L562xx
+DEFAULT_IRQ_HANDLER(AES_IRQHandler)
+#endif
+DEFAULT_IRQ_HANDLER(RNG_IRQHandler)
+DEFAULT_IRQ_HANDLER(FPU_IRQHandler)
+DEFAULT_IRQ_HANDLER(HASH_IRQHandler)
+#ifdef STM32L562xx
+DEFAULT_IRQ_HANDLER(PKA_IRQHandler)
+#endif
+DEFAULT_IRQ_HANDLER(LPTIM3_IRQHandler)
+DEFAULT_IRQ_HANDLER(SPI3_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C4_ER_IRQHandler)
+DEFAULT_IRQ_HANDLER(I2C4_EV_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT0_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT1_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT2_IRQHandler)
+DEFAULT_IRQ_HANDLER(DFSDM1_FLT3_IRQHandler)
+DEFAULT_IRQ_HANDLER(UCPD1_IRQHandler)
+DEFAULT_IRQ_HANDLER(ICACHE_IRQHandler)
+DEFAULT_IRQ_HANDLER(OTFDEC1_IRQHandler)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const pFunc __VECTOR_TABLE[];
+ const pFunc __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
+ (pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14: NMI Handler */
+ HardFault_Handler, /* -13: Hard Fault Handler */
+ MemManage_Handler, /* -12: MPU Fault Handler */
+ BusFault_Handler, /* -11: Bus Fault Handler */
+ UsageFault_Handler, /* -10: Usage Fault Handler */
+ SecureFault_Handler, /* -9: Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5: SVCall Handler */
+ DebugMon_Handler, /* -4: Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2: PendSV Handler */
+ SysTick_Handler, /* -1: SysTick Handler */
+ WWDG_IRQHandler, /* 0: Window WatchDog */
+ PVD_PVM_IRQHandler, /* 1: PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */
+ RTC_IRQHandler, /* 2: RTC non-secure interrupts through the EXTI line */
+ RTC_IRQHandler_S, /* 3: RRTC secure interrupts through the EXTI line */
+ TAMP_IRQHandler, /* 4: RTamper non-secure interrupts through the EXTI line */
+ TAMP_IRQHandler_S, /* 5: RTamper secure interrupts through the EXTI line */
+ FLASH_IRQHandler, /* 6: RFLASH non-secure interrupts */
+ FLASH_IRQHandler_S, /* 7: RFLASH secure global interrupts */
+ SERR_IRQHandler, /* 8: RSecure Error interrupts */
+ RCC_IRQHandler, /* 9: RRCC non-secure global interrupts */
+ RCC_IRQHandler_S, /* 10: RRCC secure global interrupts */
+ EXTI0_IRQHandler, /* 11: REXTI Line0 */
+ EXTI1_IRQHandler, /* 12: REXTI Line1 */
+ EXTI2_IRQHandler, /* 13: REXTI Line2 */
+ EXTI3_IRQHandler, /* 14: REXTI Line3 */
+ EXTI4_IRQHandler, /* 15: REXTI Line4 */
+ EXTI5_IRQHandler, /* 16: REXTI Line5 */
+ EXTI6_IRQHandler, /* 17: REXTI Line6 */
+ EXTI7_IRQHandler, /* 18: REXTI Line7 */
+ EXTI8_IRQHandler, /* 19: REXTI Line8 */
+ EXTI9_IRQHandler, /* 20: REXTI Line9 */
+ EXTI10_IRQHandler, /* 21: EXTI Line10 */
+ EXTI11_IRQHandler, /* 22: EXTI Line11 */
+ EXTI12_IRQHandler, /* 23: EXTI Line12 */
+ EXTI13_IRQHandler, /* 24: EXTI Line13 */
+ EXTI14_IRQHandler, /* 25: EXTI Line14 */
+ EXTI15_IRQHandler, /* 26: EXTI Line15 */
+ DMAMUX1_IRQHandler, /* 27: DMAMUX1 non-secure */
+ DMAMUX1_IRQHandler_S, /* 28: DMAMUX1 secure */
+ DMA1_Channel1_IRQHandler, /* 29: DMA1 Channel 1 */
+ DMA1_Channel2_IRQHandler, /* 30: DMA1 Channel 2 */
+ DMA1_Channel3_IRQHandler, /* 31: DMA1 Channel 3 */
+ DMA1_Channel4_IRQHandler, /* 32: DMA1 Channel 4 */
+ DMA1_Channel5_IRQHandler, /* 33: DMA1 Channel 5 */
+ DMA1_Channel6_IRQHandler, /* 34: DMA1 Channel 6 */
+ DMA1_Channel7_IRQHandler, /* 35: DMA1 Channel 7 */
+ DMA1_Channel8_IRQHandler, /* 36: DMA1 Channel 8 */
+ ADC1_2_IRQHandler, /* 37: ADC1 & ADC2 */
+ DAC_IRQHandler, /* 38: DAC1&2 underrun errors */
+ FDCAN1_IT0_IRQHandler, /* 39: FDCAN1 Interrupt 0 */
+ FDCAN1_IT1_IRQHandler, /* 40: FDCAN1 Interrupt 1 */
+ TIM1_BRK_IRQHandler, /* 41: TIM1 Break */
+ TIM1_UP_IRQHandler, /* 42: TIM1 Update */
+ TIM1_TRG_COM_IRQHandler, /* 43: TIM1 Trigger and Commutation */
+ TIM1_CC_IRQHandler, /* 44: TIM1 Capture Compare */
+ TIM2_IRQHandler, /* 45: TIM2 */
+ TIM3_IRQHandler, /* 46: TIM3 */
+ TIM4_IRQHandler, /* 47: TIM4 */
+ TIM5_IRQHandler, /* 48: TIM5 */
+ TIM6_IRQHandler, /* 49: TIM6 */
+ TIM7_IRQHandler, /* 50: TIM7 */
+ TIM8_BRK_IRQHandler, /* 51: TIM8 Break */
+ TIM8_UP_IRQHandler, /* 52: TIM8 Update */
+ TIM8_TRG_COM_IRQHandler, /* 53: TIM8 Trigger and Commutation */
+ TIM8_CC_IRQHandler, /* 54: TIM8 Capture Compare */
+ I2C1_EV_IRQHandler, /* 55: I2C1 Event */
+ I2C1_ER_IRQHandler, /* 56: I2C1 Error */
+ I2C2_EV_IRQHandler, /* 57: I2C2 Event */
+ I2C2_ER_IRQHandler, /* 58: I2C2 Error */
+ SPI1_IRQHandler, /* 59: SPI1 */
+ SPI2_IRQHandler, /* 60: SPI2 */
+ USART1_IRQHandler, /* 61: USART1 */
+ USART2_IRQHandler, /* 62: USART2 */
+ USART3_IRQHandler, /* 63: USART3 */
+ UART4_IRQHandler, /* 64: UART4 */
+ UART5_IRQHandler, /* 65: UART5 */
+ LPUART1_IRQHandler, /* 66: LP UART1 */
+ LPTIM1_IRQHandler, /* 67: LP TIM1 */
+ LPTIM2_IRQHandler, /* 68: LP TIM2 */
+ TIM15_IRQHandler, /* 69: TIM15 */
+ TIM16_IRQHandler, /* 70: TIM16 */
+ TIM17_IRQHandler, /* 71: TIM17 */
+ COMP_IRQHandler, /* 72: COMP1&2 */
+ USB_FS_IRQHandler, /* 73: USB FS */
+ CRS_IRQHandler, /* 74: CRS */
+ FMC_IRQHandler, /* 75: FMC */
+ OCTOSPI1_IRQHandler, /* 76: OctoSPI1 global interrupt */
+ 0, /* 77: Reserved */
+ SDMMC1_IRQHandler, /* 78: SDMMC1 */
+ 0, /* 79: Reserved */
+ DMA2_Channel1_IRQHandler, /* 80: DMA2 Channel 1 */
+ DMA2_Channel2_IRQHandler, /* 81: DMA2 Channel 2 */
+ DMA2_Channel3_IRQHandler, /* 82: DMA2 Channel 3 */
+ DMA2_Channel4_IRQHandler, /* 83: DMA2 Channel 4 */
+ DMA2_Channel5_IRQHandler, /* 84: DMA2 Channel 5 */
+ DMA2_Channel6_IRQHandler, /* 85: DMA2 Channel 6 */
+ DMA2_Channel7_IRQHandler, /* 86: DMA2 Channel 7 */
+ DMA2_Channel8_IRQHandler, /* 87: DMA2 Channel 8 */
+ I2C3_EV_IRQHandler, /* 88: I2C3 event */
+ I2C3_ER_IRQHandler, /* 89: I2C3 error */
+ SAI1_IRQHandler, /* 90: Serial Audio Interface 1 global interrupt */
+ SAI2_IRQHandler, /* 91: Serial Audio Interface 2 global interrupt */
+ TSC_IRQHandler, /* 92: Touch Sense Controller global interrupt */
+#ifdef STM32L562xx
+ AES_IRQHandler, /* 93: AES global interrupt */
+#else
+ 0, /* 93: Reserved */
+#endif
+ RNG_IRQHandler, /* 94: RNG global interrupt */
+ FPU_IRQHandler, /* 95: FPU */
+ HASH_IRQHandler, /* 96: HASH global interrupt */
+#ifdef STM32L562xx
+ PKA_IRQHandler, /* 97: PKA global interrupt */
+#else
+ 0, /* 97: Reserved */
+#endif
+ LPTIM3_IRQHandler, /* 98: LP TIM3 */
+ SPI3_IRQHandler, /* 99: SPI3 */
+ I2C4_ER_IRQHandler, /* 100: I2C4 error */
+ I2C4_EV_IRQHandler, /* 101: I2C4 event */
+ DFSDM1_FLT0_IRQHandler, /* 102: DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQHandler, /* 103: DFSDM1 Filter 1 global Interrupt */
+ DFSDM1_FLT2_IRQHandler, /* 104: DFSDM1 Filter 2 global Interrupt */
+ DFSDM1_FLT3_IRQHandler, /* 105: DFSDM1 Filter 3 global Interrupt */
+ UCPD1_IRQHandler, /* 106: UCPD1 */
+ ICACHE_IRQHandler, /* 107: ICACHE */
+ OTFDEC1_IRQHandler /* 108: OTFDEC1 */
+};
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ __disable_irq();
+ __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT));
+ SystemInit(); /* CMSIS System Initialization */
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+ __ASM volatile("MRS R0, control\n" /* Get control value */
+ "ORR R0, R0, #2\n" /* Select switch to PSP */
+ "MSR control, R0\n" /* Load control register */
+ :
+ :
+ : "r0");
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
diff --git a/platform/ext/target/stm/stm32l5xx/bl2/boot_hal.c b/platform/ext/target/stm/stm32l5xx/bl2/boot_hal.c
index 8df0015fdf..6982cff5d8 100644
--- a/platform/ext/target/stm/stm32l5xx/bl2/boot_hal.c
+++ b/platform/ext/target/stm/stm32l5xx/bl2/boot_hal.c
@@ -30,9 +30,13 @@
extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
/* Place code in a specific section */
-#if defined(__GNUC__)
+#if defined(__ICCARM__)
+#pragma default_function_attributes = @ ".BL2_NoHdp_Code"
+#elif defined(__CC_ARM)
+#pragma arm section code = ".BL2_NoHdp_Code"
+#else
__attribute__((section(".BL2_NoHdp_Code")))
-#endif /* __GNUC__ */
+#endif /* __ICCARM__ */
__attribute__((naked)) void boot_jump_to_next_image(uint32_t reset_handler_addr)
{
__ASM volatile(
@@ -57,10 +61,21 @@ __attribute__((naked)) void boot_jump_to_next_image(uint32_t reset_handler_addr)
"bx r7 \n" /* Jump to Reset_handler */
);
}
+/* Stop placing data in specified section */
+#if defined(__ICCARM__)
+#pragma default_function_attributes =
+#elif defined(__CC_ARM)
+#pragma arm section code
+#endif /* __ICCARM__ */
+
/* Place code in a specific section */
-#if defined(__GNUC__)
+#if defined(__ICCARM__)
+#pragma default_function_attributes = @ ".BL2_NoHdp_Code"
+#elif defined(__CC_ARM)
+#pragma arm section code = ".BL2_NoHdp_Code"
+#else
__attribute__((section(".BL2_NoHdp_Code")))
-#endif /* __GNUC__ */
+#endif /* __ICCARM__ */
/**
* @brief This function is called to clear all RAM area before jumping in
* in Secure application .
@@ -92,12 +107,21 @@ void boot_platform_quit(struct boot_arm_vector_table *vt)
boot_jump_to_next_image(vt_cpy->reset);
}
+/* Stop placing data in specified section */
+#if defined(__ICCARM__)
+#pragma default_function_attributes =
+#elif defined(__CC_ARM)
+#pragma arm section code
+#endif /* __ICCARM__ */
/* Place code in a specific section */
-#if defined(__GNUC__)
+#if defined(__ICCARM__)
+#pragma default_function_attributes = @ ".BL2_NoHdp_Code"
+#elif defined(__CC_ARM)
+#pragma arm section code = ".BL2_NoHdp_Code"
+#else
__attribute__((section(".BL2_NoHdp_Code")))
-#endif /* __GNUC__ */
-
+#endif /* __ICCARM__ */
/**
* @brief This function is called to clear all RAM area before jumping in
* in Secure application .
diff --git a/platform/ext/target/stm/stm32l5xx/boards/nucleo_l552ze_q/flash_layout.h b/platform/ext/target/stm/stm32l5xx/boards/nucleo_l552ze_q/flash_layout.h
index 64e695fd52..e0d0e1cc2c 100644
--- a/platform/ext/target/stm/stm32l5xx/boards/nucleo_l552ze_q/flash_layout.h
+++ b/platform/ext/target/stm/stm32l5xx/boards/nucleo_l552ze_q/flash_layout.h
@@ -63,12 +63,12 @@
/* area for BL2 code protected by hdp */
#define FLASH_AREA_BL2_OFFSET (0x0)
-#define FLASH_AREA_BL2_SIZE (0xF000)
+#define FLASH_AREA_BL2_SIZE (0xF800)
/* HDP area end at this address */
#define FLASH_BL2_HDP_END (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE-1)
/* area for BL2 code not protected by hdp */
#define FLASH_AREA_BL2_NOHDP_OFFSET (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE)
-#define FLASH_AREA_BL2_NOHDP_SIZE (0x1000)
+#define FLASH_AREA_BL2_NOHDP_SIZE (0x800)
/* scratch area */
#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_BL2_NOHDP_OFFSET+FLASH_AREA_BL2_NOHDP_SIZE)
diff --git a/platform/ext/target/stm/stm32l5xx/boards/scripts/armclang/preprocess.sh b/platform/ext/target/stm/stm32l5xx/boards/scripts/armclang/preprocess.sh
new file mode 100644
index 0000000000..a243bc2d8b
--- /dev/null
+++ b/platform/ext/target/stm/stm32l5xx/boards/scripts/armclang/preprocess.sh
@@ -0,0 +1,20 @@
+#!/bin/bash -
+#******************************************************************************
+# * @attention
+# *
+# * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+# * All rights reserved.</center></h2>
+# *
+# * This software component is licensed by ST under BSD 3-Clause license,
+# * the "License"; You may not use this file except in compliance with the
+# * License. You may obtain a copy of the License at:
+# * opensource.org/licenses/BSD-3-Clause
+# *
+# ******************************************************************************
+# arg1 is the build directory
+# arg2 is the file to preprocess
+# arg3 is output file beeing preprocessed
+function preprocess
+(
+armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -P -xc -I$1 $2 -o $3
+)
diff --git a/platform/ext/target/stm/stm32l5xx/boards/scripts/gcc/preprocess.sh b/platform/ext/target/stm/stm32l5xx/boards/scripts/gcc/preprocess.sh
new file mode 100644
index 0000000000..f6a8cf107c
--- /dev/null
+++ b/platform/ext/target/stm/stm32l5xx/boards/scripts/gcc/preprocess.sh
@@ -0,0 +1,20 @@
+#!/bin/bash -
+#******************************************************************************
+# * @attention
+# *
+# * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+# * All rights reserved.</center></h2>
+# *
+# * This software component is licensed by ST under BSD 3-Clause license,
+# * the "License"; You may not use this file except in compliance with the
+# * License. You may obtain a copy of the License at:
+# * opensource.org/licenses/BSD-3-Clause
+# *
+# ******************************************************************************
+# arg1 is the build directory
+# arg2 is the file to preprocess
+# arg3 is output file beeing preprocessed
+function preprocess
+(
+arm-none-eabi-gcc -E -P -xc -I$1 -o$3 $2
+)
diff --git a/platform/ext/target/stm/stm32l5xx/boards/scripts/iar/preprocess.sh b/platform/ext/target/stm/stm32l5xx/boards/scripts/iar/preprocess.sh
new file mode 100644
index 0000000000..c1ca468937
--- /dev/null
+++ b/platform/ext/target/stm/stm32l5xx/boards/scripts/iar/preprocess.sh
@@ -0,0 +1,20 @@
+#!/bin/bash -
+#******************************************************************************
+# * @attention
+# *
+# * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+# * All rights reserved.</center></h2>
+# *
+# * This software component is licensed by ST under BSD 3-Clause license,
+# * the "License"; You may not use this file except in compliance with the
+# * License. You may obtain a copy of the License at:
+# * opensource.org/licenses/BSD-3-Clause
+# *
+# ******************************************************************************
+# arg1 is the build directory
+# arg2 is the file to preprocess
+# arg3 is output file beeing preprocessed
+function preprocess
+(
+iccarm --cpu=Cortex-M33 -I$1 $2 --silent --preprocess=ns $3
+) \ No newline at end of file
diff --git a/platform/ext/target/stm/stm32l5xx/boards/scripts/postbuild.sh b/platform/ext/target/stm/stm32l5xx/boards/scripts/postbuild.sh
index 605fd00170..d894a3db60 100755..100644
--- a/platform/ext/target/stm/stm32l5xx/boards/scripts/postbuild.sh
+++ b/platform/ext/target/stm/stm32l5xx/boards/scripts/postbuild.sh
@@ -16,6 +16,7 @@
SCRIPT=$(readlink -f $0)
# Absolute path this script
projectdir=`dirname $SCRIPT`
+source $projectdir/preprocess.sh
# the file to preprocess is generated and present outside of install dir
bl2_file_to_preprocess=$projectdir/../image_macros_to_preprocess_bl2.c
preprocess_bl2_file=$projectdir/../image_macros_preprocessed_bl2.c
@@ -24,7 +25,7 @@ updatesh=$projectdir/TFM_UPDATE.sh
basedir=$projectdir
echo preprocess bl2 file
-arm-none-eabi-gcc -E -P -xc -I$projectdir -o$preprocess_bl2_file $bl2_file_to_preprocess
+preprocess $projectdir $bl2_file_to_preprocess $preprocess_bl2_file
stm_tool=$basedir"/scripts/stm_tool.py"
#determine/check python version command
cmd="python3"
diff --git a/platform/ext/target/stm/stm32l5xx/boards/stm32l562e_dk/flash_layout.h b/platform/ext/target/stm/stm32l5xx/boards/stm32l562e_dk/flash_layout.h
index d2cdc2a824..fe33fc9f78 100644
--- a/platform/ext/target/stm/stm32l5xx/boards/stm32l562e_dk/flash_layout.h
+++ b/platform/ext/target/stm/stm32l5xx/boards/stm32l562e_dk/flash_layout.h
@@ -63,12 +63,12 @@
/* area for BL2 code protected by hdp */
#define FLASH_AREA_BL2_OFFSET (0x0)
-#define FLASH_AREA_BL2_SIZE (0xF000)
+#define FLASH_AREA_BL2_SIZE (0xF800)
/* HDP area end at this address */
#define FLASH_BL2_HDP_END (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE-1)
/* area for BL2 code not protected by hdp */
#define FLASH_AREA_BL2_NOHDP_OFFSET (FLASH_AREA_BL2_OFFSET+FLASH_AREA_BL2_SIZE)
-#define FLASH_AREA_BL2_NOHDP_SIZE (0x1000)
+#define FLASH_AREA_BL2_NOHDP_SIZE (0x800)
/* scratch area */
#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_BL2_NOHDP_OFFSET+FLASH_AREA_BL2_NOHDP_SIZE)
diff --git a/platform/ext/target/stm/stm32l5xx/nucleo_l552ze_q.cmake b/platform/ext/target/stm/stm32l5xx/nucleo_l552ze_q.cmake
index a8f2daf5e8..b23701ea3f 100644
--- a/platform/ext/target/stm/stm32l5xx/nucleo_l552ze_q.cmake
+++ b/platform/ext/target/stm/stm32l5xx/nucleo_l552ze_q.cmake
@@ -28,13 +28,33 @@ if(COMPILER STREQUAL "GNUARM")
set(BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/gcc/stm32l5xx_bl2.ld")
set(S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/gcc/tfm_common_s.ld")
set(NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/gcc/stm32l5xx_ns.ld")
+ set(PREPROCESS_BL2_FILE "${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/gcc/preprocess.sh")
if (DEFINED CMSIS_DIR)
# not all project defines CMSIS_DIR, only the ones that use it.
- set (RTX_LIB_PATH "${CMSIS_DIR}/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a")
+ set(RTX_LIB_PATH "${CMSIS_DIR}/RTOS2/RTX/Library/GCC/RTX_V8MMN.a")
+ endif()
+elseif(COMPILER STREQUAL "ARMCLANG")
+ set(S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/armclang/tfm_common_s.sct")
+ set(BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_bl2.sct")
+ set(NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_ns.sct")
+ set(PREPROCESS_BL2_FILE "${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/armclang/preprocess.sh")
+ if (DEFINED CMSIS_DIR)
+ # Not all projects define CMSIS_5_DIR, only the ones that use it.
+ set(RTX_LIB_PATH "${CMSIS_DIR}/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib")
+ endif()
+elseif(COMPILER STREQUAL "IARARM")
+ set(S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/iar/tfm_common_s.icf")
+ set(BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_bl2.icf")
+ set(NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_flash_ns.icf")
+ set(PREPROCESS_BL2_FILE "${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/iar/preprocess.sh")
+ if (DEFINED CMSIS_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_DIR}/RTOS2/RTX/Library/IAR/RTX_V8MMN.a")
endif()
else()
message(FATAL_ERROR "'${COMPILER}' is not supported.")
endif()
+
if (REGRESSION OR CORE_TEST OR IPC_TEST OR PSA_API_TEST)
set(FLASH_LAYOUT "${PLATFORM_DIR}/target/stm/stm32l5xx/boards/nucleo_l552ze_q/flash_layout_test.h")
else()
@@ -45,7 +65,7 @@ set(PLATFORM_LINK_INCLUDES "${PLATFORM_DIR}/target/stm/stm32l5xx/boards/nucleo_l
if (BL2)
- set (BL2_LINKER_CONFIG ${BL2_SCATTER_FILE_NAME})
+ set(BL2_LINKER_CONFIG ${BL2_SCATTER_FILE_NAME})
endif()
embedded_include_directories(PATH "${PLATFORM_DIR}/cmsis" ABSOLUTE)
@@ -78,22 +98,10 @@ elseif(BUILD_TIME)
#fix me add a cmsis_driver for L5
endif()
-if (NOT DEFINED BUILD_STARTUP)
- message(FATAL_ERROR "Configuration variable BUILD_STARTUP (true|false) is undefined!")
-elseif(BUILD_STARTUP)
- list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_s.S")
- list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_ns.S")
- list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l552xx_bl2.S")
- set_property(SOURCE "${ALL_SRC_ASM_S}" APPEND
- PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
- set_property(SOURCE "${ALL_SRC_ASM_NS}" APPEND
- PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
-endif()
-
if (NOT DEFINED BUILD_FLASH)
message(FATAL_ERROR "Configuration variable BUILD_FLASH (true|false) is undefined!")
elseif(BUILD_FLASH)
-#list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/stm/stm32l5xx/CMSIS_Driver/Driver_Flash.c")
+ #list(APPEND ALL_SRC_C "${PLATFORM_DIR}/target/stm/stm32l5xx/CMSIS_Driver/Driver_Flash.c")
# As the PS area is going to be in RAM, it is required to set PS_CREATE_FLASH_LAYOUT
# to be sure the PS service knows that when it starts the PS area does not contain any
# valid PS flash layout and it needs to create one.
@@ -142,5 +150,6 @@ install(FILES ${PLATFORM_DIR}/target/stm/stm32l5xx/boards/stm32l562e_dk/flash_la
install(FILES ${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/regression.sh
${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/TFM_UPDATE.sh
${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/postbuild.sh
+ ${PREPROCESS_BL2_FILE}
PERMISSIONS OWNER_EXECUTE OWNER_WRITE OWNER_READ
- DESTINATION ./ PERMISSIONS WORLD_EXECUTE)
+ DESTINATION ./ )
diff --git a/platform/ext/target/stm/stm32l5xx/secure/system_stm32l5xx.c b/platform/ext/target/stm/stm32l5xx/secure/system_stm32l5xx.c
index fff63ccca4..5d6fd7d91b 100644
--- a/platform/ext/target/stm/stm32l5xx/secure/system_stm32l5xx.c
+++ b/platform/ext/target/stm/stm32l5xx/secure/system_stm32l5xx.c
@@ -190,8 +190,8 @@
void SystemInit(void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-extern uint32_t __Vectors;
- SCB->VTOR = (uint32_t) &__Vectors;
+ extern uint32_t __VECTOR_TABLE;
+ SCB->VTOR = (uint32_t) &__VECTOR_TABLE;
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
diff --git a/platform/ext/target/stm/stm32l5xx/secure/target_cfg.c b/platform/ext/target/stm/stm32l5xx/secure/target_cfg.c
index d968699ae1..efd039a568 100644
--- a/platform/ext/target/stm/stm32l5xx/secure/target_cfg.c
+++ b/platform/ext/target/stm/stm32l5xx/secure/target_cfg.c
@@ -15,6 +15,7 @@
*/
#include "cmsis.h"
+#include "region.h"
#include "target_cfg.h"
#include "Driver_MPC.h"
#include "region_defs.h"
@@ -23,10 +24,6 @@
/* fix me to move to a CMSIS driver */
#include "stm32l5xx_hal.h"
#include <stdio.h>
-/* Macros to pick linker symbols */
-#define REGION(a, b, c) a##b##c
-#define REGION_NAME(a, b, c) REGION(a, b, c)
-#define REGION_DECLARE(a, b, c) extern uint32_t REGION_NAME(a, b, c)
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
diff --git a/platform/ext/target/stm/stm32l5xx/stm32l562e_dk.cmake b/platform/ext/target/stm/stm32l5xx/stm32l562e_dk.cmake
index 7856e81fc4..7c8447a9ec 100644
--- a/platform/ext/target/stm/stm32l5xx/stm32l562e_dk.cmake
+++ b/platform/ext/target/stm/stm32l5xx/stm32l562e_dk.cmake
@@ -24,15 +24,33 @@ add_definitions("-DSTM32L562xx")
add_definitions("-DTFM_OB_RDP_LEVEL_VALUE=0xAA")
include ("${PLATFORM_DIR}/target/stm/stm32l5xx/stm32l5xx.cmake")
#Specify the location of platform specific build dependencies.
-
-if(COMPILER STREQUAL "GNUARM")
+if (COMPILER STREQUAL "GNUARM")
set(BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/gcc/stm32l5xx_bl2.ld")
set(S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/gcc/tfm_common_s.ld")
set(NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/gcc/stm32l5xx_ns.ld")
+ set(PREPROCESS_BL2_FILE "${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/gcc/preprocess.sh")
if (DEFINED CMSIS_DIR)
# not all project defines CMSIS_DIR, only the ones that use it.
set(RTX_LIB_PATH "${CMSIS_DIR}/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a")
endif()
+elseif(COMPILER STREQUAL "ARMCLANG")
+ set(S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/armclang/tfm_common_s.sct")
+ set(BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_bl2.sct")
+ set(NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/armclang/stm32l5xx_ns.sct")
+ set(PREPROCESS_BL2_FILE "${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/armclang/preprocess.sh")
+ if (DEFINED CMSIS_DIR)
+ # Not all projects define CMSIS_5_DIR, only the ones that use it.
+ set(RTX_LIB_PATH "${CMSIS_DIR}/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib")
+ endif()
+elseif(COMPILER STREQUAL "IARARM")
+ set(S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/iar/tfm_common_s.icf")
+ set(BL2_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_bl2.icf")
+ set(NS_SCATTER_FILE_NAME "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/iar/stm32l5xx_flash_ns.icf")
+ set(PREPROCESS_BL2_FILE "${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/iar/preprocess.sh")
+ if (DEFINED CMSIS_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_DIR}/RTOS2/RTX/Library/IAR/RTX_V8MMN.a")
+ endif()
else()
message(FATAL_ERROR "'${COMPILER}' is not supported.")
endif()
@@ -74,19 +92,7 @@ endif()
if (NOT DEFINED BUILD_TIME)
message(FATAL_ERROR "Configuration variable BUILD_TIME (true|false) is undefined!")
elseif(BUILD_TIME)
- #fix me add a cmsis_driver for L5
-endif()
-
-if (NOT DEFINED BUILD_STARTUP)
- message(FATAL_ERROR "Configuration variable BUILD_STARTUP (true|false) is undefined!")
-elseif(BUILD_STARTUP)
- list(APPEND ALL_SRC_ASM_S "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_s.S")
- list(APPEND ALL_SRC_ASM_NS "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_ns.S")
- list(APPEND ALL_SRC_ASM_BL2 "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/gcc/startup_stm32l562xx_bl2.S")
- set_property(SOURCE "${ALL_SRC_ASM_S}" APPEND
- PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
- set_property(SOURCE "${ALL_SRC_ASM_NS}" APPEND
- PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
+#fix me add a cmsis_driver for L5
endif()
if (NOT DEFINED BUILD_FLASH)
@@ -141,5 +147,6 @@ install(FILES ${PLATFORM_DIR}/target/stm/stm32l5xx/boards/stm32l562e_dk/flash_la
install(FILES ${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/regression.sh
${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/TFM_UPDATE.sh
${PLATFORM_DIR}/target/stm/stm32l5xx/boards/scripts/postbuild.sh
+ ${PREPROCESS_BL2_FILE}
PERMISSIONS OWNER_EXECUTE OWNER_WRITE OWNER_READ
DESTINATION ./ )
diff --git a/platform/ext/target/stm/stm32l5xx/stm32l5xx.cmake b/platform/ext/target/stm/stm32l5xx/stm32l5xx.cmake
index b5d45a3d6f..4e7449c7d8 100644
--- a/platform/ext/target/stm/stm32l5xx/stm32l5xx.cmake
+++ b/platform/ext/target/stm/stm32l5xx/stm32l5xx.cmake
@@ -5,7 +5,13 @@
#-------------------------------------------------------------------------------
#This file gathers all stm32l5 hal specific files , CMSIS and Native Driver, application file common to all L5 family soc/board
-
+if (NOT DEFINED BUILD_STARTUP)
+ message(FATAL_ERROR "Configuration variable BUILD_STARTUP (true|false) is undefined!")
+elseif(BUILD_STARTUP)
+ list(APPEND ALL_SRC_C_BL2 "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_bl2.c")
+ list(APPEND ALL_SRC_C_NS "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_ns.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/startup_stm32l5xx_s.c")
+endif()
#hal L5 file
list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/stm/stm32l5xx/stm32l5xx_hal/Src/stm32l5xx_hal_uart.c")
list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/stm/stm32l5xx/stm32l5xx_hal/Src/stm32l5xx_hal_uart_ex.c")
@@ -62,8 +68,12 @@ elseif(BUILD_TARGET_CFG)
list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/stm/stm32l5xx/secure/target_cfg.c")
list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/stm/stm32l5xx/secure/spm_hal.c")
list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/stm/stm32l5xx/Native_Driver/tick.c")
- list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/common/template/crypto_keys.c")
- list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/common/template/tfm_rotpk.c")
+ if (NOT DEFINED BUILD_TARGET_HARDWARE_KEYS)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_HARDWARE_KEYS (true|false) is undefined!")
+ elseif(BUILD_TARGET_HARDWARE_KEYS)
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/common/template/crypto_keys.c")
+ list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/common/template/tfm_rotpk.c")
+ endif()
list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/common/template/attest_hal.c")
list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/target/stm/stm32l5xx/secure/system_stm32l5xx.c")
list(APPEND ALL_SRC_C_S "${PLATFORM_DIR}/common/template/tfm_initial_attestation_key_material.c")
@@ -79,8 +89,12 @@ endif()
list(APPEND ALL_SRC_C_BL2 "${PLATFORM_DIR}/target/stm/stm32l5xx/bl2/tfm_low_level_security.c")
list(APPEND ALL_SRC_C_BL2 "${PLATFORM_DIR}/target/stm/stm32l5xx/Device/Source/Templates/system_stm32l5xx.c")
list(APPEND ALL_SRC_C_BL2 "${PLATFORM_DIR}/target/stm/stm32l5xx/Native_Driver/tick.c")
- list(APPEND ALL_SRC_C_BL2 "${PLATFORM_DIR}/common/template/crypto_keys.c")
- list(APPEND ALL_SRC_C_BL2 "${PLATFORM_DIR}/common/template/tfm_rotpk.c")
+ if (NOT DEFINED BUILD_TARGET_HARDWARE_KEYS)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_HARDWARE_KEYS (true|false) is undefined!")
+ elseif(BUILD_TARGET_HARDWARE_KEYS)
+ list(APPEND ALL_SRC_C_BL2 "${PLATFORM_DIR}/common/template/crypto_keys.c")
+ list(APPEND ALL_SRC_C_BL2 "${PLATFORM_DIR}/common/template/tfm_rotpk.c")
+ endif()
list(APPEND ALL_SRC_C_BL2 "${PLATFORM_DIR}/common/boot_hal.c")
if (NOT DEFINED BUILD_NATIVE_DRIVERS)