aboutsummaryrefslogtreecommitdiff
path: root/plat/ti/k3/common/k3_gicv3.c
blob: 3253130f6e765f63c05f2d233d15ad8681f56fe9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
/*
 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <bl_common.h>
#include <gicv3.h>
#include <interrupt_props.h>
#include <k3_gicv3.h>
#include <platform.h>
#include <platform_def.h>
#include <utils.h>

/* The GICv3 driver only needs to be initialized in EL3 */
uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];

static const interrupt_prop_t k3_interrupt_props[] = {
	PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
	PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
};

static unsigned int k3_mpidr_to_core_pos(unsigned long mpidr)
{
	return (unsigned int)plat_core_pos_by_mpidr(mpidr);
}

gicv3_driver_data_t k3_gic_data = {
	.rdistif_num = PLATFORM_CORE_COUNT,
	.rdistif_base_addrs = rdistif_base_addrs,
	.interrupt_props = k3_interrupt_props,
	.interrupt_props_num = ARRAY_SIZE(k3_interrupt_props),
	.mpidr_to_core_pos = k3_mpidr_to_core_pos,
};

void k3_gic_driver_init(uintptr_t gicd_base, uintptr_t gicr_base)
{
	/*
	 * The GICv3 driver is initialized in EL3 and does not need
	 * to be initialized again in SEL1. This is because the S-EL1
	 * can use GIC system registers to manage interrupts and does
	 * not need GIC interface base addresses to be configured.
	 */
	k3_gic_data.gicd_base = gicd_base;
	k3_gic_data.gicr_base = gicr_base;
	gicv3_driver_init(&k3_gic_data);
}

void k3_gic_init(void)
{
	gicv3_distif_init();
	gicv3_rdistif_init(plat_my_core_pos());
	gicv3_cpuif_enable(plat_my_core_pos());
}

void k3_gic_cpuif_enable(void)
{
	gicv3_cpuif_enable(plat_my_core_pos());
}

void k3_gic_cpuif_disable(void)
{
	gicv3_cpuif_disable(plat_my_core_pos());
}

void k3_gic_pcpu_init(void)
{
	gicv3_rdistif_init(plat_my_core_pos());
}