aboutsummaryrefslogtreecommitdiff
path: root/plat/hisilicon/hikey/hisi_ipc.c
blob: 4936f8316974f20520db795edf3e0a16be5084fa (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
/*
 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <arch_helpers.h>
#include <debug.h>
#include <hisi_ipc.h>
#include <hisi_sram_map.h>
#include <mmio.h>
#include <platform_def.h>
#include <stdarg.h>
#include <string.h>

static int ipc_init;

static unsigned int cpu_ipc_num[PLATFORM_CLUSTER_COUNT][PLATFORM_CORE_COUNT_PER_CLUSTER] = {
	{
		HISI_IPC_MCU_INT_SRC_ACPU0_PD,
		HISI_IPC_MCU_INT_SRC_ACPU1_PD,
		HISI_IPC_MCU_INT_SRC_ACPU2_PD,
		HISI_IPC_MCU_INT_SRC_ACPU3_PD,
	},
	{
		HISI_IPC_MCU_INT_SRC_ACPU4_PD,
		HISI_IPC_MCU_INT_SRC_ACPU5_PD,
		HISI_IPC_MCU_INT_SRC_ACPU6_PD,
		HISI_IPC_MCU_INT_SRC_ACPU7_PD,
	}
};

int hisi_cpus_pd_in_cluster_besides_curr(unsigned int cpu,
					 unsigned int cluster)
{
	unsigned int val = 0, cpu_val = 0;
	int i;

	val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR);
	val = val >> (cluster * 16);

	for (i = 0; i < PLATFORM_CORE_COUNT_PER_CLUSTER; i++) {

		if (cpu == i)
			continue;

		cpu_val = (val >> (i * 4)) & 0xF;
		if (cpu_val == 0x8)
			return 0;
	}

	return 1;
}

int hisi_cpus_powered_off_besides_curr(unsigned int cpu)
{
	unsigned int val;

	val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR);
	return (val == (0x8 << (cpu * 4)));
}

static void hisi_ipc_send(unsigned int ipc_num)
{
	if (!ipc_init) {
		tf_printf("error ipc base is null!!!\n");
		return;
	}

	mmio_write_32(HISI_IPC_CPU_RAW_INT_ADDR, 1 << ipc_num);
}

void hisi_ipc_spin_lock(unsigned int signal)
{
	unsigned int hs_ctrl;

	if (signal >= HISI_IPC_INT_SRC_NUM)
		return;

	do {
		hs_ctrl = mmio_read_32(HISI_IPC_ACPU_CTRL(signal));
	} while (hs_ctrl);
}

void hisi_ipc_spin_unlock(unsigned int signal)
{
	if (signal >= HISI_IPC_INT_SRC_NUM)
		return;

	mmio_write_32(HISI_IPC_ACPU_CTRL(signal), 0);
}

void hisi_ipc_cpu_on_off(unsigned int cpu, unsigned int cluster,
			 unsigned int mode)
{
	unsigned int val = 0;
	unsigned int offset;

	if (mode == HISI_IPC_PM_ON)
		offset = cluster * 16 + cpu * 4;
	else
		offset = cluster * 16 + cpu * 4 + 1;

	hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
	val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR);
	val |= (0x01 << offset);
	mmio_write_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR, val);
	isb();
	dsb();
	hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);

	hisi_ipc_send(cpu_ipc_num[cluster][cpu]);
}

void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster)
{
	hisi_ipc_cpu_on_off(cpu, cluster, HISI_IPC_PM_ON);
}

void hisi_ipc_cpu_off(unsigned int cpu, unsigned int cluster)
{
	hisi_ipc_cpu_on_off(cpu, cluster, HISI_IPC_PM_OFF);
}

void hisi_ipc_cluster_on_off(unsigned int cpu, unsigned int cluster,
			     unsigned int mode)
{
	unsigned int val = 0;
	unsigned int offset;

	if (mode == HISI_IPC_PM_ON)
		offset = cluster * 4;
	else
		offset = cluster * 4 + 1;

	hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
	val = mmio_read_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR);
	val |= (0x01 << offset);
	mmio_write_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR, val);
	isb();
	dsb();
	hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);

	hisi_ipc_send(cpu_ipc_num[cluster][cpu]);
}

void hisi_ipc_cluster_on(unsigned int cpu, unsigned int cluster)
{
	hisi_ipc_cluster_on_off(cpu, cluster, HISI_IPC_PM_ON);
}

void hisi_ipc_cluster_off(unsigned int cpu, unsigned int cluster)
{
	hisi_ipc_cluster_on_off(cpu, cluster, HISI_IPC_PM_OFF);
}

void hisi_ipc_cpu_suspend(unsigned int cpu, unsigned int cluster)
{
	unsigned int val = 0;
	unsigned int offset;

	offset = cluster * 16 + cpu * 4 + 2;

	hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
	val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR);
	val |= (0x01 << offset);
	mmio_write_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR, val);
	hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);

	hisi_ipc_send(cpu_ipc_num[cluster][cpu]);
}

void hisi_ipc_cluster_suspend(unsigned int cpu, unsigned int cluster)
{
	unsigned int val;
	unsigned int offset;

	offset = cluster * 4 + 1;

	hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
	if (hisi_cpus_pd_in_cluster_besides_curr(cpu, cluster)) {
		val = mmio_read_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR);
		val |= (0x01 << offset);
		mmio_write_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR, val);
	}
	hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);

	hisi_ipc_send(cpu_ipc_num[cluster][cpu]);
}

void hisi_ipc_psci_system_off(void)
{
	hisi_ipc_send(HISI_IPC_MCU_INT_SRC_ACPU_PD);
}

int hisi_ipc_init(void)
{
	ipc_init = 1;

	mmio_write_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR, 0x8);
	mmio_write_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR, 0x8);
	return 0;
}