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2024-03-14Merge "refactor(sdei): use common create_spsr() in SDEI library" into ↵Lauren Wehrmeister
integration
2024-03-08Merge "refactor(cm): couple el2 registers with dependent feature flags" into ↵Manish Pandey
integration
2024-03-07refactor(sdei): use common create_spsr() in SDEI libraryArvind Ram Prakash
The current SPSR updation code as part of the SDEI interrupt handler code is outdated. This patch replaces the legacy code with a call to an up-to-date create_spsr() Change-Id: I1f5fdd41dd14f4b09601310fe881fa3783d7f505 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
2024-03-07refactor(cm): couple el2 registers with dependent feature flagsJayanth Dodderi Chidanand
Currently the EL2 part of the context structure (el2_sysregs_t), is mostly feature dependent. For instance, CTX_HCRX_EL2 is only needed when FEAT_HCX (ENABLE_FEAT_HCX=1) is set, but the entry is unconditionally added in the EL2 context structure and thereby consuming memory even in build configurations where FEAT_HCX is disabled. Henceforth, all such context entries should be coupled/tied with their respective feature enables and be optimized away when unused. This would reduce the context memory allocation for platforms, that dont enable/support all the architectural features at once. Further, converting the assembly context-offset entries into a c structure relies on garbage collection of the linker removing unreferenced structures from memory, as well as aiding in readability and future maintenance. Change-Id: I0cf49498ee3033cb6f3ee3810331121b26627783 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2024-03-06fix(cpus): workaround for Cortex-X4 erratum 2701112Sona Mathew
Cortex-X4 erratum 2701112 is cat B erratum that applies to revision r0p0 and is fixed in r0p1. This erratum affects system configurations that do not use an Arm interconnect IP. The workaround for this erratum is not implemented in EL3. The erratum can be enabled/disabled on a platform level. The flag is used when the errata ABI feature is enabled and can assist the Kernel in the process of mitigation of the erratum. SDEN Documentation: https://developer.arm.com/documentation/SDEN2432808/latest Change-Id: I8ede1ee75b0ea1658369a0646d8af91d44a8759b Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2024-03-06Merge changes from topic "drtm1.0-updates" into integrationManish V Badarkhe
* changes: feat(drtm): update DRTM version to 1.0 feat(drtm): update references to DRTM beta0 feat(drtm): for TPM features fw hash algorithm should be 16-bits feat(drtm): add ACPI table region size to the DLME header feat(drtm): update return code if secondary PE is not off feat(drtm): add additional return codes
2024-03-05feat(drtm): update references to DRTM beta0Stuart Yoder
Update all references to DRTM beta0 to be 1.0 instead. Signed-off-by: Stuart Yoder <stuart.yoder@arm.com> Change-Id: Ieda70f26f3be42f4705e9b267706674c94f120f2
2024-03-05feat(drtm): add ACPI table region size to the DLME headerStuart Yoder
The DRTM 1.0 spec defines an additional field in the DLME header for an optional region in the DLME to hold ACPI tables. Signed-off-by: Stuart Yoder <stuart.yoder@arm.com> Change-Id: Idba7fa6bd0fb4ef2bdffc24f4588720e1661e58c
2024-03-05feat(drtm): update return code if secondary PE is not offStuart Yoder
DRTM 1.0 specifies that if any secondary PEs are not off during a dynamic launch the return code must be SECONDARY_PE_NOT_OFF. Signed-off-by: Stuart Yoder <stuart.yoder@arm.com> Change-Id: Idcb1f3c60daa63a5bc994bdeacca8aab7066f628
2024-03-05feat(drtm): add additional return codesStuart Yoder
Add additional return codes defined in the DRTM 1.0 spec. Signed-off-by: Stuart Yoder <stuart.yoder@arm.com> Change-Id: I1620e098edf4f070ac759a26ce3c7272faf2d8b2
2024-03-05fix(cpus): add erratum 2701951 to Cortex-X3's listSona Mathew
Erratum ID 2701951 is an erratum that could affect platforms that do not use an Arm interconnect IP. This was originally added to the list of Cortex-A715 in the errata ABI files. Fixed this by adding it to the Cortex-X3 list. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2024-03-05refactor(errata-abi): workaround platforms non-arm interconnectSona Mathew
The workarounds for these below mentioned errata are not implemented in EL3, but the flags can be enabled/disabled at a platform level based on arm/non-arm interconnect IP flag. The ABI helps assist the Kernel in the process of mitigation for the following errata: Cortex-A715: erratum 2701951 Neoverse V2: erratum 2719103 Cortex-A710: erratum 2701952 Cortex-X2: erratum 2701952 Neoverse N2: erratum 2728475 Neoverse V1: erratum 2701953 Cortex-A78: erratum 2712571 Cortex-A78AE: erratum 2712574 Cortex-A78C: erratum 2712575 Change-Id: Ie86b7212d731a79e2a0c07649e69234e733cd78d Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2024-03-05refactor(errata-abi): optimize errata ABI using errata frameworkSona Mathew
Errata ABI feature introduced per CPU based errata structures in the errata_abi_main.c, these can be removed by re-using the structures created by the errata framework. Change-Id: I1a60d3e4f116b6254fb45426f43ff1b21771af89 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2024-03-01fix(cpus): workaround for Cortex-A715 erratum 2429384Bipin Ravi
Cortex-A715 erratum 2429384 is a cat B erratum that applies to revision r1p0 and is fixed in r1p1. The workaround is to set bit[27] of CPUACTLR2_EL1. There is no workaround for revision r0p0. SDEN can be found here: https://developer.arm.com/documentation/SDEN2148827/latest Change-Id: I3cdb1b71567542174759f6946e9c81f77d0d993d Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>
2024-02-28fix(cpus): workaround for Cortex-X3 erratum 2372204Bipin Ravi
Cortex-X3 erratum 2372204 is a Cat B erratum that applies to revisions r0p0 and r1p0. It is fixed in r1p1. The workaround is to set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests into older prefetches with L2 miss requests outstanding. SDEN can be found here: https://developer.arm.com/documentation/SDEN2055130/latest Change-Id: Iad28f8625c84186fbd8049406d139d4f15c6e069 Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>
2024-02-22refactor(context-mgmt): remove el1_context routines from RMMJayanth Dodderi Chidanand
This is an effort to optimise the unused members in the cpu_context_t structure. TF-A statically allocates memory for context entry for each wolrd per PE. Some of the members in this struct are not used for all the build combinations. RMM in particular, is not using this context member and henceforth removing them. Change-Id: Ia5bf9c8dfef6e856ba6d88fa678876c704d42858 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2024-02-20Merge "build: use toolchain identifiers in conditions" into integrationMark Dykes
2024-02-20Merge "build: use new toolchain variables for tools" into integrationMark Dykes
2024-02-14fix(el3-spmc): fix dangling pointer in FFA_CONSOLE_LOGKarl Meakin
Fixes a dangling pointer bug in `spmc_ffa_console_log`. `chars` was assigned to an array which went out of scope at the end of the `if`/`else` block. The solution is to `memcmpy` from the temporary array into `chars`, which is now an array. Signed-off-by: Karl Meakin <karl.meakin@arm.com> Change-Id: I67d19ea25d09b72f38fcc67dab4acf449aa8f1b1
2024-02-07Merge changes from topic "od/sme" into integrationMadhukar Pappireddy
* changes: fix(fvp): permit enabling SME for SPD=spmd feat(spmd): pass SMCCCv1.3 SVE hint to lower EL
2024-02-07feat(spmd): pass SMCCCv1.3 SVE hint to lower ELOlivier Deprez
A normal world caller can emit an SMC with the SVE hint bit set such that the callee can perform an optimization by omitting to save/restore the SVE context. Update the SPMD to pass this information to the SPMC when set by the caller in the SMC flags parameter. For now, restrict this behavior to the SPMC living at S-EL2. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Icf46eb8a391dd3ddd2ee6aff8581a2f1c8a1c274
2024-02-07Merge changes from topic "ja/spm_rme" into integrationOlivier Deprez
* changes: docs: change FVP argument in RME configuration feat(fvp): added calls to unprotect/protect memory
2024-02-06build: use toolchain identifiers in conditionsChris Kay
The toolchain refactor change introduces the `${toolchain}-${tool}-id` variables, which provide identifiers for all of the toolchain tools used by the build system. This change replaces the various conditions that are in use to identify these tools based on the path with a standard set of comparisons against these new identifier variables. Change-Id: Ib60e592359fa6e415c19a012e68d660f87436ca7 Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-02-06build: use new toolchain variables for toolsChris Kay
This change migrates the values of `CC`, `CPP`, `AS` and other toolchain variables to the new `$(toolchain)-$(tool)` variables, which were introduced by the toolchain refactor patch. These variables should be equivalent to the values that they're replacing. Change-Id: I644fe4ce82ef1894bed129ddb4b6ab94fb04985d Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-02-06feat(fvp): added calls to unprotect/protect memoryJ-Alves
Added SiP calls to FVP platform to protect/unprotect a memory range. These leverage rme features to change the PAS of a given memory range from non-secure to secure. The mentioned call is leveraged by the SPMC in the memory sharing flow, when memory is shared from the normal world onto the secure world. More details in the SPM related patches. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Iaf15d8603a549d247ffb1fc14c16bfb94d0e178a
2024-02-05fix(cpus): workaround for Cortex-A715 erratum 2561034Bipin Ravi
Cortex-A715 erratum 2561034 is a Cat B erratum that applies to revision r1p0 and is fixed in r1p1. The workaround is to set bit[26] in CPUACTLR2_EL1. Setting this bit is not expected to have a significant performance impact. SDEN documentation: https://developer.arm.com/documentation/SDEN2148827/latest Change-Id: I377f250a2994b6ced3ac7d93f947af6ceb690d49 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2024-01-25fix(cpus): workaround for Cortex X3 erratum 2641945Bipin Ravi
Cortex X3 erratum 2641945 is a Cat B erratum that applies to all revisions <= r1p0 and is fixed in r1p1. The workaround is to disable the affected L1 data cache prefetcher by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance penalty of ~1%. Contact Arm for an alternate workaround that impacts power. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2024-01-24Merge "refactor(mte): deprecate CTX_INCLUDE_MTE_REGS" into integrationManish V Badarkhe
2024-01-23Merge changes from topic "errata" into integrationLauren Wehrmeister
* changes: fix(cpus): workaround for Cortex-A78C erratum 2683027 fix(cpus): workaround for Cortex-X3 erratum 2266875 fix(cpus): workaround for Cortex-X3 erratum 2302506
2024-01-23refactor(mte): deprecate CTX_INCLUDE_MTE_REGSGovindraj Raja
Currently CTX_INCLUDE_MTE_REGS is used for dual purpose, to enable allocation tags register and to context save and restore them and also to check if mte feature is available. To make it more meaningful, remove CTX_INCLUDE_MTE_REGS and introduce FEAT_MTE. This would enable allocation tags register when FEAT_MTE is enabled and also supported from platform. Also arch features can be conditionally enabled disabled based on arch version from `make_helpers/arch_features.mk` Change-Id: Ibdd2d43874634ad7ddff93c7edad6044ae1631ed Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-01-18feat(spmd): add FFA_MSG_SEND_DIR_RESP2Kathleen Capella
Add handling for FF-A 1.2 FFA_MSG_SEND_DIR_RESP2 interface. Signed-off-by: Kathleen Capella <kathleen.capella@arm.com> Change-Id: Ibd0546ecd71d004804e6e18b27a4728a21259fa0
2024-01-18feat(spmd): add FFA_MSG_SEND_DIR_REQ2Kathleen Capella
Add handling for FF-A 1.2 FFA_MSG_SEND_DIR_REQ2 interface. Handler validates security states of sender/receiver pairs and forwards the call to other world if necessary. Signed-off-by: Kathleen Capella <kathleen.capella@arm.com> Change-Id: I02a60362d8d9a50fcc0b6a84753cba274ba5eb1b
2024-01-17fix(cpus): workaround for Cortex-A78C erratum 2683027Bipin Ravi
Cortex-A78C erratum 2683027 is a cat B erratum that applies to revisions r0p1 - r0p2 and is still open. The workaround is to execute a specific code sequence in EL3 during reset. SDEN can be found here: https://developer.arm.com/documentation/SDEN-2004089/latest Change-Id: I2bf9e675f48b62b4cd203100f7df40f4846aafa8 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2024-01-17fix(cpus): workaround for Cortex-X3 erratum 2266875Bipin Ravi
Cortex-X3 erratum 2266875 is a Cat B erratum that applies to all revisions <= r1p0 and is fixed in r1p1. The workaround is to set CPUACTLR_EL1[22]=1 which will cause the CFP instruction to invalidate all branch predictor resources regardless of context. SDEN Documentation: https://developer.arm.com/documentation/2055130/latest Change-Id: I9c610777e222f57f520d223bb03fc5ad05af1077 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2024-01-17fix(cpus): workaround for Cortex-X3 erratum 2302506Bipin Ravi
Cortex-X3 erratum 2302506 is a cat B erratum that applies to revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidation to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN can be found here: https://developer.arm.com/documentation/2055130/latest Change-Id: I048b830867915b88afa36582c6da05734a56d22a Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2024-01-16feat(el3-spmc): add support for FFA_CONSOLE_LOGShruti Gupta
Add support for FFA_CONSOLE_LOG in EL3 SPMC, Disallow forwarding FFA_CONSOLE_LOG across worlds. Add support for FFA_CONSOLE_LOG in FFA_FEATURES. Input parameters: w0/x0 - FFA_CONSOLE_LOG_32/64 w1/x1 - Character count w2/x2-w7/x7 - 24 or 48 characters depending upon whether a SMC32 or SMC64 FID was used. Output parameters in case of success: w0/x0 - FFA_SUCCESS Output parameters in case of error: w0/x0 - FFA_ERROR w2/x2 - NOT_SUPPORTED: ABI is not implemented INVALID_PARAMETERS: Parameters are incorrectly encoded Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: I004c043729e77d1b9aa396c42d25c73d9268169a
2024-01-04fix(rmmd): avoid TRP when external RMM is definedRohit Mathew
The Test Realm Package (TRP) is a small payload that runs at R-EL2 if an external RMM image path is not provided. Currently, the TRP makefile is included if RME is enabled, regardless of whether an external RMM image path is defined or not. This fix ensures that TRP is included only when an external RMM path is not defined. Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Change-Id: I3cc3d2a636e65071e45c5c82cc125290887ffc09
2023-12-21Merge "fix(cpus): workaround for Cortex X3 erratum 2743088" into integrationBipin Ravi
2023-12-20fix(cpus): workaround for Cortex X3 erratum 2743088Harrison Mutai
Cortex X3 erratum 2743088 is a Cat B erratum that applies to all revisions <= r1p1 and is fixed in r1p2. The workaround is to add a DSB instruction before the ISB of the powerdown code sequence specified in the TRM. SDEN documentation: https://developer.arm.com/documentation/2055130 Change-Id: I2c8577e3ca0781af8b1c3912e577d3bd77f92709 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-12-19refactor(cm): reset the cptr_el3 before perworld context setupJayanth Dodderi Chidanand
Currently, the registers which are maintained per-world, does not take into account the reset value while configuring the context for the respective world. This leads to an issue, wherein the register retains the same value across world switch, which is an error. This patch addresses this problem, by configuring the register (cptr_el3) precisely according to the world, the cpu is in execution via resetting it before initializing the world specific context. Change-Id: I592d82af373155fca67eed109c199341c305f0b9 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2023-12-18fix(cpus): workaround for Cortex-A520 erratum 2858100Arvind Ram Prakash
Cortex-A520 erratum 2858100 is a Cat B erratum that applies to all revisions <=r0p1 and is still open. The workaround is to set bit[29] of CPUACTLR_EL1. SDEN Documentation: https://developer.arm.com/documentation/SDEN-2444153/latest Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I5a07163f919352583b03328abd5659bf7b268677
2023-12-18fix(errata): add Cortex-A520 definitionsArvind Ram Prakash
Include the missing Cortex-A520 header. Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I45153a1aa2d6dace38650268a32106f5201f48bd
2023-12-13Merge changes from topic "sm/erratum" into integrationBipin Ravi
* changes: fix(cpus): workaround for Cortex-A520 erratum 2630792 fix(cpus): workaround for Cortex-X2 erratum 2778471 fix(cpus): workaround for Cortex-A710 erratum 2778471
2023-12-12fix(cpus): workaround for Cortex-A520 erratum 2630792Sona Mathew
Cortex-A520 erratum is a Cat B erratum that applies to revisions r0p0 and r0p1 and is still open. The workaround is to set CPUACTLR_EL1[38] to 1. SDEN Documentation: https://developer.arm.com/documentation/SDEN-2444153/latest Change-Id: Idb6f32f680ee1378a57c2d2f809ea847fffe5910 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-12-12fix(cpus): workaround for Cortex-X2 erratum 2778471Sona Mathew
Cortex-X2 erratum 2778471 is a Cat B erratum that applies to revisions r0p1, r1p0, r2p0 and r2p1 and is still open. The workaround is to set CPUACTLR3_EL1[47] to 1. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775100/latest Change-Id: Ia95f0e276482283bf50e06c58c2bc5faab3f62c6 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-12-12fix(cpus): workaround for Cortex-A710 erratum 2778471Sona Mathew
Cortex-A710 erratum 2778471 is a Cat B erratum that applies to revisions r0p1, r1p0, r2p0 and r2p1 and is still open. The workaround is to set CPUACTLR3_EL1[47] to 1. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest Change-Id: Id3bb4a2673e41ff237682e46784d37752daf2f83 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2023-12-07feat(el3-spmc): add support to handle power mgmt calls for s-el0 spNishant Sharma
Add support to setup S-EL0 SP context during power management power on procedure. In case of power on, initialise the context data structure for the secure world on the current CPU. The S-EL0 SP does not support power message. Add the check to make sure that it does not subscribe to any power messages. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Nishant Sharma <nishant.sharma@arm.com> Change-Id: Ic9cf98cd15b6ee5d86d071a52bc0973677049df3
2023-11-30Merge changes from topic "ns/spmc_at_el3" into integrationManish Pandey
* changes: feat(rdn2): add dts for secure partition feat(el3-spmc): synchronize access to the s-el0 sp context feat(el3-spmc): add support to map S-EL0 SP device regions feat(el3-spmc): add support to map S-EL0 SP memory regions feat(el3-spmc): add support for FFA_MEM_PERM_GET and SET ABIs feat(el3-spmc): add support to setup S-EL0 context
2023-11-29Merge "fix(cpus): workaround for Neoverse V2 erratum 2618597" into integrationLauren Wehrmeister
2023-11-29fix(cpus): workaround for Neoverse V2 erratum 2618597Bipin Ravi
Neoverse V2 erratum 2618597 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. The workaround is to disable the use of the Full Retention power mode in the core (setting WFI_RET_CTRL and WFE_RET_CTRL in IMP_CPUPWRCTLR_EL1 to 0b000). SDEN can be found here: https://developer.arm.com/documentation/SDEN-2332927/latest Change-Id: I23a81275d1e40cae39e6897093d6cdd3e11c08ea Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>