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Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Cortex-A715 in the errata ABI files.
Fixed this by adding it to the Cortex-X3 list.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on arm/non-arm interconnect IP flag. The ABI helps assist the
Kernel in the process of mitigation for the following errata:
Cortex-A715: erratum 2701951
Neoverse V2: erratum 2719103
Cortex-A710: erratum 2701952
Cortex-X2: erratum 2701952
Neoverse N2: erratum 2728475
Neoverse V1: erratum 2701953
Cortex-A78: erratum 2712571
Cortex-A78AE: erratum 2712574
Cortex-A78C: erratum 2712575
Change-Id: Ie86b7212d731a79e2a0c07649e69234e733cd78d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structures created by the errata framework.
Change-Id: I1a60d3e4f116b6254fb45426f43ff1b21771af89
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
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This enables the usage of speaking defines instead of magic numbers:
CSU_SA(CSU_SA_SDMA1, 1, LOCKED)
becomes:
CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED)
Change-Id: Idcabcda677bf7840084a2ea66d321b50aa0b2b20
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
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This ports the missing enum defines for the central security unit found
in NXPs i.MX8M socs. The defines itself where imported from NXP's
downstream version of the trusted-firmware-a version 2.8[1].
[1]: https://github.com/nxp-imx/imx-atf/commit/0c52279fc4
Change-Id: Iad0c5d3733e9d29ead86334ba4bc5ce915018142
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
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The csu found in the imx8mp has 3 csu_sa registers, before the fix not
all of them could be addressed.
The defines itself was imported from NXP's downstream version of the
trusted-firmware-a version 2.8[1].
[1]: https://github.com/nxp-imx/imx-atf/commit/0c52279fc4
Change-Id: Ia3653118bba82df9244c819a5c5f37bdc4e89c49
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
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* changes:
refactor(allwinner): console runtime switch on bl31 exit
refactor(arm): console runtime switch on bl31 exit
refactor(console): flush before console_switch_state
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* changes:
build(fpga): correctly handle gcc as linker for LTO
fix(build): enforce single partition for LTO build
fix(rockchip): add support for building with LTO enabled
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Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.
This patch only affects the Allwinner platform.
Change-Id: I15b4a459a280822a01c60e3b0c856b530db6efab
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
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Any BL31 setup and Runtime initialization within BL31 is still part of
the BOOT process. As such, the console flush and switch must be the
last calls before BL31 exit. Flush the console print buffer before
switching to runtime. This is so that there is no lingering chars in
the print buffer when we move to the runtime console.
This patch adds console flush before switching to runtime in
bl31_plat_runtime_setup() function (before BL31 exits). The plan is to
move flush and switch calls to bl31_main before BL31 exits, until then
console_flush() in bl31_main.c has been left as is.
This patch affects the Arm platform only.
Change-Id: I4d367b9e9640686ac15246ad24318ae4685c12c5
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
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TF-A plans to move console_flush() and
console_switch_state(CONSOLE_FLAG_RUNTIME) to the end of bl31_main()
before BL31 exits.
Add console_flush() in the generic implementation of
bl31_plat_runtime_setup() call so that platforms can implement or
follow the generic pattern to test this implementation before
console_flush() and console_switch_state() move to bl31_main().
This patch affects the generic implementation of
bl31_plat_runtime_setup()
Change-Id: I92b4176022bfb84558dec5a83386e8ecef49516a
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
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* changes:
style(fwu): change the metadata fields to align with specification
style(partition): use GUID values for GPT partition fields
feat(st): add logic to boot the platform from an alternate bank
feat(st): add a function to clear the FWU trial state counter
feat(fwu): add a function to obtain an alternate FWU bank to boot
feat(fwu): add some sanity checks for the FWU metadata
feat(fwu): modify the check for getting the FWU bank's state
feat(st): get the state of the active bank directly
feat(fwu): add a config flag for including image info in the FWU metadata
feat(fwu): migrate FWU metadata structure to version 2
feat(fwu): document the config flag for including image info in the FWU metadata
feat(fwu): update the URL links for the FWU specification
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* changes:
refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd
refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
refactor(sgi): move apis and types to "nrd" prefix
refactor(sgi): replace build-option prefix to "NRD"
refactor(sgi): move neoverse_rd out of css
refactor(sgi): move from "sgi" to "neoverse_rd"
feat(sgi): remove unused SGI_PLAT build-option
fix(sgi): align to misra rule for braces
feat(rde1edge): remove support for RD-E1-Edge
fix(rdn2): populate TOS_CONFIG only when SPMC_AT_EL3 is enabled
fix(board): update spi_id max for sgi multichip platforms
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* changes:
feat(smmu): separate out smmuv3_security_init from smmuv3_init
feat(smmu): fix to perform INV_ALL before enabling GPC
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* changes:
docs(maintainers): add the maintainers for imx8ulp
docs(imx8ulp): add imx8ulp platform
fix(imx8ulp): increase the mmap region num
feat(imx8ulp): adjust the dram mapped region
feat(imx8ulp): ddrc switch auto low power and software interface
feat(imx8ulp): add some delay before cmc1 access
feat(imx8ulp): add a flag check for the ddr status
fix(imx8ulp): add sw workaround for csi/hotplug test hang
feat(imx8ulp): adjust the voltage when sys dvfs enabled
feat(imx8ulp): enable the DDR frequency scaling support
fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only
feat(imx8ulp): update XRDC for ELE to access DDR with CA35 DID
feat(imx8ulp): add memory region policy
feat(imx8ulp): protect TEE region for secure access only
feat(imx8ulp): add trusty support
feat(imx8ulp): add OPTEE support
feat(imx8ulp): update the upower config for power optimization
feat(imx8ulp): allow RTD to reset APD through MU
feat(imx8ulp): not power off LPAV PD when LPAV owner is RTD
feat(imx8ulp): add system power off support
feat(imx8ulp): add APD power down mode(PD) support in system suspend
feat(imx8ulp): add the basic support for idle & system suspned
feat(imx8ulp): enable 512KB cache after resume on imx8ulp
feat(imx8ulp): add the initial XRDC support
feat(imx8ulp): allocated caam did for the non secure world
feat(imx8ulp): add i.MX8ULP basic support
build(changelog): add new scopes for nxp imx8ulp platform
feat(scmi): add scmi sensor support
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Change the names of some FWU metadata structure members to have them
align with the wording used in the corresponding specification. Use
the GUID type instead of UUID as the fields described in the
specification are GUIDs. Make corresponding changes to the code that
accesses these fields. No functional changes are introduced by the
patch.
Change-Id: Id3544ed1633811b0eeee2bf99477f9b7e6667044
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
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In a few scenarios, there is a need to boot the platform from an
alernate bank which is not the active bank. Call the API
fwu_get_alernate_boot_bank() to select an alternate bank to boot the
platform from. Calling this API function might be required in a couple
of cases. One, in the unlikely scenario of the active bank being in an
invalid state, or if the number of times the platform boots in trial
state exceeds a pre-set count.
Also add a debug print that indicates the bank that
the platform is booting from.
Change-Id: I688406540e64d1719af8d5c121821f5bb6335c06
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
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Add an API stm32_clear_fwu_trial_boot_cnt() function to clear the
trial state counter. This is called in the corner case scenario when
the active index is in an Invalid state, thus needing a reset of the
trial state counter.
Change-Id: I2980135da88d0d947c222655c7958b51eb572d69
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
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With version 2 of the FWU metadata structure, the state that a bank is
in can be obtained from the bank_state field in the top level
structure. Read the state of the active bank by referencing this field
directly, instead of making an API call.
Change-Id: Ib22c56acbe172923b1323c544801ded81f1598ec
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
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Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.
This patch affects the QEMU platform only.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I6188d73dd3f3c97f41bb25de543f8c46a972adf0
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Datastore symbol used by EL3 SPMC is not relocated at
boot time when using ENABLE_PIE=1.
Use linker script markers instead of symbol.
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: If22d2fc8deacc74c73d7dc51bb70093935d9fa2b
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* changes:
refactor(tc): reorder config variable defines
refactor(tc): move DTB to start of DRAM
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integration
* changes:
refactor(tc): correlate secure world addresses with platform_def
feat(tc): add memory node in the device tree
feat(tc): pass the DTB address to BL33 in R0
feat(tc): add arm_ffa node in dts
chore(tc): add dummy entropy to speed up the Linux boot
feat(tc): choose the DPU address and irq based on the target
feat(tc): add SCMI power domain and IOMMU toggles
refactor(tc): move the FVP RoS to a separate file
feat(tc): factor in FVP/FPGA differences
feat(tc): introduce an FPGA subvariant and TC3 CPUs
feat(tc): add TC3 platform definitions
refactor(tc): sanitise the device tree
feat(tc): add PMU entry
feat(tc): allow booting from DRAM
chore(tc): remove unused hdlcd
feat(tc): add firmware update secure partition
feat(tc): add spmc manifest with trusty sp
refactor(tc): unify all the spmc manifests
feat(arm): add trusty_sp_fw_config build option
fix(tc): do not enable MPMM and Aux AMU counters always
fix(tc): correct interrupts
feat(tc): interrupt numbers for `smmu_700`
feat(tc): enable gpu/dpu scmi power domain and also gpu perf domain
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the mmap region num is not enough for the mmap regions,
so increase it, increase the xlat_table num too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2a2515b291e96cc12398a2c2c526351342811fff
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below commit mapped 16 MB memory from the start of DRAM(0x80000000),
which may have conflict with the shared memory used by Trusty OS:
LF-8819: plat: imx8ulp: ddrc switch auto low power and software interface
change the mapped memory to 'vdev0buffer' reserved memory (0x8ff00000)
to avoid memory conflict. This commit also bumps the XTLB tables
to avoid mapping failure.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Change-Id: I1a7af958af47e3fc9955d0a80d1649971e843eab
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Enable switch between DDRC Auto low power and software/hardware
control modes DDRC Auto low-power mode is used when system is
active, software/hardware control mode is used when going into
suspend. Enable switching between Auto mode and SW/HW mode in
enter/exit retention routines.
Set LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 Max setting to allow
LPDDR_EN_CLKGATE reload LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 to
exit retention mode
Signed-off-by: Pascal Mareau <pascal.mareau@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Hongting Ting <hongting.dong@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3c4b6f7bc6ca02649ff27cd3d9a0c50dab3a3ad0
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When resume from APD sleep mode, need to add a small delay
before accessing the CMC1 register.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ic8acdf58a3bf82b1791e7ae7f173f8c94c56b49d
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for some user case, the ddr may need to be controlled
by RTD side to save power, when APD resume from low
power mode, it should wait ddr is ready for access.
currently we use a GPR in SIM_RTD_SEC as a flag to
indicate when the DDR is for access, non-zero value
means the DDR can be access from APD.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I6fb0cc17a040d803a597304620202423f646f294
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When doing CSI stress test after cpu hotplug, sometimes, system
will hang in CSI test. After some debug, we find that if slow
down the APD NIC frequency before power on the offline CPU,
the issue is gone. For now, just add such SW workaround.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I39a49efc382fbebf46e1ff15c93d506bd5f6bec1
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When system level DVFS is enabled, voltage can be changed to
optimize the power consumption.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Idfa0e637402078f3daf6e7c4ea1abb9af7675494
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Enable the DDR frequency scaling support on i.MX8ULP.
Normally, the freq_index define is as below:
0: boot frequency;
1: low frequency(PLL bypassed);
2. high frequency(PLL ON).
Currently, DDR DFS only do frequency switching between
Low freq and high freq.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I3acd8bdf75e2dd6dff645b9f597dcfc0a756c428
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After resume from APD power down, XRDC is initialized by S400 but
the PAC2 and MSC0-2 are not configured, so only DBD owner can access
the resources.
We have to move GPIO restore after TFA XRDC reinit and configure
PDAC for PCC5 before enabling eDMA2 MP clock
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I82748de080151b0bdf1cace092b7892a1e402a27
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In order to isolate application memories, ELE FW introduces
a new policy which mimics the requestor attributes (DID, TZ).
So ELE configures SCM to access to external memory with CA35 DID
when CA35 request something from ELE.
Because ELE accesses DDR through NIC_LPAV, the XRDC MRC6 must be
configured for CA35 DID 7 to authorize the access.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I9e91a1b2798e8d15127d1bfa9aa0ffc612fd8981
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set the memory region policy for secure heap(0xA9600000 ~ 0xAF600000),
it can only be RWX by secure master. At the same time, restrict G2D
and DCnano(domain 3) to write non-secure memory when they are set as
secure master.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If53e130eaeb1ac867ee56e4af04e3be29dec9857
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Using XRDC MRC4/5/6 to restrict the secure access for TEE DDR
memory to protect TEE.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic161df6a98ded23b9a74d552717fc5dcc1ee2ae8
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Support trusty on imx8ulp.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I7ada2557023e271a721d50bfe7fd20b5f01cb128
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Add opteed support for imx8ulp.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Iddf6f164b7146332e99de42fcbbf9c892eb1d994
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Enable the AFBB by default for active mode when APD side wakeup
from low power mode to align with the first time boot up.
Update the power mode configs to force shutdown all the
necessary power switches to optimize the power consumption.
To reduce the pad power consumption, put all the pad into
OFF mode to save more power. the PTD's compensation should
also be disabled in low power mode to save more power.
when APD enters PD mode, the LDO1(used by DDR) can be shutdown
to save power. when APD enters DPD mode, the BUCK3(supply for
APD/LPAV) can be shutdown to save power.
In single boot mode, When APD enters DPD mode, buck3 will
shutdown, LDO1 should be off to save more power as the DDR
controller has lost power.
In dualboot mode, the LPAV is owned by RTD side. When APD enters
low power mode, APD side should not config those PMIC regulators
that used by the resource owned by RTD side.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ie5e9b428f85345b81744313a8fb93bfc27e0dd71
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Clear HRM bit in MU0_B CCR0 register to allow RTD to reset APD.
The action needs at both ATF init and APD resume.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2475e34b13f57818580a478ab567bfb9fc6cf174
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Upower will check the LPAV ownership when power off the SRAM or PS.
if the LPAV owner is not APD, then the power off will return failure.
Add similar checking in SCMI PD driver to skip the power off to avoid
failure print causing suspend/resume not work.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I9dc657c2277129ac90a792232f734c08fca5f997
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On i.MX8ULP, we need to use the APD deep power down(DPD) mode
to support the system power off function. when APD enter
power off mode, only the RTD can re-kick it and boot from ROM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ifb42db0a7cf87b932160c59b47eca4d0f08f8cdf
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The APD can be put into PD mode when linux suspend(mem). This patch
add the support for it. As the whole AP domain's context will be lost,
so we must save the necessary HW module states before entering PD mode,
and we need to restore those contexts when system wake up. Fot details
about which HW module's state will be lost, please refer to the RM.
When APD enter PD mode, only the wakeup event connected to the WUU
can wakeup APD successfully. The upower wakeup source is used to
wakeup APD by RTD due to the factor that the MU between A core & M
core is not connected into WUU to generate wakeup event.
as the SRAM0 will be power down when APD enters PD mode, so we
need to re-init the scmi channels(resides in the SRAM0). otherwise
the SCMI can NOT work anymore.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I44b0cdc8397e5d6a82081ea6746542e9fa4b9fc1
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Add basic support for the cpuidle(cluster retention) and system
suspend support using the HW sleep mode.
When system enter low power mode after doing reboot twice, APD
will be failed to exit from low power mode successfully. it is
because that after secondary reboot, upower will modify the default
power switch config, then DDR will be off wrongly. So config the
low power mode info explicitly before APD entering any low power
mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ib68bfdfd4b925541e343aef4a5296a542451f86b
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The L2 cache size config will be reset to default 256KB,
So we need to switch to 512KB after resume to make sure
the L2 cache size is same as before suspend.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ifd9b3e01829fbd7b1ae4ba00611359330f1a4f83
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Add the initial xRDC support on i.MX8ULP.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I93ea8e2cebb049e6f20e71cfe50c7583a3228f38
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JR1, JR2 and JR3 are available for use by the non secure
world. Setup the A35 core DID for these job rings.
Signed-off-by: Varun Sethi <v.sethi@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If64d4ce11ebff49a2405d8b561b344fcd7b2614f
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Add the basic support for i.MX8ULP.
The i.MX 8ULP family of processors features NXP’s advanced
implementation of the dual Arm Cortex-A35 cores alongside
an Arm Cortex-M33. This combined architecture enables the
device to run a rich operating system (such as Linux) on
the Cortex-A35 core and an RTOS (such as FreeRTOS) on the
Cortex-M33 core. It also includes a Cadence Tensilica Fusion
DSP for low-power audio and a HiFi4 DSP for advanced audio
and machine learning applications.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36
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They are very scattered, hard to read, and especially hard to track
down. As a result some are duplicate and some are overridden in the
downstream as it's simpler.
Put all variables at the top of the platform makefile. Also drop setting
variables that don't change from their default values
(CTX_INCLUDE_EL2_REGS, ARCH, ENABLE_FEAT_RAS, SDEI_SUPPORT,
EL3_EXCEPTION_HANDLING, HANDLE_EA_EL3_FIRST_NS, ENABLE_SPE_FOR_NS).
While we're at it, add some variables that are necessary. SPMD
requires MTE registers to be saved, BRANCH_PROTECTION, as well as
running at SEL2. All of our CPUs are Armv8.7 compliant so we can have
ARM_ARCH_MINOR=7 (and drop ENABLE_TRF_FOR_NS which it includes).
Finally, drop the override directives as there's no reason to prohibit
experimentation (even if incorrect).
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I6ac596934952aab8abf5d4db5220e13a4941a10c
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