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2023-04-26feat(tegra): implement 'pwr_domain_off_early' handlerVarun Wadekar
This patch implements the pwr_domain_off_early handler for Tegra platforms. Powering off the boot core on some Tegra platforms is not allowed and the SOC specific helper functions for Tegra194, Tegra210 and Tegra186 implement this restriction. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I9d06e0eee12314764adb0422e023a5bec6ed9c1e
2020-08-31Tegra186: sanity check power state typeVarun Wadekar
This patch sanity checks the power state type before use, from the platform's PSCI handler. Verified with TFTF Standard Test Suite. Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-18Tegra186: system resume from TZSRAM memoryVarun Wadekar
TZSRAM loses power during System suspend, so the entire contents are copied to TZDRAM before Sysem Suspend entry. The warmboot code verifies and restores the contents to TZSRAM during System Resume. This patch removes the code that sets up CPU vector to point to TZSRAM during System Resume as a result. The trampoline code can also be completely removed as a result. Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-18Tegra186: disable PROGRAMMABLE_RESET_ADDRESSVarun Wadekar
This patch disables the code to program reset vector for secondary CPUs to a different entry point, than cold boot. The cold boot entry point has the ability to differentiate between a cold boot and a warm boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By reusing the same entry point, we can lock the CPU reset vector during cold boot. Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-11Tegra: smmu: remove context save sequencePritesh Raithatha
SMMU and MC registers are saved as part of the System Suspend sequence. The register list includes some NS world SMMU registers that need to be saved by NS world software instead. All that remains as a result are the MC registers. This patch moves code to MC file as a result and renames all the variables and defines to use the MC prefix instead of SMMU. The Tegra186 and Tegra194 platform ports are updated to provide the MC context register list to the parent driver. The memory required for context save is reduced due to removal of the SMMU registers. Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
2020-03-11Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194Varun Wadekar
This patch fixes the SE clock ID being used for Tegra186 and Tegra194 SoCs. Previous assumption, that both SoCs use the same clock ID, was incorrect. Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-03-09Tegra186: add SE support to generate SHA256 of TZRAMJeetesh Burman
The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This memory loses power when we enter System Suspend and so its contents are stored to TZDRAM, before entry. This opens up an attack vector where the TZDRAM contents might be tampered with when we are in the System Suspend mode. To mitigate this attack the SE engine calculates the hash of entire TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The WB0 code will validate the TZDRAM and match the hash with the one in PMC scratch. This patch adds driver for the SE engine, with APIs to calculate the hash and store SE SHA256 hash-result to PMC scratch registers. Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
2020-01-31Tegra: remove weakly defined PSCI platform handlersVarun Wadekar
This patch removes all the weakly defined PSCI handlers defined per-platform, to improve code coverage numbers and reduce MISRA defects. Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-02-07Tegra186: use common 'BL31_BASE' variableVarun Wadekar
This patch modfies the 'tegra_soc_pwr_domain_power_down_wfi' handler to use BL31_BASE variable, provided by bl_common.h Change-Id: I9747228d0193c1ae6999284458b9f866955a61a2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-23Tegra186: save system suspend entry marker to TZDRAMVarun Wadekar
This patch adds support to save the system suspend entry and exit markers to TZDRAM to help the trampoline code decide if the current warmboot is actually an exit from System Suspend. The Tegra186 platform handler sets the system suspend entry marker before entering SC7 state and the trampoline flips the state back to system resume, on exiting SC7. Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-23Tegra186: helper functions for CPU rst handler and SMMU ctx offsetVarun Wadekar
This patch adds a helper function to get the SMMU context's offset and uses another helper function to get the CPU trampoline offset. These helper functions are used by the System Suspend entry sequence to save the SMMU context and CPU reset handler to TZDRAM. Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-23Tegra: rename secure scratch register macrosSteven Kao
This patch renames all the secure scratch registers to reflect their usage. This is a list of all the macros being renamed: - SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_* - SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG - SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_* - SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_* - SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_* NOTE: Future SoCs will have to define these macros to keep the drivers functioning. Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987 Signed-off-by: Steven Kao <skao@nvidia.com>
2019-01-23Tegra186: sanity check target cluster during core power onVarun Wadekar
This patch sanity checks the target cluster value, during core power on, by comparing it against the maximum number of clusters supported by the platform. Reported by: Rohit Khanna <rokhanna@nvidia.com> Change-Id: Ia73ccf04bd246403de4ffff6e5c99e3b00fb98ca Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-23Tegra186: fix MISRA Rule 8.3 violationAnthony Zhou
MISRA Rule 8.3, All declarations of an object or function shall use the same names and type qualifiers. This patch removes unused function(s). Change-Id: I90865c003d46f1dc08bfb5f4fe8a327ea42a2bb7 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2019-01-18Tegra: fix defects flagged by MISRA Rule 10.3Anthony Zhou
MISRA Rule 10.3, the value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The essential type of a enum member is anonymous enum, the enum member should be casted to the right type when using it. Both UL and ULL suffix equal to uint64_t constant in compiler aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix in platform code. So in some case, cast a constant to uint32_t is necessary. Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2019-01-18Tegra186: fix defects flagged by MISRA scanAnthony Zhou
Main fixes: Remove unused type conversion Fix invalid use of function pointer [Rule 1.3] Fix variable essential type doesn't match [Rule 10.3] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I23994c9d4d6a240080933d848d2b03865acaa833 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2019-01-18Tegra186: reduce complexity for the 'get_target_pwr_state' handlerVarun Wadekar
This patch reduces the code complexity for the platform's 'get_target_pwr_state' handler, by reducing the number of 'if' conditions and adding helper functions to calculate power state for the cluster/system. Tested with 'pmccabe' Change-Id: I32fa4c814bd97f620f2003fa39f1bfceae563771 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-16Tegra186: PM: fix MISRA defects in plat_psci_handlers.cAnthony Zhou
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Fix implicit widening of composite assignment [Rule 10.6] Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2019-01-16Tegra186: remove support for Quasi System power off (SC8) stateVarun Wadekar
This patch removes support for the SC8 power state as the feature is no longer required for Tegra186 projects. Change-Id: I622a5ddcffe025b9b798801d09bbb856853befd7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-16Tegra: support to set the L2 ECC and Parity enable bitHarvey Hsieh
This patch adds capability to read the boot flag to enable L2 ECC and Parity Protection bit for the Cortex-A57 CPUs. The previous bootloader sets this flag value for the platform. * with some coverity fix: MISRA C-2012 Directive 4.6 MISRA C-2012 Rule 2.5 MISRA C-2012 Rule 10.3 MISRA C-2012 Rule 10.4 Change-Id: Id7303bbbdc290b52919356c31625847b8904b073 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-22libc: Fix all includes in codebaseAntonio Nino Diaz
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-06-14Tegra: enable 'signed-comparison' compilation warning/errorsVarun Wadekar
This patch enables the 'sign-compare' flag, to enable warning/errors for comparisons between signed/unsigned variables. The warning has been enabled for all the Tegra platforms, to start with. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-01Tegra186: calculate proper power state for cluster/system power downVarun Wadekar
Earlier, we were setting "System Suspend" as the power state for all system states. This caused incorrect system state during a cluster power down. This patch fixes this anomaly and sets the correct power state during a cluster/system power down. Change-Id: Ibd002930e0ae103e381e0a19670c3c4d057e7cb7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-20Tegra: smmu: make the context save sequence robustVarun Wadekar
This patch sanity checks the SMMU context created by the platform code. The first entry contains the size of the array; which the driver now verifies before moving on with the save. This patch also fixes an error in the calculation of the size of the context that gets copied to TZDRAM. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: PSCI: support for 64-bit TZDRAM baseSteven Kao
This patch fixes the variable width to store the TZDRAM base address used to resume from System Suspend. Change-Id: Ib67eda64b09f26fb2f427f0d624f057081473132 Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: use MSB of wake_timeKrishna Sitaraman
This patch updates wake time of the cpu to use the MSBs and zero out the LSB's. Only 24 out of 32 bits are currently passed through the PSCI interface. Previously all the LSB's were used. Change-Id: Ie2d9d1bf6e3003dd47526a124f64e6ad555d2371 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: clean CPU wake times from L2 cacheMustafa Yigit Bilgen
When entering C7, ATF disables caches and flushes the L1 cache. However, wake_time[cpu] can still remain in the L2 cache, causing later reads to it to fetch from DRAM. This will read stale values. Fix this by aligning wake_time[cpu] to cache lines, and explicitly cleaning it before disabling caches. Change-Id: Id73d095b479677595a6b3dd0abb240a1fef5f311 Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: implement `get_target_pwr_state` handlerVarun Wadekar
This patch implements the `get_target_pwr_state` handler for Tegra186 SoCs. The SoC port uses this handler to find out the cluster/system state during CPU_SUSPEND, CPU_OFF and SYSTEM_SUSPEND calls. The MCE firmware controls the power state of the CPU/CLuster/System, so we query it to get the state and act accordingly. Change-Id: I86633d8d79aec7dcb405d2301ac69910f93110fe Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-27Tegra186: reset CPU power state info while onliningVarun Wadekar
This patch resets the CPU power state info when we online any CPU. The NS world software would re-init the CPU power state after the CPU gets online anyways. This allows us to maintain proper CPU/cluster power states in the MCE firmware at all times. Change-Id: Ib24054f53df720a4f88d67b2cb5a2e036e475e14 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-23Tegra186: reset power state info during CPU_ONVarun Wadekar
This patch resets the power state info for CPUs when onlining, as we set deepest power when offlining a core but that may not be requested by non-secure sw which controls idle states. It will re-init this info from non-secure software when the core come online. Original change by Prashant Gaikwad <pgaikwad@nvidia.com> Change-Id: Id6c2fa2b821c7705aafbb561a62348c36fd3abd8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-23Tegra186: fix programming sequence for SC7/SC8 entryVarun Wadekar
This patch fixes the programming sequence for 'System Suspend' and 'Quasi power down' state entry. The device needs to update the required power state before querying the MCE firmware to see the entry to that power state is allowed. Original change by Allen Yu <alleny@nvidia.com> Change-Id: I65e03754322188af913fabf41f29d1c3595afd85 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-23Tegra186: program default core wake mask during CPU_SUSPENDVarun Wadekar
This patch programs the default CPU wake mask during CPU_SUSPEND. This reduces the CPU_SUSPEND latency as the system has to send one less SMC before issuing the actual suspend request. Original change by Krishna Sitaraman <ksitaraman@nvidia.com> Change-Id: I1f9351dde4ab30936070e9f42c2882fa691cbe46 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-23Tegra186: clear the system cstate for offline coreVarun Wadekar
This patch clears the system cstate when offlining a CPU core as we need to update the sytem cstate to SC7 only when we enter system suspend. Original change by Prashant Gaikwad <pgaikwad@nvidia.com> Change-Id: I1cff9bbab4db7d390a491c8939aea5db6c6b5c59 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-23Tegra186: save/restore BL31 context to/from TZDRAMVarun Wadekar
This patch adds support to save the BL31 state to the TZDRAM before entering system suspend. The TZRAM loses state during system suspend and so we need to copy the entire BL31 code to TZDRAM before entering the state. In order to restore the state on exiting system suspend, a new CPU reset handler is implemented which gets copied to TZDRAM during boot. TO keep things simple we use this same reset handler for booting secondary CPUs too. Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-22Tegra186: implement support for System SuspendVarun Wadekar
This patch adds the chip level support for System Suspend entry and exit. As part of the entry sequence we first query the MCE firmware to check if it is safe to enter system suspend. Once we get a green light, we save hardware block settings and enter the power state. As expected, all the hardware settings are restored once we exit the power state. Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-20Tegra186: implement quasi power off (SC8) stateVarun Wadekar
This patch adds support for the SC8 system power off state. This state keeps the sensor subsystem powered ON while powering down the remaining parts of the SoC. The CPUs and DRAM are powered down as part of this state entry and perform a cold boot when exiting SC8. Change-Id: Iba65c661a7fe077a0d696f114bab3b4595e19a0d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-20Tegra186: disable DCO operations for PSCI_CPU_OFFVarun Wadekar
This patch disables the DCO operations when we turn OFF a CPU. DCO operations are still ON when a CPU enters a power down suspend state. Change-Id: I954a800209ffcc9ab43a77f04040608cbbbd9055 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-20Tegra186: fix per-cpu wake times for CPU power statesVarun Wadekar
This patch fixes the logic used to calculate the CPU index for storing the per-cpu wake times. We use the MIDR register to calculate the CPU index now. This allows us to store values for Denver/A57 CPUs properly. Change-Id: I9df0377afd4b92bbdaea495c0df06a9780a99d09 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-20Tegra186: support for C6/C7 CPU_SUSPEND statesVarun Wadekar
This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is an idle state while C7 is a powerdown state. The MCE block takes care of the entry/exit to/from these core power states and hence we call the corresponding MCE handler to process these requests. The NS driver passes the tentative time that the core is expected to stay in this state as part of the power_state parameter, which we store in a per-cpu array and pass it to the MCE block. Change-Id: I152acb11ab93d91fb866da2129b1795843dfa39b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-20Tegra186: support for the latest platform port handlersVarun Wadekar
This patch adds support for the newer platform handler functions. Commit I6db74b020b141048b6b8c03e1bef7ed8f72fd75b merges the upstream code which has already moved all the upstream supported platforms over to these handler functions. Change-Id: I621eff038f3c0dc1b90793edcd4dd7c71b196045 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-20Tegra186: implement prepare_system_reset handlerVarun Wadekar
This patch implements the 'prepare_system_reset' handler to issue the 'system reset' command to the MCE. Change-Id: I83d8d0b4167aac5963d640fe77d5754dc7ef05b1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-20Tegra186: implement CPU_OFF handlerVarun Wadekar
This patch implements the CPU_OFF handler for powering down a CPU using the MCE driver. Change-Id: I8d455005d0b547cc61cc7778bfe9eb84b7e5480c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-20Tegra186: implement prepare_system_off handlerVarun Wadekar
This patch issues the 'System Off' ARI to power off the entire system from the 'prepare_system_off' handler. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-20Tegra186: power on/off secondary CPUsVarun Wadekar
This patch add code to power on/off the secondary CPUs on the Tegra186 chip. The MCE block is the actual hardware that takes care of the power on/off sequence. We pass the constructed CPU #, depending on the MIDR_IMPL field, to the MCE CPU handlers. This patch also programs the reset vector addresses to allow the CPUs to power on through the monitor and then jump to the linux world. Change-Id: Idc164586cda91c2009d66f3e09bf4464de9662db Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-20Tegra186: platform support for Tegra "T186" SoCVarun Wadekar
Tegra186 is the newest SoC in the Tegra family which consists of two CPU clusters - Denver and A57. The Denver cluster hosts two next gen Denver15 CPUs while the A57 cluster hosts four ARM Cortex-A57 CPUs. Unlike previous Tegra generations, all the six cores on this SoC would be available to the system at the same time and individual clusters can be powered down to conserve power. Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>