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2019-01-15imx: add necessary lpuart console_flush callback for debugAnson Huang
Current lpuart driver does NOT implement .console_flush callback, if debug console is enabled, the console_flush() will call the undefined .console_flush callback(NULL) for lpuart and leak to panic, this patch adds .console_flush callback to make lpuart work for debug mode. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-12-05plat: imx: Add i.MX8MQ basic supportBai Ping
i.MX8MQ is new SOC of NXP's i.MX8M family based on A53. It can provide industry-leading audio, voice and video processing for applications that scale from consumer home audio to industrial building automation and mobile computers this patchset add the basic supoort to boot up the 4 X A53. more feature will be added later. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-08Standardise header guards across codebaseAntonio Nino Diaz
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-25Merge pull request #1636 from antonio-nino-diaz-arm/an/consoleAntonio Niño Díaz
Deprecate weak crash console functions
2018-10-25Add plat_crash_console_flush to platforms without itAntonio Nino Diaz
Even though at this point plat_crash_console_flush is optional, it will stop being optional in a following patch. The console driver of warp7 doesn't support flush, so the implementation is a placeholder. TI had ``plat_crash_console_init`` and ``plat_crash_console_putc``, but they weren't global so they weren't actually used. Also, they were calling the wrong functions. imx8_helpers.S only has placeholders for all of the functions. Change-Id: I8d17bbf37c7dad74e134c61ceb92acb9af497718 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-19Multi-console: Deprecate the `finish_console_register` macroSoby Mathew
The `finish_console_register` macro is used by the multi console framework to register the `console_t` driver callbacks. It relied on weak references to the `ldr` instruction to populate 0 to the callback in case the driver has not defined the appropriate function. Use of `ldr` instruction to load absolute address to a reference makes the binary position dependant. These instructions should be replaced with adrp/adr instruction for position independant executable(PIE). But adrp/adr instructions don't work well with weak references as described in GNU ld bugzilla issue 22589. This patch defines a new version of `finish_console_register` macro which can spcify which driver callbacks are valid and deprecates the old one. If any of the argument is not specified, then the macro populates 0 for that callback. Hence the functionality of the previous deprecated macro is preserved. The USE_FINISH_CONSOLE_REG_2 define is used to select the new variant of the macro and will be removed once the deprecated variant is removed. All the upstream console drivers have been migrated to use the new macro in this patch. NOTE: Platforms be aware that the new variant of the `finish_console_register` should be used and the old variant is deprecated. Change-Id: Ia6a67aaf2aa3ba93932992d683587bbd0ad25259 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-09-28imx8qm: imx8qx: Migrate to new interfacesAntonio Nino Diaz
- Migrate to new GIC interfaces. - Migrate to bl31_early_platform_setup2(). - Remove references to removed build options. Change-Id: Ia7c63f75325ea4b41e32a9de3f01b0007d0ae210 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-04imx: imx_wdog: Add code to initialize the wdog blockBryan O'Donoghue
The watchdog block on the IMX is mercifully simple. This patch maps the various registers and bits associated with the block. We are mostly only really interested in the power-down-enable (PDE) bits in the block for the purposes of ATF. The i.MX7 Solo Applications Processor Reference Manual details the PDE bit as follows: "Power Down Enable bit. Reset value of this bit is 1, which means the power down counter inside the WDOG is enabled after reset. The software must write 0 to this bit to disable the counter within 16 seconds of reset de-assertion. Once disabled this counter cannot be enabled again. See Power-down counter event for operation of this counter." This patch does that zero write in-lieu of later phases in the boot no-longer have the necessary permissions to rewrite the PDE bit directly. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_caam: Add code to initialize the CAAM job-rings to NS-worldBryan O'Donoghue
This patch defines the most basic part of the CAAM and the only piece of the CAAM silicon we are really interested in, in ATF, the CAAM control structure. The CAAM itself is a huge address space of some 32k, way out of scope for the purpose we have in ATF. This patch adds a simple CAAM init function that assigns ownership of the CAAM job-rings to the non-secure MID with the ownership bit set to non-secure. This will allow later logic in the boot process such as OPTEE, u-boot and Linux to assign job-rings as appropriate, restricting if necessary but leaving open the main functionality of the CAAM to the Linux NS runtime. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_hab: Define a HAB header fileBryan O'Donoghue
The High Assurance Boot or HAB is an on-chip method of providing a root-of-trust from the reset vector to subsequent stages in the bootup flow of the Cortex-A7 on the i.MX series of processors. This patch adds a simple header file with pointer offsets of the provided set of HAH API callbacks in the BootROM. The relative offset of the function pointers is a constant and known quantum, a software-contract between NXP and an implementation which is defined in the NXP HAB documentation. All we need is the correct base offset and then we can map the set of function pointers relative to that offset. imx_hab_arch.h provides the correct offset and the imx_hab.h hooks the offset to the pre-determined callbacks. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
2018-09-04imx: imx_snvs: Add an SNVS core functionalityBryan O'Donoghue
This patch adds snvs.c with a imx_snvs_init() function. imx_snvs_init() sets up permissions of the RTC via the SNVS HPCOMR. During previous work with OPTEE on the i.MX7 part we discovered that prior to switching from secure-world to normal-world it is required to apply more permissive permissions than are defaulted to in order for Linux to be able to access the RTC and CAAM functionality in general. This patch pertains to fixing the RTC permissions by way of the HPCOMR.NPSWA_EN bit. Once set non-privileged code aka Linux-kernel code has permissions to access the SNVS where the RTC resides. Perform that permissions fix in imx_snvs_init() now, with a later patch making the call from our platform setup code. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_snvs: Define a SNVS header and memory mapBryan O'Donoghue
This commit defines two things. - The basic SNVS memory map. At the moment that is total overkill for the permission bits we need to set inside the SNVS but, for the sake of completeness define the whole SNVS area as a struct. - The bits of the HPCOMR register A permission fix will need to be applied to the SNVS block prior to switching on TrustZone. All we need to do is waggle a bit in the HPCOMR register. To do that waggle we first need to define the bits of the HPCOMR register. - A imx_snvs_init() function definition Declare the snvs_init() function so that it can be called from our platform setup code. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_csu: Add a simple CSU layerBryan O'Donoghue
- Add a header to define imx_csu_init(). - Defines the Central Security Unit's Config Security Level permission bits. - Define CSU_CSL_OPEN_ACCESS permission bitmask - Run a loop to setup peripheral CSU permissions Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_aips: Add initial AIPS supportBryan O'Donoghue
This patch adds an initial AHB-to-IP TrustZone (AIPS-TZ) initialization routine. Setting up the AIPSTZ controller is required to inform the SoC interconnect fabric which bus-masters can read/write and if the read/writes are buffered. For our purposes the initial configuration is for everything to be open. We can lock-down later on as necessary. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_io_mux: Define an IO-mux layerBryan O'Donoghue
This patch defines: - The full range of IO-mux register offsets relative to the base address of the IO-mux block base address. - The bits for muxing the UART1 TX/RX lines. - The bits for muxing the UART6 TX/RX lines. - The pad control pad bits for the UART Two functions are provided to configure pad muxes: - void io_muxc_set_pad_alt_function(pad_mux_offset, alt_function) Takes a pad_mux_offset and sets the alt_function bit-mask supplied. This will have the effect of switching the pad into one of its defined peripheral functions. These peripheral function modes are defined in the NXP documentation and need to be referred to in order to correctly configure a new alternative-function. - void io_muxc_set_pad_features(pad_feature_offset, pad_features) Takes a pad_feature_offset and applies a pad_features bit-mask to the indicated pad. This function allows the setting of PAD drive-strength, pull-up values, hysteresis glitch filters and slew-rate settings. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx7: imx7_clock: usb: Initialize the USB core clocksBryan O'Donoghue
This patch initializes USB core clocks for the i.MX7. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx7: imx7_clock: wdog: Initialize the watchdog clocksBryan O'Donoghue
This patch initializes the watchdog clocks for the i.MX7. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx7: imx7_clock: uart: Add UART clock init logicBryan O'Donoghue
This patch adds an internal UART init routine that gets called from the external facing clock init function. In the first pass this call does an explicit disable of all UART clock-gates. Later changes will enable only the UART clock-gates we care about. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_clock: usb: Add USB clock APIBryan O'Donoghue
This set of patches adds a very minimal layer of USB enabling patches to clock.c. Unlike the watchdog or UART blocks the USB clocks pertain to PHYs, the main USB clock etc, not to different instances of the same IP block. As a result this patch-set takes the clock CCGR clock identifier directly rather than as an index of an instance of blocks of the same type. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_clock: wdog: Add watchdog clock APIBryan O'Donoghue
This patch adds a set of functions to enable the clock for each of the watchdog IP blocks. Unlike the MMC and UART blocks, the watchdog blocks operate off of the one root clock, only the clock-gates are enable/disabled individually. As a consequence the function clock_set_wdog_clk_root_bits() is used to set the root-slice just once for all of the watchdog blocks. Future implementations may need to change this model but for now on the one supported processor and similar NXP SoCs this model should work fine. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_clock: mmc: Add USDHC clock APIJun Nie
This patch adds an API to configure up the base USDHC clocks, taking a bit-mask of silicon specific bits as an input from a higher layer in order to direct the necessary clock source. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_clock: uart: Add UART clock APIBryan O'Donoghue
This patch adds an API to configure up the base UART clocks, taking a bit-mask of silicon specific bits as an input from a higher layer in order to direct the necessary clock source. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-09-04imx: imx_clock: Add driver and associated clock register definitionsBryan O'Donoghue
This commit: - Defines a clock stub with a conjoined header defining the clock memory map. - Defines the CCM Clock Gating Register which comes in a quadrumvirate register set to read, set, clear and toggle individual clock gates into one of four states based bitmask. 00: Domain clocks not needed 01: Domain clocks needed when in RUN 10: Domain clocks needed when in RUN and WAIT 11: Domain clocks needed all the time - Defines clock control register bits There are various quadrumvirate register blocks target-root, misc-root, post-root, pre-root in the CCM. The number of registers is huge but the four registers in each quadrumvirate block contain the same bits, so the number of bit definitions is actually quite low. - Defines clock identifiers An array of clock gates is provided in the CCM block. In order to index that array and thus enable/disable clock gates for the right components, we need to provide meaningful names to the indices. Section 5.2.5 of the i.MX7 Solo Application Processor Reference Manual Rev 0.1 provides the relevant details. - Defines target mux select bits This is a comprehensive definition of the target clock mux select bits. These bits are required to correctly select the clock source. Defining all of the bits up-front even for unused blocks in ATF means we can switch on any block we want at a later date without having to write new code in the clock-mux layer. - Defines identifier indices into root-slice array The root-slice array of control registers has a specific set of indices, which differ from the clock-gate indices. - Provides a clock gate enable/disable routine Provides a clock-gate enable/disable routine via the set/clr registers in a given clock-gate control register block. This index passed should be one of the enums associated with CCM and depending on enable/disable being passed either set or clr will be written to. The Domain0 bits are currently the only bits targeted by this write, more work may need to be done on the domain bits in subsequent patches as a result. - imx: Adds set/clr routines to clock layer Adds a set and clr routine to the clock layer. These routines allow us to access the set and clear registers of the "target" block registers. These are the registers where we select the clock source from the available list. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-08-22libc: Fix all includes in codebaseAntonio Nino Diaz
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-12imx: imx8qm: add domain off supportAnson Huang
Add domain off support for Linux kernel's cpu hot-plug feature, when there are cpu off request from Linux kernel, TF-A will send command to system controller to do CPU power gate accordingly, tested on i.MX8QM MEK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12imx: imx8qx: add domain suspend/resume supportAnson Huang
Add domain suspend/resume support, Linux kernel can "echo mem > /sys/power/state" to put system into suspend mode, all CPUs and cluster will be powered off and can be waked up if irq pending in GIC, tested on i.MX8QX MEK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12imx: imx8qx: add system reset supportAnson Huang
Add system reset support for i.MX8QX, when Linux kernel issues "reboot" command, TF-A will send command to inform system controller to reset whole board according to board design, tested on i.MX8QX MEK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-12imx: imx8qx: add system off supportAnson Huang
Add system power off support for i.MX8QX, when Linux kernel issues "poweroff" command, TF-A will send command to inform system controller to power off whole board according to board design, tested on i.MX8QX MEK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-19Support for NXP's i.MX8QM SoCAnson Huang
NXP's i.MX8QM is an ARMv8 SoC with 2 clusters, 2 Cortex-A72 cores in one cluster and 4 Cortex-A53 in the other cluster, and also has system controller (Cortex-M4) inside, documentation can be found in below link: https://www.nxp.com/products/processors-and-microcontrollers/ applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES This patch adds support for booting up SMP linux kernel (v4.9). Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-19Support for NXP's i.MX8QX SoCAnson Huang
NXP's i.MX8QX is an ARMv8 SoC with 4 Cortex-A35 cores and system controller (Cortex-M4) inside, documentation can be found in below link: https://www.nxp.com/products/processors-and-microcontrollers/ applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES This patch adds support for booting up SMP linux kernel (v4.9). Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-19Support for NXP's imx SoC common functionAnson Huang
This patch adds support for NXP's imx SoC common function support like topology, gic implementation. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-19Support for NXP's imx SoC debug uartAnson Huang
Add NXP's imx SoC debug uart driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-19Support for NXP's i.MX8 SoCs IPCAnson Huang
NXP's i.MX8 SoCs have system controller (M4 core) which takes control of clock management, power management, partition management, PAD management etc., other clusters like Cortex-A35 can send out command via MU (Message Unit) to system controller for clock/power management etc.. This patch adds basic IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>