aboutsummaryrefslogtreecommitdiff
path: root/plat/arm/common/arm_bl2_setup.c
AgeCommit message (Collapse)Author
2024-01-25feat(arm): move GPT setup to common BL sourceRohit Mathew
As of now, GPT setup is being handled from BL2 for plat/arm platforms. However, for platforms having a separate entity to load firmware images, it is possible for BL31 to setup the GPT. In order to address this concern, move the GPT setup implementation from arm_bl2_setup.c file to arm_common.c. Additionally, rename the API from arm_bl2_gpt_setup to arm_gpt_setup to make it boot stage agnostic. Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Change-Id: I35d17a179c8746945c69db37fd23d763a7774ddc
2024-01-25feat(arm): retrieve GPT related data from platformRohit Mathew
For RME-enabled platforms, initializing L0 and L1 tables and enabling GPC checks is necessary. For systems using BL2 to load firmware images, the GPT initialization has to be done in BL2 prior to the image load. The common Arm platform code currently implements this in the "arm_bl2_plat_gpt_setup" function, relying on the FVP platform's specifications (PAS definitions, GPCCR_PPS, and GPCCR_PGS). Different Arm platforms may have distinct PAS definitions, GPCCR_PPS, GPCCR_PGS, L0/L1 base, and size. To accommodate these variations, introduce the "plat_arm_get_gpt_info" API. Platforms must implement this API to provide the necessary data for GPT setup on RME-enabled platforms. It is essential to note that these additions are relevant to platforms under the plat/arm hierarchy that will reuse the "arm_bl2_plat_gpt_setup" function. As a result of these new additions, migrate data related to the FVP platform to its source and header files. Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Change-Id: I4f4c8894c1cda0adc1f83e7439eb372e923f6147
2024-01-25refactor(arm): rename L0/L1 GPT base macrosRohit Mathew
In accordance with common naming conventions, macros specifying the base address of a region typically use the prefix "BASE" combined with the region name, rather than "ADDR_BASE." Currently, the macros defining the base addresses for L0 and L1 GPT tables within `arm_def.h` are named "ARM_L0_GPT_ADDR_BASE" and "ARM_L1_GPT_ADDR_BASE" respectively. To adhere to the established naming convention, rename these macros as "ARM_L1_GPT_BASE" and "ARM_L0_GPT_BASE" respectively. Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Change-Id: Ibd50a58a1f63ba97d2df141f41a21a89ef97d6fb
2023-11-08chore(auth)!: remove CryptoCell-712/713 supportSandrine Bailleux
CryptoCell-712 and CryptoCell-713 drivers have been deprecated since TF-A v2.9 and their removal was announced for TF-A v2.10 release. See [1]. As the release is approaching, this patch deletes these drivers' code as well as all references to them in the documentation and Arm platforms code (Nuvoton platform is taken care in a subsequent patch). Associated build options (ARM_CRYPTOCELL_INTEG and PLAT_CRYPTOCELL_BASE) have also been removed and thus will have no effect if defined. This is a breaking change for downstream platforms which use these drivers. [1] https://trustedfirmware-a.readthedocs.io/en/v2.9/about/release-information.html#removal-of-deprecated-drivers Note that TF-A v3.0 release later got renumbered into v2.10. Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: Idabbc9115f6732ac1a0e52b273d3380677a39813
2023-10-30refactor(bl2): make post image handling platform-specificHarrison Mutai
In certain instances a platform may need to make modifications to an image after it has been loaded by BL2. The existing common implementation is a thin wrapper for a more generic arm post image handler. To enable platforms to make changes to images when they're loaded, move this into platform code. Change-Id: I44025391056adb2d8a8eb4ea5984257b02027181 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-10-27refactor(arm): use gpt_partition_initGovindraj Raja
Current interface partition_init accepts GPT image id and parses the GPT image but doesn't return any error on failure. So use gpt_partition_init which implicitly initialises with GPT image ID and returns a value. Change-Id: I63280aa672388f1f8d9dc377ae13002c9f861f03 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-01-31feat(rme): read DRAM information from FVP DTBAlexeiFedorov
This patch builds on the previous patch by implementing support for reading NS DRAM layout of FVP model from HW_CONFIG Device tree. Macro _RMMD_MANIFEST_VERSION is renamed to SET_RMMD_MANIFEST_VERSION to suppress MISRA-C "rule MC3R1.D4.5: (advisory) Identifiers in the same name space with overlapping visibility should be typographically unambiguous" warning Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: Ifc2461b4441a1efdd4b7c656ab4d15e62479f77b
2023-01-17feat(rme): set DRAM information in Boot Manifest platform dataAlexeiFedorov
This patch adds support for setting configuration of DRAM banks for FVP model in RMM-EL3 Boot Manifest structure. Structure 'rmm_manifest' is extended with 'plat_dram' structure which contains information about platform's DRAM layout: - number of DRAM banks; - pointer to 'dram_bank[]' array; - check sum: two's complement 64-bit value of the sum of data in 'plat_dram' and 'dram_bank[] array. Each 'dram_bank' structure holds information about DRAM bank base address and its size. This values must be aligned to 4KB page size. The patch increases Boot Manifest minor version to 2 and removes 'typedef rmm_manifest_t' as per "3.4.15.1. Avoid anonymous typedefs of structs/enums in headers" of https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: I5176caa5780e27d1e0daeb5dea3e40cf6ad5fd12
2022-12-06feat(rmm): add support for the 2nd DRAM bankAlexeiFedorov
This patch adds support for RMM granules allocation in FVP 2nd DRAM 2GB bank at 0x880000000 base address. For ENABLE_RME = 1 case it also removes "mem=1G" Linux kernel command line option in fvp-base-psci-common.dsti to allow memory layout discovery from the FVP device tree. FVP parameter 'bp.dram_size' - size of main memory in gigabytes documented in docs/components/realm-management-extension.rst is changed from 2 to 4. Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: I174da4416ad5a8d41bf0ac89f356dba7c0cd3fe7
2021-10-12refactor(measured_boot): remove passing of BL2 hash via device treeManish V Badarkhe
Subsequent patches will provide a solution to do the BL2 hash measurement and recording in BL1 itself, hence in preparation to adopt that solution remove the logic of passing BL2 hash measurement to BL2 component via TB_FW config. Change-Id: Iff9b3d4c6a236a33b942898fcdf799cbab89b724 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-10-05refactor(gpt): productize and refactor GPT libraryjohpow01
This patch updates and refactors the GPT library and fixes bugs. - Support all combinations of PGS, PPS, and L0GPTSZ parameters. - PPS and PGS are set at runtime, L0GPTSZ is read from GPCCR_EL3. - Use compiler definitions to simplify code. - Renaming functions to better suit intended uses. - MMU enabled before GPT APIs called. - Add comments to make function usage more clear in GPT library. - Added _rme suffix to file names to differentiate better from the GPT file system code. - Renamed gpt_defs.h to gpt_rme_private.h to better separate private and public code. - Renamed gpt_core.c to gpt_rme.c to better conform to TF-A precedent. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I4cbb23b0f81e697baa9fb23ba458aa3f7d1ed919
2021-10-05feat(plat/arm): add GPT initialization code for Arm platformsZelalem Aweke
When RME is enabled, during configuration of the TrustZone controller, Root regions are initially configured as Secure regions, and Realm regions as Non-secure regions. Then later these regions are configured as Root and Realm regions respectively in the GPT. According to the RME architecture reference manual, Root firmware must ensure that Granule Protection Check is enabled before enabling any stage of translation. Therefore initializations are done as follows when RME is enabled : Initialize/enable the TrustZone controller (plat_arm_security_setup) --> Initialize/enable GPC (arm_bl2_plat_gpt_setup) --> enable MMU (enable_mmu_el3) Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I91094e8259079437bee02de1f65edb9ad51e43cf
2021-10-05feat(plat/fvp): add memory map for FVP platform for FEAT_RMEZelalem Aweke
When FEAT_RME is enabled, memory is divided into four Physical Address Spaces (PAS): Root, Realm, Secure and Non-secure. This patch introduces new carveouts for the Trusted SRAM and DRAM for the FVP platform accordingly. The following new regions are introduced with this change: ARM_MAP_L0_GPT_REGION: Trusted SRAM region used to store Level 0 Granule Protection Table (GPT). This region resides in the Root PAS. ARM_MAP_GPT_L1_DRAM: DRAM region used to store Level 1 GPT. It resides in the Root PAS. ARM_MAP_RMM_DRAM: DRAM region used to store RMM image. It resides in the Realm PAS. The L0 GPT is stored on Trusted SRAM next to firmware configuration memory. The DRAM carveout when RME is enable is modified as follow: -------------------- | | | AP TZC (~28MB) | -------------------- | | | REALM (32MB) | -------------------- | | | EL3 TZC (3MB) | -------------------- | L1 GPT + SCP TZC | | (~1MB) | 0xFFFF_FFFF -------------------- During initialization of the TrustZone controller, Root regions are configured as Secure regions. Then they are later reconfigured to Root upon GPT initialization. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: If2e257141d51f51f715b70d4a06f18af53607254
2021-10-05refactor(plat/arm): modify memory region attributes to account for FEAT_RMEZelalem Aweke
If FEAT_RME is enabled, EL3 runs in the Root world as opposed to Secure world. This patch changes EL3 memory region attributes for Arm platforms accordingly. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: Ie176f8b440ff34330e4e44bd3bf8d9703b3892ff
2021-09-28build(bl2): enable SP pkg loading for S-EL1 SPMCBalint Dobszay
Currently the SP package loading mechanism is only enabled when S-EL2 SPMC is selected. Remove this limitation. Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Change-Id: I5bf5a32248e85a26d0345cacff7d539eed824cfc
2021-08-02feat(plat/arm): add FWU support in Arm platformsManish V Badarkhe
Added firmware update support in Arm platforms by using FWU platform hooks and compiling FWU driver in BL2 component. Change-Id: I71af06c09d95c2c58e3fd766c4a61c5652637151 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-04-29feat(plat/arm): add GPT parser supportManish V Badarkhe
Added GPT parser support in BL2 for Arm platforms to get the entry address and length of the FIP in the GPT image. Also, increased BL2 maximum size for FVP platform to successfully compile ROM-enabled build with this change. Verified this change using a patch: https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/9654 Change-Id: Ie8026db054966653b739a82d9ba106d283f534d0 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-08-14Prevent colliding identifiersJimmy Brisson
There was a collision between the name of the typedef in the CASSERT and something else, so we make the name of the typedef unique to the invocation of DEFFINE_SVC_UUID2 by appending the name that's passed into the macro. This eliminates the following MISRA violation: bl1/bl1_main.c:233:[MISRA C-2012 Rule 5.6 (required)] Identifier "invalid_svc_uuid" is already used to represent a typedef. This also resolves MISRA rule 5.9. These renamings are as follows: * tzram -> secram. This matches the function call name as it has sec_mem in it's name * fw_config_base -> config_base. This file does not mess with hw_conig, so there's little chance of confusion Change-Id: I8734ba0956140c8e29b89d0596d10d61a6ef351e Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-07-23plat/arm: Move fconf population after the enablement of MMUManish V Badarkhe
In BL2, fw_config's population happened before the cache gets enabled. Hence to boost the performance, moved fw_config's population after cache gets enabled (i.e. after MMU gets enabled). Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I2e75cabd76b1cb7a660f6b72f409ab40d2877284
2020-07-21TF-A: Add support for Measured Boot driverAlexei Fedorov
This patch adds support for Measured Boot driver functionality in common Arm platform code. Change-Id: If049dcf8d847c39023b77c0d805a8cf5b8bcaa3e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-06-29plat/arm: Add assert for the valid address of dtb informationManish V Badarkhe
Added assert in the code to check valid address of dtb information structure retrieved from fw_config device tree. This patch fixes coverity defect:360213. Also, removed conditional calling of "fconf_populate" as "fconf_populate" function already checks the validity of the device tree address received and go to panic in case of address is NULL. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib83e4e84a95e2456a12c7a2bb3fe70461d882cba
2020-06-25plat/arm: Load and populate fw_config and tb_fw_configManish V Badarkhe
Modified the code to do below changes: 1. Load tb_fw_config along with fw_config by BL1. 2. Populate fw_config device tree information in the BL1 to load tb_fw_config. 3. In BL2, populate fw_config information to retrieve the address of tb_fw_config and then tb_fw_config gets populated using retrieved address. 4. Avoid processing of configuration file in case of error value returned from "fw_config_load" function. 5. Updated entrypoint information for BL2 image so that it's arg0 should point to fw_config address. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: Ife6f7b673a074e7f544ee3d1bda7645fd5b2886c
2020-06-24fconf: Clean confused naming between TB_FW and FW_CONFIGManish V Badarkhe
Cleaned up confused naming between TB_FW and FW_CONFIG. Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I9e9f6e6ca076d38fee0388f97d370431ae067f08
2020-03-23spmd: skip loading of secure partitions on pre-v8.4 platformsOlivier Deprez
When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1 then there is no need for TF-A to load secure partitions individually. In this configuration, SPMC handles secure partition loading at S-EL1/EL0 levels. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I06a0d88a4811274a8c347ce57b56bb5f64e345df
2020-03-11fconf: enhancements to firmware configuration frameworkMadhukar Pappireddy
A populate() function essentially captures the value of a property, defined by a platform, into a fconf related c structure. Such a callback is usually platform specific and is associated to a specific configuration source. For example, a populate() function which captures the hardware topology of the platform can only parse HW_CONFIG DTB. Hence each populator function must be registered with a specific 'config_type' identifier. It broadly represents a logical grouping of configuration properties which is usually a device tree source file. Example: > TB_FW: properties related to trusted firmware such as IO policies, base address of other DTBs, mbedtls heap info etc. > HW_CONFIG: properties related to hardware configuration of the SoC such as topology, GIC controller, PSCI hooks, CPU ID etc. This patch modifies FCONF_REGISTER_POPULATOR macro and fconf_populate() to register and invoke the appropriate callbacks selectively based on configuration type. Change-Id: I6f63b1fd7a8729c6c9137d5b63270af1857bb44a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-03-04SPMD: loading Secure Partition payloadsManish Pandey
This patch implements loading of Secure Partition packages using existing framework of loading other bl images. The current framework uses a statically defined array to store all the possible image types and at run time generates a link list and traverse through it to load different images. To load SPs, a new array of fixed size is introduced which will be dynamically populated based on number of SPs available in the system and it will be appended to the loadable images list. Change-Id: I8309f63595f2a71b28a73b922d20ccba9c4f6ae4 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
2020-02-11Merge changes from topic "lm/fconf" into integrationSandrine Bailleux
* changes: arm-io: Panic in case of io setup failure MISRA fix: Use boolean essential type fconf: Add documentation fconf: Move platform io policies into fconf fconf: Add mbedtls shared heap as property fconf: Add TBBR disable_authentication property fconf: Add dynamic config DTBs info as property fconf: Populate properties from dtb during bl2 setup fconf: Load config dtb from bl1 fconf: initial commit
2020-02-07fconf: Populate properties from dtb during bl2 setupLouis Mayencourt
Use the dtb provided by bl1 as configuration file for fconf. Change-Id: I3f466ad9b7047e1a361d94e71ac6d693e31496d9 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-02-05coverity: Fix MISRA null pointer violationsZelalem
Fix code that violates the MISRA rule: MISRA C-2012 Rule 11.9: Literal "0" shall not be used as null pointer constant. The fix explicitly checks whether a pointer is NULL. Change-Id: Ibc318dc0f464982be9a34783f24ccd1d44800551 Signed-off-by: Zelalem <zelalem.aweke@arm.com>
2019-08-01Switch AARCH32/AARCH64 to __aarch64__Julius Werner
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-01-25plat/arm: Sanitise includesAntonio Nino Diaz
Use full include paths like it is done for common includes. This cleanup was started in commit d40e0e08283a ("Sanitise includes across codebase"), but it only cleaned common files and drivers. This patch does the same to Arm platforms. Change-Id: If982e6450bbe84dceb56d464e282bcf5d6d9ab9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-15plat/arm: Fix header dependenciesAntonio Nino Diaz
From now on, platform_def.h must include any header with definitions that are platform-specific (like arm_def.h) and the included headers mustn't include back platform_def.h, and shouldn't be used by other files. Only platform_def.h should be included in other files. This will ensure that all needed definitions are present, rather than needing to include all the headers in all the definitions' headers just in case. This also prevents problems like cyclic dependencies. Change-Id: I9d3cf4d1de4b956fa035c79545222697acdaf5ca Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-26Convert arm_setup_page_tables into a generic helperRoberto Vargas
This function is not related to Arm platforms and can be reused by other platforms if needed. Change-Id: Ia9c328ce57ce7e917b825a9e09a42b0abb1a53e8 Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28plat/arm: Migrate to new interfacesAntonio Nino Diaz
- Remove references to removed build options. - Remove support for legacy GIC driver. - Remove support for LOAD_IMAGE_V2=0. Change-Id: I72f8c05620bdf4a682765e6e53e2c04ca749a3d5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-18ARM platforms: Reintroduce coherent memory for BL1 and BL2Soby Mathew
The patch d323af9 removed the support for coherent memory in BL1 and BL2 for ARM platforms. But the CryptoCell SBROM integration depends on use of coherent buffers for passing data from the AP CPU to the CryptoCell. Hence this patch reintroduces support for coherent memory in BL1 and BL2 if ARM_CRYPTOCELL_INTEG=1. Change-Id: I011482dda7f7a3ec9e3e79bfb3f4fa03796f7e02 Signed-Off-by: Soby Mathew <soby.mathew@arm.com>
2018-08-30Prevent two weak definitions of the same functionDaniel Boulby
Add another level of abstraction of weak defs for arm_bl2_handle_post_image_load to prevent two weak definitions of the same function Change-Id: Ie953786f43b0f88257c82956ffaa5fe0d19603db Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-08-13Merge pull request #1510 from robertovargas-arm/romlibDimitris Papastamos
Add support for moving libraries to ROM
2018-08-10plat/arm: Migrate to enable_mmu_svc_mon()Antonio Nino Diaz
Change-Id: I1bb310e1b05968d30b28913c4011c0601e1ae64e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-06Add librom support in FVPRoberto Vargas
Change-Id: Idb9ba3864d6de3053260724f07172fd32c1523e0 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-08-01Fix build for SEPARATE_CODE_AND_RODATA=0Daniel Boulby
TF won't build since no memory region is specified for when SEPARATE_CODE_AND_RODATA=0 it still relies on the ARM_MAP_BL_RO_DATA region which is never defined for this case. Create memory region combining code and RO data for when the build flag SEPARATE_CODE_AND_RODATA=0 to fix this Change-Id: I6c129eb0833497710cce55e76b8908ce03e0a638 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-07-25Merge pull request #1472 from danielboulby-arm/db/Reclaimdanh-arm
Rework page table setup for varying number of mem regions
2018-07-24Rework page table setup for varying number of mem regionsDaniel Boulby
Change arm_setup_page_tables() to take a variable number of memory regions. Remove coherent memory region from BL1, BL2 and BL2U as their coherent memory region doesn't contain anything and therefore has a size of 0. Add check to ensure this doesn't change without us knowing. Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-07-11Fix some violations to MISRA rule 8.3Sandrine Bailleux
Wherever we use 'struct foo' and 'foo_t' interchangeably in a function's declaration and definition, use 'struct foo' consistently for both, as per the TF-A coding guidelines [1]. [1] https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Coding-Guidelines#avoid-anonymous-typedefs-of-structsenums-in-header-files Change-Id: I7998eb24a26746e87e9b6425529926406745b721 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-06-19plat/arm: Migrate AArch64 port to the multi console driverAntonio Nino Diaz
The old API is deprecated and will eventually be removed. Arm platforms now use the multi console driver for boot and runtime consoles. However, the crash console uses the direct console API because it doesn't need any memory access to work. This makes it more robust during crashes. The AArch32 port of the Trusted Firmware doesn't support this new API yet, so it is only enabled in AArch64 builds. Because of this, the common code must maintain compatibility with both systems. SP_MIN doesn't have to be updated because it's only used in AArch32 builds. The TSP is only used in AArch64, so it only needs to support the new API without keeping support for the old one. Special care must be taken because of PSCI_SYSTEM_SUSPEND. In Juno, this causes the UARTs to reset (except for the one used by the TSP). This means that they must be unregistered when suspending and re-registered when resuming. This wasn't a problem with the old driver because it just restarted the UART, and there were no problems associated with registering and unregistering consoles. The size reserved for BL2 has been increased. Change-Id: Icefd117dd1eb9c498921181a21318c2d2435c441 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-06-08Revert "Code change to fix small bugs"Dimitris Papastamos
2018-06-08Merge pull request #1389 from danielboulby-arm/db/bugfixDimitris Papastamos
Code change to fix small bugs
2018-06-07ARM platforms: Move BL31 below BL2 to enable BL2 overlaySoby Mathew
The patch changes the layout of BL images in memory to enable more efficient use of available space. Previously BL31 was loaded with the expectation that BL2 memory would be reclaimed by BL32 loaded in SRAM. But with increasing memory requirements in the firmware, we can no longer fit BL32 in SRAM anymore which means the BL2 memory is not reclaimed by any runtime image. Positioning BL2 below BL1-RW and above BL31 means that the BL31 NOBITS can be overlaid on BL2 and BL1-RW. This patch also propogates the same memory layout to BL32 for AArch32 mode. The reset addresses for the following configurations are also changed : * When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode * When BL2_AT_EL3=1 for BL2 The restriction on BL31 to be only in DRAM when SPM is enabled is now removed with this change. The update to the firmware design guide for the BL memory layout is done in the following patch. Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-05-25Remove duplicate weak definitionDaniel Boulby
The weak pragma was assigned twice to the bl2_plat_handle_post_image_load definition both in plat/common/ and in plat/arm/common/ this was an error as it should have only have been defined in plat/common Change-Id: Id85e14c699cb09ed998d1677f2a172e760911918 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-05-18FVP: Enable capability to disable auth via dynamic configSoby Mathew
This patch adds capability to FVP to disable authentication dynamically via the `disable_auth` property in TB_FW_CONFIG. Both BL1 and BL2 parses the TB_FW_CONFIG for the `disable_auth` property and invokes the `load_dyn_disable_auth()` API to disable authentication if the property is set to 1. The DYN_DISABLE_AUTH is enabled by default for FVP as it is a development platform. Note that the TB_FW_CONFIG has to be authenticated by BL1 irrespective of these settings. The arm_bl2_dyn_cfg_init() is now earlier in bl2_plat_preload_setup() rather than in bl2_platform_setup() as we need to get the value of `disable_auth` property prior to authentication of any image by BL2. Change-Id: I734acd59572849793e5020ec44c6ac51f654a4d1 Signed-off-by: Soby Mathew <soby.mathew@arm.com>