aboutsummaryrefslogtreecommitdiff
path: root/plat/allwinner/common/sunxi_common.c
AgeCommit message (Collapse)Author
2023-04-26feat(allwinner): add function to detect H616 die variantAndre Przywara
Allwinner provides a number of SoCs that use the same die as the H616. Some of those chips apparently use a slight variation of that die, that differs in the way the CPU cores' power and reset controls are handled. This die variation can be detected by reading the SRAM version register. Provide a predicate function that returns false if that die variant is used. Since the CPU power control code is shared for all supported SoCs, we provide an instance of this function for each SoC, as a static inline, and return true on all other SoCs. This allows to always use this function, and still let the compiler optimise away the unneeded branch for those older SoCs. This function is unused for now, but is needed in the next patch. Change-Id: I49e014b895b7e2f55b4e7dc2b3d8aa31cee711b5 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-04feat(allwinner): add SMCCC SOCID supportAndre Przywara
The Allwinner SID device holds a 16-bit SoC identifier, which we already use in our code. Export this number through the generic SMCCC SOCID interface, to allow an architectural identification of an Allwinner SoC. This enables access to this information from non-secure world, simplifies generic drivers (ACPI comes to mind), and gives easy and precise access to the SoC ID from userland in OSes like Linux. Change-Id: I91753046b2ae5408ca7bc0b864fcd97d24c8267c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-22refactor(plat/allwinner): do not map BL32 DRAM at EL3Samuel Holland
BL31 does not appear to ever access the DRAM allocated to BL32, so there is no need to map it at EL3. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ie8727b793e53ea14517894942266f6da0333eb74
2021-07-22refactor(plat/allwinner): map SRAM as device memory by defaultSamuel Holland
The SRAM on Allwinner platforms is shared between BL31 and coprocessor firmware. Previously, SRAM was mapped as normal memory by default. This scheme requires carveouts and cache maintenance code for proper synchronization with the coprocessor. A better scheme is to only map pages owned by BL31 as normal memory, and leave everything else as device memory. This removes the need for cache maintenance, and it makes the mapping for BL31 RW data explicit instead of magic. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I820ddeba2dfa2396361c2322308c0db51b55c348
2021-07-22refactor(plat/allwinner): rename static mmap region constantSamuel Holland
This constant specifically refers to the number of static mmap regions. Rename it to make that clear. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I475c037777ce2a10db2631ec0e7446bb73590a36
2021-03-26allwinner: H616: Add reserved-memory node to DTAndre Przywara
When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure we tell the non-secure world about the memory region it uses. Add a reserved-memory node to the DT, which covers the area that BL31 could occupy. The "no-map" property will prevent OSes from mapping the area, so there would be no speculative accesses. Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25allwinner: Add Allwinner H616 SoC supportAndre Przywara
The new Allwinner H616 SoC lacks the management controller and the secure SRAM A2, so we need to tweak the memory map quite substantially: We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our compressed virtual address space (max 256MB) anymore, so we revert to the full 32bit VA space and use a flat mapping throughout all of it. The missing controller also means we need to always use the native PSCI ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC. Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25allwinner: Add H616 SoC IDAndre Przywara
Change-Id: I557fd05401e24204952135cf3ca26479a43ad1f1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25allwinner: Express memmap more dynamicallyAndre Przywara
In preparation for changing the memory map, express the locations of the various code and data pieces more dynamically, allowing SoCs to override the memmap later. Also prepare for the SCP region to become optional. No functional change. Change-Id: I7ac01e309be2f23bde2ac2050d8d5b5e3d6efea2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25allwinner: Move sunxi_cpu_power_off_self() into platformsAndre Przywara
The code to power the current core off when SCPI is not available is now different for the two supported SoC families. To make adding new platforms easier, move sunxi_cpu_power_off_self() into the SoC directory, so we don't need to carry definitions for both methods for all SoCs. On the H6 we just need to trigger the CPUIDLE hardware, so can get rid of all the code to program the ARISC, which is now only needed for the A64 version. Change-Id: Id2a1ac7dcb375e2fd021b441575ce86b4d7edf2c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-12-22Merge "allwinner: Fix non-default PRELOADED_BL33_BASE" into integrationAndré Przywara
2020-12-13allwinner: Use RSB for the PMIC connection on H6Samuel Holland
RSB is faster and more efficient, and it has a simpler driver. As long as the PMIC is returned to I2C mode after use, the rich OS can later use either bus. Change-Id: I0c5f32e88a090c8c5cccb81bd24596b301ab9da7 Signed-off-by: Samuel Holland <samuel@sholland.org>
2020-12-13allwinner: Fix non-default PRELOADED_BL33_BASESamuel Holland
While the Allwinner platform code nominally supported a custom PRELOADED_BL33_BASE, some references to the BL33 load address used another constant: PLAT_SUNXI_NS_IMAGE_OFFSET. To allow the DTB search code to work if a U-Boot BL33 is loaded to a custom address, consistently use PRELOADED_BL33_BASE. And to avoid this confusion in the future, remove the other constant. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ie6b97ae1fdec95d784676aef39200bef161471b0
2020-02-12allwinner: Reserve and map space for the SCP firmwareSamuel Holland
The SCP firmware is allocated the last 16KiB of SRAM A2. This includes the SCPI shared memory area, which must be mapped as MT_DEVICE to prevent problems with cache coherency between the AP CPUs and the SCP. For simplicity, map the whole SCP region as MT_DEVICE. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ie39eb5ff281b8898a3c1d9748dc08755f528e2f8
2020-02-12allwinner: Adjust SRAM A2 base to include the ARISC vectorsSamuel Holland
The ARISC vector area consists of 0x4000 bytes before the beginning of usable SRAM. Still, it is technically a part of SRAM A2, so include it in the memory definition. This avoids the confusing practice of subtracting from the beginning of the SRAM region when referencing the ARISC vectors. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Iae89e01aeab93560159562692e03e88306e2a1bf
2020-01-20allwinner: Clean up MMU setupSamuel Holland
Remove the general BL31 mmap region: it duplicates the existing static mapping for the entire SRAM region. Use the helper definitions when applicable to simplify the code and add the MT_EXECUTE_NEVER flag. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I7a6b79e50e4b5c698774229530dd3d2a89e94a6d
2020-01-15allwinner: Reenable USE_COHERENT_MEMSamuel Holland
Now that there is plenty of space (32 KiB) available for NOBITS sections, we can afford using an entire page for coherent memory. In fact, because it simplifies the code, this is a beneficial change for loaded image (.text) size, where we are still close to the size limit. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9
2019-12-13allwinner: Enable clock before resetting I2C/RSBSamuel Holland
The clock must be running for the module to be reset. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ic8fafc946f3a1a697174b91288e357ffa033ab9a
2019-12-04allwinner: Fix incorrect ARISC code patch offset checkSamuel Holland
The current range check for the offset is wrong: it is counting bytes, while indexing an array of uint32_t. Since the offset is always zero, the parameter is unnecessary. Instead of adding more code to fix the check, remove the parameter to avoid the problem entirely. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6
2019-02-17allwinner: Constify data structuresSamuel Holland
This maximizes the amount of data protected by the MMU. Signed-off-by: Samuel Holland <samuel@sholland.org>
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-20allwinner: Prepare for executing code on the management processorAndre Przywara
The more recent Allwinner SoCs contain an OpenRISC management controller (called arisc or CPUS), which shares the bus with the ARM cores, but runs on a separate power domain. This is meant to handle power management with the ARM cores off. There are efforts to run sophisticated firmware on that core (communicating via SCPI with the ARM world), but for now can use it for the rather simple task of helping to turn the ARM cores off. As this cannot be done by ARM code itself (because execution stops at the first of the three required steps), we can offload some instructions to this management processor. This introduces a helper function to hand over a bunch of instructions and triggers execution. We introduce a bakery lock to avoid two cores trying to use that (single) arisc core. The arisc code is expected to put itself into reset after is has finished execution. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-10-20allwinner: H6: Factor out I2C platform setupAndre Przywara
In the H6 platform code there is a routine to do the platform initialisation of the R_I2C controller. We will need a very similar setup routine to initialise the RSB controller on the A64. Move this code to sunxi_common.c and generalise it to support all SoCs and also to cover the related RSB bus. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-10-20allwinner: Introduce GPIO helper functionAndre Przywara
Many boards without a dedicated PMIC contain simple regulators, which can be controlled via GPIO pins. To later allow turning them off easily, introduce a simple function to configure a given pin as a GPIO out pin and set it to the desired level. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-10-20allwinner: Export sunxi_private.hAndre Przywara
So far we have a sunxi_private.h header file in the common code directory. This holds the prototypes of various functions we share in *common* code. However we will need some of those in the platform specific code parts as well, and want to introduce new functions shared across the whole platform port. So move the sunxi_private.h file into the common/include directory, so that it becomes visible to all parts of the platform code. Fix up the existing #includes and add missing ones, also add the sunxi_read_soc_id() prototype here. This will be used in follow up patches. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-10-20allwinner: Disable USE_COHERENT_MEMAndre Przywara
According to the documentation, platforms may choose to trade memory footprint for performance (and elegancy) by not providing a separately mapped coherent page. Since a debug build is getting close to the SRAM size limit already, this allows us to save about 3.5KB of BSS and have some room for future enhancements. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-10-20allwinner: Adjust memory mapping to fit into 256MBAndre Przywara
At the moment we map as much of the DRAM into EL3 as possible, however we actually don't use it. The only exception is the secure DRAM for BL32 (if that is configured). To decrease the memory footprint of ATF, we save on some page tables by reducing the memory mapping to the actually required regions: SRAM, device MMIO, secure DRAM and U-Boot (to be used later). This introduces a non-identity mapping for the DRAM regions. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-28allwinner: Detect and output current SoCAndre Przywara
So far we already support booting on two different SoCs, and we will shortly add a third, so add some code to determine the current SoC type. This can be later used to runtime detect certain properties. Also print the SoC name to the console, to give valuable debug information. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-28allwinner: Don't map boot ROMAndre Przywara
There is nothing we need from the BootROM area, so we also don't need to map it in EL3. Remove the mapping and reduce the number of MMAP regions by one. Reported-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-28allwinner: common: add missing headerAndre Przywara
Some code in sunxi_common.c requires symbols defined in sunxi_private.h, so add the header to that file. It was included via another header before, but let's make this explicit. Reported-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-15allwinner: Introduce basic platform supportSamuel Holland
This platform supports Allwinner's SoCs with ARMv8 cores. So far they all sport a single cluster of Cortex-A53 cores. "sunxi" is the original code name used for this platform, and since it appears in the Linux kernel and in U-Boot as well, we use it here as a short file name prefix and for identifiers. This port includes BL31 support only. U-Boot's SPL takes the role of the primary loader, also doing the DRAM initialization. It then loads the rest of the firmware, namely ATF and U-Boot (BL33), then hands execution over to ATF. This commit includes the basic platform code shared across all SoCs. There is no platform.mk yet. [Andre: moved files into proper directories, supported RESET_TO_BL31, various clean ups and simplifications ] Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>