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2023-07-13fix(xlat): fix defects on the xlat library reported by coverity scanJavier Almansa Sobrino
The coverity defects fixed by this patch is ** CID 394601: Integer handling issues (NO_EFFECT) /lib/xlat_tables_v2/aarch64/xlat_tables_arch.c: 30 in xlat_arch_is_granule_size_supported() Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Ibc8e20bd7318a52702fbd7aa86e22cd2ded42610
2023-06-05feat(xlat): detect 4KB and 16KB page support when FEAT_LPA2 is presentJavier Almansa Sobrino
At the moment, TF-A does not need to access VAs or PAs larger than 48 bits, so this patch just enables proper detection of support for 4KB and 16KB granularity with 52 bits address support. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iccebbd5acc21f09dbb234ef21a802300e290ec18
2021-10-04feat(rme): add xlat table library changes for FEAT_RMEZelalem Aweke
FEAT_RME adds a new bit (NSE) in the translation table descriptor to determine the Physical Address Space (PAS) of an EL3 stage 1 translation according to the following mapping: TTD.NSE TTD.NS | PAS ================================= 0 0 | Secure 0 1 | Non-secure 1 0 | Root 1 1 | Realm This patch adds modifications to version 2 of the translation table library accordingly. Bits 4 and 5 in mmap attribute are used to determine the PAS. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I82790f6900b7a1ab9494c732eac7b9808a388103
2020-04-03xlat_tables_v2: use get_current_el_maybe_constant() in is_dcache_enabled()Masahiro Yamada
Using get_current_el_maybe_constant() produces more optimized code because in most cases, we know the exception level at build-time. For example, BL31 runs at EL3, so unneeded code will be trimmed. [before] 0000000000000000 <is_dcache_enabled>: 0: d5384240 mrs x0, currentel 4: 53020c00 ubfx w0, w0, #2, #2 8: 7100041f cmp w0, #0x1 c: 54000081 b.ne 1c <is_dcache_enabled+0x1c> // b.any 10: d5381000 mrs x0, sctlr_el1 14: 53020800 ubfx w0, w0, #2, #1 18: d65f03c0 ret 1c: 7100081f cmp w0, #0x2 20: 54000061 b.ne 2c <is_dcache_enabled+0x2c> // b.any 24: d53c1000 mrs x0, sctlr_el2 28: 17fffffb b 14 <is_dcache_enabled+0x14> 2c: d53e1000 mrs x0, sctlr_el3 30: 17fffff9 b 14 <is_dcache_enabled+0x14> [after] 0000000000000000 <is_dcache_enabled>: 0: d53e1000 mrs x0, sctlr_el3 4: 53020800 ubfx w0, w0, #2, #1 8: d65f03c0 ret Change-Id: I3698fae9b517022ff9fbfd4cad3a320c6e137e10 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-04-03SPM: Move shim layer to TTBR1_EL1Antonio Nino Diaz
This gives each Secure Partition complete freedom on its address space. Previously, the memory used by the exception vectors was reserved and couldn't be used. Also, it always had to be mapped, forcing SPM to generate translation tables that included the exception vectors as well as the Partition memory regions. With this change, partitions can reduce their address space size easily. Change-Id: I67fb5e9bdf2870b73347f23bff702fab0a8f8711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-30lib/xlat_tables: Add support for ARMv8.4-TTSTSathees Balya
ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the size of translation tables by increasing the maximum permitted value of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and VSTCR_EL2. This feature is supported in AArch64 state only. This patch adds support for this feature to both versions of the translation tables library. It also removes the static build time checks for virtual address space size checks to runtime assertions. Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
2019-01-11xlat v2: Dynamically detect need for CnP bitAntonio Nino Diaz
ARMv8.2-TTCNP is mandatory from ARMv8.2 onwards, but it can be implemented in CPUs that don't implement all mandatory 8.2 features (and so have to claim to be a lower version). This patch removes usage of the ARM_ARCH_AT_LEAST() macro and uses system ID registers to detect whether it is needed to set the bit or not. Change-Id: I7bcbf0c7c937590dfc2ca668cfd9267c50f7d52c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-22libc: Fix all includes in codebaseAntonio Nino Diaz
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-10xlat v2: Support the EL2 translation regimeAntonio Nino Diaz
The translation library is useful elsewhere. Even though this repository doesn't exercise the EL2 support of the library, it is better to have it here as well to make it easier to maintain. enable_mmu_secure() and enable_mmu_direct() have been deprecated. The functions are still present, but they are behind ERROR_DEPRECATED and they call the new functions enable_mmu_svc_mon() and enable_mmu_direct_svc_mon(). Change-Id: I13ad10cd048d9cc2d55e0fff9a5133671b67dcba Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-07xlat v2: Flush xlat tables after being modifiedAntonio Nino Diaz
During cold boot, the initial translation tables are created with data caches disabled, so all modifications go to memory directly. After the MMU is enabled and data cache is enabled, any modification to the tables goes to data cache, and eventually may get flushed to memory. If CPU0 modifies the tables while CPU1 is off, CPU0 will have the modified tables in its data cache. When CPU1 is powered on, the MMU is enabled, then it enables coherency, and then it enables the data cache. Until this is done, CPU1 isn't in coherency, and the translation tables it sees can be outdated if CPU0 still has some modified entries in its data cache. This can be a problem in some cases. For example, the warm boot code uses only the tables mapped during cold boot, which don't normally change. However, if they are modified (and a RO page is made RW, or a XN page is made executable) the CPU will see the old attributes and crash when it tries to access it. This doesn't happen in systems with HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY. In these systems, the data cache is enabled at the same time as the MMU. As soon as this happens, the CPU is in coherency. There was an attempt of a fix in psci_helpers.S, but it didn't solve the problem. That code has been deleted. The code was introduced in commit <264410306381> ("Invalidate TLB entries during warm boot"). Now, during a map or unmap operation, the memory associated to each modified table is flushed. Traversing a table will also flush it's memory, as there is no way to tell in the current implementation if the table that has been traversed has also been modified. Change-Id: I4b520bca27502f1018878061bc5fb82af740bb92 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-02xlat: Use bool instead of intAntonio Nino Diaz
Change-Id: I35d5b6a7c219f6f38983b30f157c1ed3808af17f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-30xlat: Fix MISRA defectsAntonio Nino Diaz
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6, 14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9. Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-15xlat v2: Make setup_mmu_config publicAntonio Nino Diaz
This allows other parts of the code to reuse it. No functional changes. Change-Id: Ib052ae235c422d9179958bd3016c3e678779ae9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-13xlat v2: Turn MMU parameters into 64-bit valuesAntonio Nino Diaz
Most registers are 64-bit wide, even in AArch32 mode: - MAIR_ELx is equivalent to MAIR0 and MAIR1. - TTBR is 64 bit in both AArch64 and AArch32. The only difference is the TCR register, which is 32 bit in AArch32 and in EL3 in AArch64. For consistency with the rest of ELs in AArch64, it makes sense to also have it as a 64-bit value. Change-Id: I2274d66a28876702e7085df5f8aad0e7ec139da9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-13xlat v2: Remove IMAGE_EL defineAntonio Nino Diaz
The Exception Level is now detected at runtime. This means that it is not needed to hardcode the EL used by each image. This doesn't result in a substantial increase of the image size because the initialization functions that aren't used are garbage-collected by the linker. In AArch32 the current EL has been changed from EL3 to EL1 because the the AArch32 PL1&0 translation regime behaves more like the AArch64 EL1&0 translation regime than the EL3 one. Change-Id: I941404299ebe7666ca17619207c923b49a55cb73 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-13xlat v2: Remove unused tlbi helperAntonio Nino Diaz
xlat_arch_tlbi_va_regime() isn't used, so it has been renamed to xlat_arch_tlbi_va() and the previous implementation has been removed. Change-Id: Ic118bed3fb68234748d86b2e9e95b25650289276 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-13xlat v2: Remove architectural headersAntonio Nino Diaz
They only contained one function that is easily integrated in the private library header and the existing architectural C files. This also helps making the library more portable, as the Makefile of the library now doesn't use the variable INCLUDES, which is specific to this codebase and doesn't respect the namespace of the library. Change-Id: I22228e6a97e9b4f346f5cd8947609263e8df71d8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-03xlat v2: Split code into separate filesAntonio Nino Diaz
Instead of having one big file with all the code, it's better to have a few smaller files that are more manageable: - xlat_tables_core.c: Code related to the core functionality of the library (map and unmap regions, initialize xlat context). - xlat_tables_context.c: Instantiation of the active image context as well as APIs to manipulate it. - xlat_tables_utils.c: Helper code that isn't part of the core functionality (change attributes, debug print messages). Change-Id: I3ea956fc1afd7473c0bb5e7c6aab3b2e5d88c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-06-27xlat v2: Split MMU setup and enableJeenu Viswambharan
At present, the function provided by the translation library to enable MMU constructs appropriate values for translation library, and programs them to the right registers. The construction of initial values, however, is only required once as both the primary and secondaries program the same values. Additionally, the MMU-enabling function is written in C, which means there's an active stack at the time of enabling MMU. On some systems, like Arm DynamIQ, having active stack while enabling MMU during warm boot might lead to coherency problems. This patch addresses both the above problems by: - Splitting the MMU-enabling function into two: one that sets up values to be programmed into the registers, and another one that takes the pre-computed values and writes to the appropriate registers. With this, the primary effectively calls both functions to have the MMU enabled, but secondaries only need to call the latter. - Rewriting the function that enables MMU in assembly so that it doesn't use stack. This patch fixes a bunch of MISRA issues on the way. Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-06-13xlat v2: Introduce xlat granule size helpersAntonio Nino Diaz
The function xlat_arch_is_granule_size_supported() can be used to check if a specific granule size is supported. In Armv8, AArch32 only supports 4 KiB pages. AArch64 supports 4 KiB, 16 KiB or 64 KiB depending on the implementation, which is detected at runtime. The function xlat_arch_get_max_supported_granule_size() returns the max granule size supported by the implementation. Even though right now they are only used by SPM, they may be useful in other places in the future. This patch moves the code currently in SPM to the xlat tables lib so that it can be reused. Change-Id: If54624a5ecf20b9b9b7f38861b56383a03bbc8a4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-05-02xlat: Have all values of PARange for 8.x architecturesAntonio Nino Diaz
In AArch64, the field ID_AA64MMFR0_EL1.PARange has a different set of allowed values depending on the architecture version. Previously, we only compiled the Trusted Firmware with the values that were allowed by the architecture. However, given that this field is read-only, it is easier to compile the code with all values regardless of the target architecture. Change-Id: I57597ed103dd0189b1fb738a9ec5497391c10dd1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-02-27Update ULL() macro and instances of ull to comply with MISRADavid Cunado
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-11-17Add ARMv8.2 ID_AA64MMFR0_EL1.PARange valueAntonio Nino Diaz
If an implementation of ARMv8.2 includes ARMv8.2-LPA, the value 0b0110 is permitted in ID_AA64MMFR0_EL1.PARange, which means that the Physical Address range supported is 52 bits (4 PiB). It is a reserved value otherwise. Change-Id: Ie0147218e9650aa09f0034a9ee03c1cca8db908a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-11-08xlat: Make function to calculate TCR PA bits publicAntonio Nino Diaz
This function can be useful to setup TCR_ELx by callers that don't use the translation tables library to setup the system registers related to them. By making it common, it can be reused whenever it is needed without duplicating code. Change-Id: Ibfada9e846d2a6cd113b1925ac911bb27327d375 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-10-05xlat: Add support for EL0 and EL1 mappingsAntonio Nino Diaz
This patch introduces the ability of the xlat tables library to manage EL0 and EL1 mappings from a higher exception level. Attributes MT_USER and MT_PRIVILEGED have been added to allow the user specify the target EL in the translation regime EL1&0. REGISTER_XLAT_CONTEXT2 macro is introduced to allow creating a xlat_ctx_t that targets a given translation regime (EL1&0 or EL3). A new member is added to xlat_ctx_t to represent the translation regime the xlat_ctx_t manages. The execute_never mask member is removed as it is computed from existing information. Change-Id: I95e14abc3371d7a6d6a358cc54c688aa9975c110 Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-10-05xlat: Introduce function xlat_arch_tlbi_va_regime()Douglas Raillard
Introduce a variant of the TLB invalidation helper function that allows the targeted translation regime to be specified, rather than defaulting to the current one. This new function is useful in the context of EL3 software managing translation tables for the S-EL1&0 translation regime, as then it might need to invalidate S-EL1&0 TLB entries rather than EL3 ones. Define a new enumeration to be able to represent translation regimes in the xlat tables library. Change-Id: Ibe4438dbea2d7a6e7470bfb68ff805d8bf6b07e5 Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-10-05xlat: Always compile TLB invalidation functionsSandrine Bailleux
TLB invalidation functions used to be conditionally compiled in. They were enabled only when using the dynamic mapping feature. because only then would we need to modify page tables on the fly. Actually there are other use cases where invalidating TLBs is required. When changing memory attributes in existing translation descriptors for example. These other use cases do not necessarily depend on the dynamic mapping feature. This patch removes this dependency and always compile TLB invalidation functions in. If they're not used, they will be removed from the binary at link-time anyway so there's no consequence on the memory footprint if these functions are not called. Change-Id: I1c33764ae900eb00073ee23b7d0d53d4efa4dd21 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-09-21Set TCR_EL1.EPD1 bit to 1Antonio Nino Diaz
In the S-EL1&0 translation regime we aren't using the higher VA range, whose translation table base address is held in TTBR1_EL1. The bit TCR_EL1.EPD1 can be used to disable translations using TTBR1_EL1, but the code wasn't setting it to 1. Additionally, other fields in TCR1_EL1 associated with the higher VA range (TBI1, TG1, SH1, ORGN1, IRGN1 and A1) weren't set correctly as they were left as 0. In particular, 0 is a reserved value for TG1. Also, TBBR1_EL1 was not explicitly set and its reset value is UNKNOWN. Therefore memory accesses to the higher VA range would result in unpredictable behaviour as a translation table walk would be attempted using an UNKNOWN value in TTBR1_EL1. On the FVP and Juno platforms accessing the higher VA range resulted in a translation fault, but this may not always be the case on all platforms. This patch sets the bit TCR_EL1.EPD1 to 1 so that any kind of unpredictable behaviour is prevented. This bug only affects the AArch64 version of the code, the AArch32 version sets this bit to 1 as expected. Change-Id: I481c000deda5bc33a475631301767b9e0474a303 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-08-24Enable CnP bit for ARMv8.2 CPUsIsla Mitchell
This patch enables the CnP (Common not Private) bit for secure page tables so that multiple PEs in the same Inner Shareable domain can use the same translation table entries for a given stage of translation in a particular translation regime. This only takes effect when ARM Trusted Firmware is built with ARM_ARCH_MINOR >= 2. ARM Trusted Firmware Design has been updated to include a description of this feature usage. Change-Id: I698305f047400119aa1900d34c65368022e410b8 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-07-26xlat lib: Fix some typesSandrine Bailleux
Fix the type length and signedness of some of the constants and variables used in the translation table library. This patch supersedes Pull Request #1018: https://github.com/ARM-software/arm-trusted-firmware/pull/1018 Change-Id: Ibd45faf7a4fb428a0bf71c752551d35800212fb2 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-07-26xlat lib v2: Remove hard-coded virtual address space sizeSandrine Bailleux
Previous patches have made it possible to specify the physical and virtual address spaces sizes for each translation context. However, there are still some places in the code where the physical (resp. virtual) address space size is assumed to be PLAT_PHY_ADDR_SPACE_SIZE (resp. PLAT_VIRT_ADDR_SPACE_SIZE). This patch removes them and reads the relevant address space size from the translation context itself instead. This information is now passed in argument to the enable_mmu_arch() function, which needs it to configure the TCR_ELx.T0SZ field (in AArch64) or the TTBCR.T0SZ field (in AArch32) appropriately. Change-Id: I20b0e68b03a143e998695d42911d9954328a06aa Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-07-26xlat lib v2: Refactor the functions enabling the MMUSandrine Bailleux
This patch refactors both the AArch32 and AArch64 versions of the function enable_mmu_arch(). In both versions, the code now computes the VMSA-related system registers upfront then program them in one go (rather than interleaving the 2). In the AArch64 version, this allows to reduce the amount of code generated by the C preprocessor and limits it to the actual differences between EL1 and EL3. In the AArch32 version, this patch also removes the function enable_mmu_internal_secure() and moves its code directly inside enable_mmu_arch(), as it was its only caller. Change-Id: I35c09b6db4404916cbb2e2fd3fda2ad59f935954 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-07-26xlat lib v2: Remove init_xlat_tables_arch() functionSandrine Bailleux
In both the AArch32 and AArch64 versions, this function used to check the sanity of the PLAT_PHY_ADDR_SPACE_SIZE in regard to the architectural maximum value. Instead, export the xlat_arch_get_max_supported_pa() function and move the debug assertion in AArch-agnostic code. The AArch64 used to also precalculate the TCR.PS field value, based on the size of the physical address space. This is now done directly by enable_mmu_arch(), which now receives the physical address space size in argument. Change-Id: Ie77ea92eb06db586f28784fdb479c6e27dd1acc1 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-05-09Minor fixes to the xlat tables lib v2Antonio Nino Diaz
- Fix some comments. - Remove duplicated definition. - Make xlat_arch_get_max_supported_pa() private in aarch64. Change-Id: I629237209cfb2ce7b0c4bd539d63dd81d45b2edd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-05Merge pull request #924 from antonio-nino-diaz-arm/an/fix-xn-bitdavidcunado-arm
Fix execute-never permissions in xlat tables libs
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-02Fix execute-never permissions in xlat tables libsAntonio Nino Diaz
Translation regimes that only support one virtual address space (such as the ones for EL2 and EL3) can flag memory regions as execute-never by setting to 1 the XN bit in the Upper Attributes field in the translation tables descriptors. Translation regimes that support two different virtual address spaces (such as the one shared by EL1 and EL0) use bits PXN and UXN instead. The Trusted Firmware runs at EL3 and EL1, it has to handle translation tables of both translation regimes, but the previous code handled both regimes the same way, as if both had only 1 VA range. When trying to set a descriptor as execute-never it would set the XN bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is at the same bit position as UXN, which means that EL0 was being prevented from executing code at this region, not EL1 as the code intended. Therefore, the PXN bit was unset to 0 all the time. The result is that, in AArch64 mode, read-only data sections of BL2 weren't protected from being executed. This patch adds support of translation regimes with two virtual address spaces to both versions of the translation tables library, fixing the execute-never permissions for translation tables in EL1. The library currently does not support initializing translation tables for EL0 software, therefore it does not set/unset the UXN bit. If EL1 software needs to initialize translation tables for EL0 software, it should use a different library instead. Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-04-20Control inclusion of helper code used for assertsAntonio Nino Diaz
Many asserts depend on code that is conditionally compiled based on the DEBUG define. This patch modifies the conditional inclusion of such code so that it is based on the ENABLE_ASSERTIONS build option. Change-Id: I6406674788aa7e1ad7c23d86ce94482ad3c382bd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-03-28Add support to change xlat_tables to non-cacheableSummer Qin
This patch adds an additional flag `XLAT_TABLE_NC` which marks the translation tables as Non-cacheable for MMU accesses. Change-Id: I7c28ab87f0ce67da237fadc3627beb6792860fd4 Signed-off-by: Summer Qin <summer.qin@arm.com>
2017-03-08Apply workaround for errata 813419 of Cortex-A57Antonio Nino Diaz
TLBI instructions for EL3 won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. This errata has been enabled for Juno. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-03-08Add dynamic region support to xlat tables lib v2Antonio Nino Diaz
Added APIs to add and remove regions to the translation tables dynamically while the MMU is enabled. Only static regions are allowed to overlap other static ones (for backwards compatibility). A new private attribute (MT_DYNAMIC / MT_STATIC) has been added to flag each region as such. The dynamic mapping functionality can be enabled or disabled when compiling by setting the build option PLAT_XLAT_TABLES_DYNAMIC to 1 or 0. This can be done per-image. TLB maintenance code during dynamic table mapping and unmapping has also been added. Fixes ARM-software/tf-issues#310 Change-Id: I19e8992005c4292297a382824394490c5387aa3b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-03-08Add version 2 of xlat tables libraryAntonio Nino Diaz
The folder lib/xlat_tables_v2 has been created to store a new version of the translation tables library for further modifications in patches to follow. At the moment it only contains a basic implementation that supports static regions. This library allows different translation tables to be modified by using different 'contexts'. For now, the implementation defaults to the translation tables used by the current image, but it is possible to modify other tables than the ones in use. Added a new API to print debug information for the current state of the translation tables, rather than printing the information while the tables are being created. This allows subsequent debug printing of the xlat tables after they have been changed, which will be useful when dynamic regions are implemented in a patch to follow. The common definitions stored in `xlat_tables.h` header have been moved to a new file common to both versions, `xlat_tables_defs.h`. All headers related to the translation tables library have been moved to a the subfolder `xlat_tables`. Change-Id: Ia55962c33e0b781831d43a548e505206dffc5ea9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>