AgeCommit message (Collapse)Author
20 hoursMerge "doc: Fix broken external link for Odroid C2"HEADmasterSandrine Bailleux
30 hoursMerge "plat: imx: imx8qx: provide debug uart num as build param" into ↵Mark Dykes
31 hoursMerge "Update code freeze and release target date for 2.3" into integrationMark Dykes
32 hoursMerge "xlat_tables_v2: add enable_mmu()" into integrationMark Dykes
32 hoursMerge "Add get_current_el_maybe_constant()" into integrationMark Dykes
32 hoursMerge "Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C files" into ↵Mark Dykes
32 hoursUpdate code freeze and release target date for 2.3laurenw-arm
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Icf0a5737852e4f025dd8ce3748594ad25da43045
33 hoursMerge "fconf: exclude fconf_dyn_cfg_getter.c from BL1_SOURCES" into integrationMark Dykes
33 hoursMerge "bl32: sp_min: reduce the alignment for fconf_populator" into integrationMark Dykes
33 hoursMerge "plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGS" into ↵Mark Dykes
33 hoursMerge "Build: introduce per-BL CPPFLAGS and ASFLAGS" into integrationMark Dykes
33 hoursdoc: Fix broken external link for Odroid C2Heinrich Schuchardt
The file README.odroid-c2 has been moved in the U-Boot repository. Reference the official uplink repository. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Change-Id: Ie72c7aefd6363a406f88ad2c87faee1c7a2125a3
38 hoursMerge "Create separate header for ARM specific SMCCC defines" into integrationOlivier Deprez
38 hoursMerge "Makefile: don't use $(CC) before value is explicit set" into integrationSandrine Bailleux
40 hoursMakefile: don't use $(CC) before value is explicit setAhmad Fatoum
Unless specified in the environment, $(CC) expands to some generic host C compiler like cc or c99. We set our own value for $(CC), but only few lines later. Move the first use of the $(CC) variable behind the definition to correct this. Change-Id: I45344e063d21ddfe22b7ad77954e85c1c46087bd Fixes: 1684b8733 ("Use clang assembler when clang compiler is used") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
40 hoursMerge "TF-A GICv3 driver: Introduce makefile" into integrationManish Pandey
44 hoursMerge "Tegra: fixup GIC init from the 'on_finish' handler" into integrationSandrine Bailleux
44 hoursMerge "Tegra186: increase memory mapped regions" into integrationSandrine Bailleux
45 hoursfconf: exclude fconf_dyn_cfg_getter.c from BL1_SOURCESMasahiro Yamada
fconf_dyn_cfg_getter.c calls FCONF_REGISTER_POPULATOR(), which populates the fconf_populator structure. However, bl1/bl1.ld.S does not have: __FCONF_POPULATOR_START__ = .; KEEP(*(.fconf_populator)) __FCONF_POPULATOR_END__ = .; So, this is not linked to bl1.elf We could change either bl1/bl1.lds.S or lib/fconf/fconf.mk to make them consistent. I chose to fix up fconf.mk to keep the current behavior. This is a groundwork to factor out the common code from linker scripts. Change-Id: I07b7ad4db4ec77b57acf1588fffd0b06306d7293 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
45 hoursbl32: sp_min: reduce the alignment for fconf_populatorMasahiro Yamada
sp_min.ld.S is used for aarch32. ALIGN(4) is used for alignment of the other structures. I do not think struct fconf_populator is a special case. Let's use ALIGN(4) here too. Perhaps, this is just a copy-paste mistake of commit 26d1e0c33098 ("fconf: necessary modifications to support fconf in BL31 & SP_MIN"). Change-Id: I29f4c68680842c1b5ef913934b4ccf378e9bfcfb Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
45 hoursplat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGSMasahiro Yamada
-D is a preprocessor flag that defines a macro. So, adding it to BL*_CPPFLAGS makes more sense. You can reference it not only from .c files but also from .S files. Change-Id: Ib4f2f27a3ed3eae476a6a32da7ab5225ad0649de Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
45 hoursBuild: introduce per-BL CPPFLAGS and ASFLAGSMasahiro Yamada
Currently, BL*_CFLAGS and BL*_LDFLAGS are supported. For completion, this adds BL*_CPPFLAGS and BL*_ASFLAGS. My main motivation is to pass -D<macro> to BL*_CPPFLAGS so that the macro can be used from all source files. Change-Id: I0ca1e4e26386bef7fed999af140ee7cce7c2f8ef Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2 daysxlat_tables_v2: add enable_mmu()Masahiro Yamada
enable_mmu_* has a different function name, so it is not handy in the shared code. enable_mmu() calls an appropriate one depending on the exception level. Change-Id: I0657968bfcb91c32733f75f9259f550a5c35b1c3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2 daysAdd get_current_el_maybe_constant()Masahiro Yamada
There are some cases where we want to run EL-dependent code in the shared code. We could use #ifdef, but it leaves slight possibility where we do not know the exception level at the build-time (e.g. library code). The counter approach is to use get_current_el(), but it is run-time detection, so all EL code is linked, some of which might be unneeded. This commit adds get_current_el_maybe_constant(). This is a static inline function that returns a constant value if we know the exception level at build-time. This is mostly the case. if (get_current_el_maybe_constant() == 1) { /* do something for EL1 */ } else if (get_current_el_maybe_constant() == 3) { /* do something for EL3 */ } If get_current_el_maybe_constant() is build-time constant, the compiler will optimize out the unreachable code. If such code is included from the library code, it is not built-time constant. In this case, it falls back to get_current_el(), so it still works. Change-Id: Idb03c20342a5b5173fe2d6b40e1fac7998675ad3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2 daysBuild: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C filesMasahiro Yamada
The build system defines the IMAGE_BL* macro when compiling each image. This is useful to distinguish which image the current file is being built for by using #if defined(IMAGE_BL2) or #if defined(IMAGE_BL31), or whatever. There are some cases where we are more interested in which exception level the current file is being built for. include/lib/cpus/{aarch32,aarch64}/cpu_macros.S defines IMAGE_AT_EL3, but we do not have it globally. Pass IMAGE_AT_EL1 or IMAGE_AT_EL3 to BL*_CFLAGS so that it is available from all C code. The library code (libc.a, libmbedtls.a, etc.) is exceptional cases, where the code can be shared between BL images. Other than that, we know the exception level at the build time, and this macro will be useful in the shared code. Change-Id: I7c8a1da10726906adfba981cfe8464dff111d6b0 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2 daysMerge "plat/sgm775: Add support for dynamic config using fconf" into integrationManish Pandey
2 daysplat/sgm775: Add support for dynamic config using fconfMadhukar Pappireddy
1. Necessary changes to platform makefile to include fw_config device tree and package it in fip.bin 2. Removed hw_config node from fw_config dts as there is no HW_CONFIG device tree source for sgm775 3. Added mbedtls_heap related properties for TBBR functionality Change-Id: I26b940c65b17ad2fb5537141f8649785bb0fd4ad Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
3 daysMerge "Flush dcache when storing timestamp" into integrationOlivier Deprez
3 daysMerge changes from topic "ddr_map" into integrationOlivier Deprez
* changes: stm32mp1: use stm32mp_get_ddr_ns_size() function stm32mp1: set XN attribute for some areas in BL2 stm32mp1: dynamically map DDR later and non-cacheable during its test stm32mp1: add a function to get non-secure DDR size
3 daysCreate separate header for ARM specific SMCCC definesManish V Badarkhe
Moved SMCCC defines from plat_arm.h to new <smccc_def.h> header and include this header in all ARM platforms. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I4cbc69c7b9307461de87b7c7bf200dd9b810e485
3 daysTF-A GICv3 driver: Introduce makefileAlexei Fedorov
This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
5 daysMerge "plat/arm/sgi: fix the incorrect check for SCMI channel ID" into ↵Manish Pandey
5 daysplat/arm/sgi: fix the incorrect check for SCMI channel IDAditya Angadi
Use ARRAY_SIZE macro instead of sizeof operator to obtain the maximum number of SCMI channels supported on the platform. Change-Id: Id922bb548af98ac99b4ac0c34e38e589e5a80b2d Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
5 daysMerge changes from topic "os/bl31-fpga-port" into integrationManish Pandey
* changes: plat/arm/board/arm_fpga: Compile with additional CPU libraries plat/arm/board/arm_fpga: Enable position-independent execution plat/arm/board/arm_fpga: Enable port for alternative cluster configurations plat/arm/board/arm_fpga: Initialize the Generic Interrupt Controller plat/arm/board/arm_fpga: Initialize the System Counter plat/arm/board/arm_fpga: Add PSCI implementation for FPGA images plat/arm/board/arm_fpga: Use preloaded BL33 alternative boot flow plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image
5 daysMerge "Changelog updates for recent commits" into integrationManish Pandey
5 daysMerge "doc: add spm and spmd related build options" into integrationManish Pandey
6 daysFlush dcache when storing timestampZelalem
On DynamIQ CPU FVPs, stats test cases are failing when hardware-assisted coherency is enabled due to a corrupt timestamp value. Investigation of the issue indicates that on these models the timestamp value is stored in cache instead of memory. This patch flushes the dcache when the timestamp is stored to make sure it is stored in memory. Change-Id: I05cd54ba5991a5a96dd07f1e08b5212273201411 Signed-off-by: Zelalem <zelalem.aweke@arm.com>
6 daysMerge "fconf: notify if fw_config dt is not used" into integrationOlivier Deprez
6 daysdoc: add spm and spmd related build optionsOlivier Deprez
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I93892dbe76611a7a4b852af3272a0e6271ae037b
6 daysfconf: notify if fw_config dt is not usedManish Pandey
Notify if fw_config dt is either not available or not loaded from fip. Change-Id: I4dfcbe5032503d97f532a3287c5312c581578b68 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
6 daysplat/arm/board/arm_fpga: Compile with additional CPU librariesOliver Swede
This change is part of the goal of enabling the port to be compatible with multiple FPGA images. BL31 behaves differently depending on whether or not the CPUs in the system use cache coherency, and as a result any CPU libraries that are compiled together must serve processors that are consistent in this regard. This compiles a different set of CPU libraries depending on whether or not the HW_ASSISTED_COHERENCY is enabled at build-time to indicate the CPUs support hardware-level support for cache coherency. This build flag is used in the makefile in the same way as the Arm FVP port. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I18300b4443176b89767015e3688c0f315a91c27e
6 daysplat/arm/board/arm_fpga: Enable position-independent executionOliver Swede
This allows the BL31 port to run with position-independent execution enabled so that it can be ran from any address in the system. This increases the flexibility of the image, allowing it to be ran from other locations rather than only its hardcoded absolute address (currently set to the typical DRAM base of 2GB). This may be useful for future images that describe system configurations with other memory layouts (e.g. where SRAM is included). It does this by setting ENABLE_PIE=1 and changing the absolute address to 0. The load address of bl31.bin can then be specified by the -l [load address] argument in the fpga-run command (additionally, this address is required by any preceding payloads that specify the start address. For ELF payloads this is usually extracted automatically by reading the entrypoint address in the header, however bl31.bin is a different file format so has this additional dependency). Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143
6 daysplat/arm/board/arm_fpga: Enable port for alternative cluster configurationsOliver Swede
This change is part of the goal of enabling the port to be compatible with multiple FPGA images. The BL31 port that is uploaded as a payload to the FPGA with an image should cater for a wide variety of system configurations. This patch makes the necessary changes to enable it to function with images whose cluster configurations may be larger (either by utilizing more clusters, more CPUs per cluster, more threads in each CPU, or a combination) than the initial image being used for testing. As part of this, the hard-coded values that configure the size of the array describing the topology of the power domain tree are increased to max. 8 clusters, max. 8 cores per cluster & max 4 threads per core. This ensures the port works with cluster configurations up to these sizes. When there are too many entries for the number of available PEs, e.g. if there is a variable number of CPUs between clusters, then there will be empty entries in the array. This is permitted and the PSCI library will still function as expected. While this increases its size, this shouldn't be an issue in the context of the size of BL31, and is worth the trade-off for the extra compatibility. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I7d4ae1e20b2e99fdbac428d122a2cf9445394363
6 daysplat/arm/board/arm_fpga: Initialize the Generic Interrupt ControllerOliver Swede
This initializes the GIC using the Arm GIC drivers in TF-A. The initial FPGA image uses a GIC600 implementation, and so that its power controller is enabled, this platform port calls the corresponding implementation-specific routines. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I88d5a073eead4b653b1ca73273182cd98a95e4c5
6 daysplat/arm/board/arm_fpga: Initialize the System CounterOliver Swede
This sets the frequency of the system counter so that the Delay Timer driver programs the correct value to CNTCRL. This value depends on the FPGA image being used, and is 10MHz for the initial test image. Once configured, the BL31 platform setup sequence then enables the system counter. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a
6 daysplat/arm/board/arm_fpga: Add PSCI implementation for FPGA imagesOliver Swede
This adds a basic PSCI implementation allow secondary CPUs to be released from an initial state and continue through to the warm boot entrypoint. Each secondary CPU is kept in a holding pen, whereby it polls the value representing its hold state, by reading this from an array that acts as a table for all the PEs. The hold states are initially set to 0 for all cores to indicate that the executing core should continue polling. To prevent the secondary CPUs from interfering with the platform's initialization, they are only updated by the primary CPU once the cold boot sequence has completed and fpga_pwr_domain_on(mpidr) is called. The polling target CPU will then read 1 (which indicates that it should branch to the warm reset entrypoint) and then jump to that address rather than continue polling. In addition to the initial polling behaviour of the secondary CPUs before their warm boot reset sequence, they are also placed in a low-power wfe() state at the end of each poll; accordingly, the PSCI fpga_pwr_domain_on(mpidr) function also signals an event to all cores (after updating the target CPU's hold entry) to wake them from this state, allowing any secondary CPUs that are still polling to check their hold state again. This method is in accordance with both the PSCI and Linux kernel recommendations, as the lessened overhead reduces the energy consumption associated with the busy-loop. The table of hold entries is implemented by a global array as shared SRAM (which is used by other platforms in similar implementations) is not available on the FPGA images. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I65cfd1892f8be1dfcb285f0e1e94e7a9870cdf5a
6 daysplat/arm/board/arm_fpga: Use preloaded BL33 alternative boot flowOliver Swede
This makes use of the PRELOADED_BL33_BASE flag to indicate to BL31 that the BL33 payload (kernel) has already been loaded and resides in memory; BL31 will then jump to the non-secure address. For this port the BL33 payload is the Linux kernel, and in accordance with the pre-kernel setup requirements (as specified in the `Booting AArch64 Linux' documentation: https://www.kernel.org/doc/Documentation/arm64/booting.txt), this change also sets up the primary CPU's registers x0-x3 so they are the expected values, which includes the address of the DTB at x0. An external linker script is currently required to combine BL31, the BL33 payload, and any other software images to create an ELF file that can be uploaded to the FPGA board along with the bit file. It therefore has dependencies on the value of PRELOADED_BL33_BASE (kernel base) and the DTB base (plus any other relevant base addresses used to distinguish the different ELF sections), both of which are set in this patch. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: If7ae8ee82d1e09fb05f553f6077ae13680dbf66b
6 daysplat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA imageOliver Swede
This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
6 daysMerge "FVP: Add BL2 hash calculation in BL1" into integrationMark Dykes
6 daysstm32mp1: use stm32mp_get_ddr_ns_size() functionYann Gautier
Instead of using dt_get_ddr_size() and withdrawing the secure and shared memory areas, use stm32mp_get_ddr_ns_size() function. Change-Id: I5608fd7873589ea0e1262ba7d2ee3e52b53d9a7d Signed-off-by: Yann Gautier <yann.gautier@st.com>