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Diffstat (limited to 'plat/hisilicon/poplar/bl1_plat_setup.c')
-rw-r--r--plat/hisilicon/poplar/bl1_plat_setup.c59
1 files changed, 26 insertions, 33 deletions
diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c
index f40bcf319f..c2adc44ecc 100644
--- a/plat/hisilicon/poplar/bl1_plat_setup.c
+++ b/plat/hisilicon/poplar/bl1_plat_setup.c
@@ -25,35 +25,39 @@
/* Data structure which holds the extents of the trusted RAM for BL1 */
static meminfo_t bl1_tzram_layout;
+static meminfo_t bl2_tzram_layout;
-meminfo_t *bl1_plat_sec_mem_layout(void)
+/*
+ * Cannot use default weak implementation in bl1_main.c because BL1 RW data is
+ * not at the top of the secure memory.
+ */
+int bl1_plat_handle_post_image_load(unsigned int image_id)
{
- return &bl1_tzram_layout;
-}
+ image_desc_t *image_desc;
+ entry_point_info_t *ep_info;
-#if LOAD_IMAGE_V2
-/*******************************************************************************
- * Function that takes a memory layout into which BL2 has been loaded and
- * populates a new memory layout for BL2 that ensures that BL1's data sections
- * resident in secure RAM are not visible to BL2.
- ******************************************************************************/
-void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
- meminfo_t *bl2_mem_layout)
-{
+ if (image_id != BL2_IMAGE_ID)
+ return 0;
+
+ /* Get the image descriptor */
+ image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
+ assert(image_desc != NULL);
+
+ /* Get the entry point info */
+ ep_info = &image_desc->ep_info;
- assert(bl1_mem_layout != NULL);
- assert(bl2_mem_layout != NULL);
+ bl2_tzram_layout.total_base = BL2_BASE;
+ bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE;
- /*
- * Cannot use default weak implementation in bl1main.c because
- * BL1 RW data is not at the top of bl1_mem_layout
- */
- bl2_mem_layout->total_base = BL2_BASE;
- bl2_mem_layout->total_size = BL32_LIMIT - BL2_BASE;
+ flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t));
- flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
+ ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout;
+
+ VERBOSE("BL1: BL2 memory layout address = %p\n",
+ (void *)&bl2_tzram_layout);
+
+ return 0;
}
-#endif /* LOAD_IMAGE_V2 */
void bl1_early_platform_setup(void)
{
@@ -64,17 +68,6 @@ void bl1_early_platform_setup(void)
bl1_tzram_layout.total_base = BL1_RW_BASE;
bl1_tzram_layout.total_size = BL1_RW_SIZE;
-#if !LOAD_IMAGE_V2
- /* Calculate how much RAM BL1 is using and how much remains free */
- bl1_tzram_layout.free_base = BL1_RW_BASE;
- bl1_tzram_layout.free_size = BL1_RW_SIZE;
-
- reserve_mem(&bl1_tzram_layout.free_base,
- &bl1_tzram_layout.free_size,
- BL1_RAM_BASE,
- BL1_RAM_LIMIT - BL1_RAM_BASE);
-#endif
-
INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
BL1_RAM_LIMIT - BL1_RAM_BASE);
}