diff options
41 files changed, 575 insertions, 258 deletions
diff --git a/docs/components/debugfs-design.rst b/docs/components/debugfs-design.rst index 06916f3d97..8ce1ba6a7a 100644 --- a/docs/components/debugfs-design.rst +++ b/docs/components/debugfs-design.rst @@ -15,8 +15,9 @@ Virtual filesystem ------------------ The core functionality lies in a virtual file system based on a 9p file server -interface (`Notes on the Plan 9 Kernel Source`_). The implementation permits -exposing virtual files, firmware drivers, and file blobs. +interface (`Notes on the Plan 9 Kernel Source`_ and +`Linux 9p remote filesystem protocol`_). +The implementation permits exposing virtual files, firmware drivers, and file blobs. Namespace ~~~~~~~~~ @@ -77,10 +78,10 @@ SMC interface ------------- The communication with the 9p layer in BL31 is made through an SMC conduit -(`SMC Calling Convention PDD`_), using a specific SiP Function Id. An NS shared -buffer is used to pass path string parameters, or e.g. to exchange data on a -read operation. Refer to `ARM SiP Services`_ for a description of the SMC -interface. +(`SMC Calling Convention PDD`_), using a specific SiP Function Id. An NS +shared buffer is used to pass path string parameters, or e.g. to exchange +data on a read operation. Refer to `ARM SiP Services`_ for a description +of the SMC interface. Security considerations ----------------------- @@ -114,17 +115,9 @@ The SMC interface is accessible from an NS environment, that is: - a Linux kernel driver running at NS-EL1 - a Linux userspace application through the kernel driver -References ----------- - -.. [#] `SMC Calling Convention PDD`_ -.. [#] `Notes on the Plan 9 Kernel Source`_ -.. [#] `Linux 9p remote filesystem protocol`_ -.. [#] `ARM SiP Services`_ - -------------- -*Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.* .. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ .. _Notes on the Plan 9 Kernel Source: http://lsub.org/who/nemo/9.pdf diff --git a/docs/components/index.rst b/docs/components/index.rst index 6a6b1b0d54..ae78b2bd1d 100644 --- a/docs/components/index.rst +++ b/docs/components/index.rst @@ -8,6 +8,7 @@ Components spd/index arm-sip-service + debugfs-design exception-handling fconf firmware-update diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index b4b4e0c82d..7186f98570 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -303,7 +303,7 @@ static void cp110_axi_attr_init(uintptr_t base) DOMAIN_SYSTEM_SHAREABLE); } -static void amb_bridge_init(uintptr_t base) +void cp110_amb_init(uintptr_t base) { uint32_t reg; @@ -399,7 +399,7 @@ void cp110_init(uintptr_t cp110_base, uint32_t stream_id) cp110_stream_id_init(cp110_base, stream_id); /* Open AMB bridge for comphy for CP0 & CP1*/ - amb_bridge_init(cp110_base); + cp110_amb_init(cp110_base); /* Reset RTC if needed */ cp110_rtc_init(cp110_base); @@ -411,7 +411,7 @@ void cp110_ble_init(uintptr_t cp110_base) #if PCI_EP_SUPPORT INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); - amb_bridge_init(cp110_base); + cp110_amb_init(cp110_base); /* Configure PCIe clock */ cp110_pcie_clk_cfg(cp110_base); diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h index 3686257d3d..f8cd26b126 100644 --- a/include/drivers/marvell/mochi/cp110_setup.h +++ b/include/drivers/marvell/mochi/cp110_setup.h @@ -51,5 +51,6 @@ static inline uint32_t cp110_rev_id_get(uintptr_t base) void cp110_init(uintptr_t cp110_base, uint32_t stream_id); void cp110_ble_init(uintptr_t cp110_base); +void cp110_amb_init(uintptr_t base); #endif /* CP110_SETUP_H */ diff --git a/plat/arm/board/corstone700/corstone700_stack_protector.c b/plat/arm/board/corstone700/corstone700_stack_protector.c new file mode 100644 index 0000000000..6fd09da5b6 --- /dev/null +++ b/plat/arm/board/corstone700/corstone700_stack_protector.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <arch_helpers.h> +#include <plat/common/platform.h> + +static uint32_t plat_generate_random_number(void) +{ + uintptr_t return_addr = (uintptr_t)__builtin_return_address(0U); + uintptr_t frame_addr = (uintptr_t)__builtin_frame_address(0U); + uint64_t cntpct = read_cntpct_el0(); + + /* Generate 32-bit pattern: saving the 2 least significant bytes + * in random_lo and random_hi + */ + uint16_t random_lo = (uint16_t)( + (((uint64_t)return_addr) << 13) ^ frame_addr ^ cntpct + ); + + uint16_t random_hi = (uint16_t)( + (((uint64_t)frame_addr) << 15) ^ return_addr ^ cntpct + ); + + return (((uint32_t)random_hi) << 16) | random_lo; +} + +u_register_t plat_get_stack_protector_canary(void) +{ + return plat_generate_random_number(); /* a 32-bit pattern is returned */ +} diff --git a/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk index 57e1ec3e42..acee6c39c5 100644 --- a/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk +++ b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -15,4 +15,10 @@ BL32_SOURCES += drivers/cfi/v2m/v2m_flash.c \ plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c \ ${CORSTONE700_GIC_SOURCES} +ifneq (${ENABLE_STACK_PROTECTOR},0) + ifneq (${ENABLE_STACK_PROTECTOR},none) + BL32_SOURCES += plat/arm/board/corstone700/corstone700_stack_protector.c + endif +endif + include plat/arm/common/sp_min/arm_sp_min.mk diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_fw_config.dts b/plat/arm/board/rddaniel/fdts/rddaniel_fw_config.dts new file mode 100644 index 0000000000..81e4cc12d3 --- /dev/null +++ b/plat/arm/board/rddaniel/fdts/rddaniel_fw_config.dts @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <export/common/tbbr/tbbr_img_def_exp.h> + +/dts-v1/; + +/ { + dtb-registry { + compatible = "arm,dyn_cfg-dtb_registry"; + + /* tb_fw_config is temporarily contained on this dtb */ + tb_fw-config { + load-address = <0x0 0x4001010>; + max-size = <0x200>; + id = <TB_FW_CONFIG_ID>; + }; + + nt_fw-config { + load-address = <0x0 0xFEF00000>; + max-size = <0x0100000>; + id = <NT_FW_CONFIG_ID>; + }; + }; + + tb_fw-config { + compatible = "arm,tb_fw"; + + /* Disable authentication for development */ + disable_auth = <0x0>; + + /* + * The following two entries are placeholders for Mbed TLS + * heap information. The default values don't matter since + * they will be overwritten by BL1. + * In case of having shared Mbed TLS heap between BL1 and BL2, + * BL1 will populate these two properties with the respective + * info about the shared heap. This info will be available for + * BL2 in order to locate and re-use the heap. + */ + mbedtls_heap_addr = <0x0 0x0>; + mbedtls_heap_size = <0x0>; + }; +}; diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts b/plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts deleted file mode 100644 index 9acec137e7..0000000000 --- a/plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/dts-v1/; - -/ { - /* Platform Config */ - compatible = "arm,tb_fw"; - nt_fw_config_addr = <0x0 0xFEF00000>; - nt_fw_config_max_size = <0x0100000>; - - /* - * The following two entries are placeholders for Mbed TLS - * heap information. The default values don't matter since - * they will be overwritten by BL1. - * In case of having shared Mbed TLS heap between BL1 and BL2, - * BL1 will populate these two properties with the respective - * info about the shared heap. This info will be available for - * BL2 in order to locate and re-use the heap. - */ - mbedtls_heap_addr = <0x0 0x0>; - mbedtls_heap_size = <0x0>; -}; diff --git a/plat/arm/board/rddaniel/platform.mk b/plat/arm/board/rddaniel/platform.mk index 67f57779a2..c7e3c7dd86 100644 --- a/plat/arm/board/rddaniel/platform.mk +++ b/plat/arm/board/rddaniel/platform.mk @@ -28,8 +28,8 @@ BL31_SOURCES += ${SGI_CPU_SOURCES} \ plat/arm/common/arm_nor_psci_mem_protect.c # Add the FDT_SOURCES and options for Dynamic Config -FDT_SOURCES += ${RDDANIEL_BASE}/fdts/${PLAT}_tb_fw_config.dts -TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb +FDT_SOURCES += ${RDDANIEL_BASE}/fdts/${PLAT}_fw_config.dts +TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb # Add the TB_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config)) diff --git a/plat/arm/board/rde1edge/fdts/rde1edge_fw_config.dts b/plat/arm/board/rde1edge/fdts/rde1edge_fw_config.dts new file mode 100644 index 0000000000..2719ab4159 --- /dev/null +++ b/plat/arm/board/rde1edge/fdts/rde1edge_fw_config.dts @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <export/common/tbbr/tbbr_img_def_exp.h> + +/dts-v1/; + +/ { + dtb-registry { + compatible = "arm,dyn_cfg-dtb_registry"; + + /* tb_fw_config is temporarily contained on this dtb */ + tb_fw-config { + load-address = <0x0 0x4001010>; + max-size = <0x200>; + id = <TB_FW_CONFIG_ID>; + }; + + nt_fw-config { + load-address = <0x0 0xFEF00000>; + max-size = <0x0100000>; + id = <NT_FW_CONFIG_ID>; + }; + }; + + tb_fw-config { + compatible = "arm,tb_fw"; + + /* Disable authentication for development */ + disable_auth = <0x0>; + + /* + * The following two entries are placeholders for Mbed TLS + * heap information. The default values don't matter since + * they will be overwritten by BL1. + * In case of having shared Mbed TLS heap between BL1 and BL2, + * BL1 will populate these two properties with the respective + * info about the shared heap. This info will be available for + * BL2 in order to locate and re-use the heap. + */ + mbedtls_heap_addr = <0x0 0x0>; + mbedtls_heap_size = <0x0>; + }; +}; diff --git a/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts b/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts deleted file mode 100644 index 766dc00f55..0000000000 --- a/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/dts-v1/; - -/ { - /* Platform Config */ - compatible = "arm,tb_fw"; - nt_fw_config_addr = <0x0 0xFEF00000>; - nt_fw_config_max_size = <0x0100000>; - /* - * The following two entries are placeholders for Mbed TLS - * heap information. The default values don't matter since - * they will be overwritten by BL1. - * In case of having shared Mbed TLS heap between BL1 and BL2, - * BL1 will populate these two properties with the respective - * info about the shared heap. This info will be available for - * BL2 in order to locate and re-use the heap. - */ - mbedtls_heap_addr = <0x0 0x0>; - mbedtls_heap_size = <0x0>; -}; diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk index 88aa634b86..1a4dd17d18 100644 --- a/plat/arm/board/rde1edge/platform.mk +++ b/plat/arm/board/rde1edge/platform.mk @@ -35,8 +35,8 @@ BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c endif # Add the FDT_SOURCES and options for Dynamic Config -FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts -TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb +FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_fw_config.dts +TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb # Add the TB_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config)) diff --git a/plat/arm/board/rdn1edge/fdts/rdn1edge_fw_config.dts b/plat/arm/board/rdn1edge/fdts/rdn1edge_fw_config.dts new file mode 100644 index 0000000000..ba74b75bcc --- /dev/null +++ b/plat/arm/board/rdn1edge/fdts/rdn1edge_fw_config.dts @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <export/common/tbbr/tbbr_img_def_exp.h> + +/dts-v1/; +/ { + dtb-registry { + compatible = "arm,dyn_cfg-dtb_registry"; + + /* tb_fw_config is temporarily contained on this dtb */ + tb_fw-config { + load-address = <0x0 0x80001010>; + max-size = <0x200>; + id = <TB_FW_CONFIG_ID>; + }; + + nt_fw-config { + load-address = <0x0 0xFEF00000>; + max-size = <0x0100000>; + id = <NT_FW_CONFIG_ID>; + }; + }; + + tb_fw-config { + compatible = "arm,tb_fw"; + + /* Disable authentication for development */ + disable_auth = <0x0>; + + /* + * The following two entries are placeholders for Mbed TLS + * heap information. The default values don't matter since + * they will be overwritten by BL1. + * In case of having shared Mbed TLS heap between BL1 and BL2, + * BL1 will populate these two properties with the respective + * info about the shared heap. This info will be available for + * BL2 in order to locate and re-use the heap. + */ + mbedtls_heap_addr = <0x0 0x0>; + mbedtls_heap_size = <0x0>; + }; +}; + diff --git a/plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts b/plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts deleted file mode 100644 index b14d7adca9..0000000000 --- a/plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/dts-v1/; - -/ { - /* Platform Config */ - compatible = "arm,tb_fw"; - nt_fw_config_addr = <0x0 0xFEF00000>; - nt_fw_config_max_size = <0x0100000>; - /* - * The following two entries are placeholders for Mbed TLS - * heap information. The default values don't matter since - * they will be overwritten by BL1. - * In case of having shared Mbed TLS heap between BL1 and BL2, - * BL1 will populate these two properties with the respective - * info about the shared heap. This info will be available for - * BL2 in order to locate and re-use the heap. - */ - mbedtls_heap_addr = <0x0 0x0>; - mbedtls_heap_size = <0x0>; -}; diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk index 04f70f3f25..99bb71d792 100644 --- a/plat/arm/board/rdn1edge/platform.mk +++ b/plat/arm/board/rdn1edge/platform.mk @@ -39,8 +39,8 @@ endif BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 # Add the FDT_SOURCES and options for Dynamic Config -FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts -TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb +FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_fw_config.dts +TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb # Add the TB_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config)) diff --git a/plat/arm/board/sgi575/fdts/sgi575_fw_config.dts b/plat/arm/board/sgi575/fdts/sgi575_fw_config.dts new file mode 100644 index 0000000000..605cc08b7f --- /dev/null +++ b/plat/arm/board/sgi575/fdts/sgi575_fw_config.dts @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <export/common/tbbr/tbbr_img_def_exp.h> + +/dts-v1/; + +/ { + dtb-registry { + compatible = "arm,dyn_cfg-dtb_registry"; + + /* tb_fw_config is temporarily contained on this dtb */ + tb_fw-config { + load-address = <0x0 0x4001010>; + max-size = <0x200>; + id = <TB_FW_CONFIG_ID>; + }; + + nt_fw-config { + load-address = <0x0 0xFEF00000>; + max-size = <0x0100000>; + id = <NT_FW_CONFIG_ID>; + }; + }; + + tb_fw-config { + compatible = "arm,tb_fw"; + + /* Disable authentication for development */ + disable_auth = <0x0>; + + /* + * The following two entries are placeholders for Mbed TLS + * heap information. The default values don't matter since + * they will be overwritten by BL1. + * In case of having shared Mbed TLS heap between BL1 and BL2, + * BL1 will populate these two properties with the respective + * info about the shared heap. This info will be available for + * BL2 in order to locate and re-use the heap. + */ + mbedtls_heap_addr = <0x0 0x0>; + mbedtls_heap_size = <0x0>; + }; +}; diff --git a/plat/arm/board/sgi575/fdts/sgi575_tb_fw_config.dts b/plat/arm/board/sgi575/fdts/sgi575_tb_fw_config.dts deleted file mode 100644 index b14d7adca9..0000000000 --- a/plat/arm/board/sgi575/fdts/sgi575_tb_fw_config.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/dts-v1/; - -/ { - /* Platform Config */ - compatible = "arm,tb_fw"; - nt_fw_config_addr = <0x0 0xFEF00000>; - nt_fw_config_max_size = <0x0100000>; - /* - * The following two entries are placeholders for Mbed TLS - * heap information. The default values don't matter since - * they will be overwritten by BL1. - * In case of having shared Mbed TLS heap between BL1 and BL2, - * BL1 will populate these two properties with the respective - * info about the shared heap. This info will be available for - * BL2 in order to locate and re-use the heap. - */ - mbedtls_heap_addr = <0x0 0x0>; - mbedtls_heap_size = <0x0>; -}; diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk index 76cc4e2c2e..d91f829ee3 100644 --- a/plat/arm/board/sgi575/platform.mk +++ b/plat/arm/board/sgi575/platform.mk @@ -35,8 +35,8 @@ BL2_SOURCES += ${SGI575_BASE}/sgi575_trusted_boot.c endif # Add the FDT_SOURCES and options for Dynamic Config -FDT_SOURCES += ${SGI575_BASE}/fdts/${PLAT}_tb_fw_config.dts -TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb +FDT_SOURCES += ${SGI575_BASE}/fdts/${PLAT}_fw_config.dts +TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb # Add the TB_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config)) diff --git a/plat/arm/board/sgm775/fdts/sgm775_fw_config.dts b/plat/arm/board/sgm775/fdts/sgm775_fw_config.dts new file mode 100644 index 0000000000..a0d0ea90e1 --- /dev/null +++ b/plat/arm/board/sgm775/fdts/sgm775_fw_config.dts @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <export/common/tbbr/tbbr_img_def_exp.h> + +/dts-v1/; + +/ { + dtb-registry { + compatible = "arm,dyn_cfg-dtb_registry"; + + /* tb_fw_config is temporarily contained on this dtb */ + tb_fw-config { + load-address = <0x0 0x4001010>; + max-size = <0x200>; + id = <TB_FW_CONFIG_ID>; + }; + + hw-config { + load-address = <0x0 0x83000000>; + max-size = <0x01000000>; + id = <HW_CONFIG_ID>; + }; + }; + + tb_fw-config { + compatible = "arm,tb_fw"; + + /* Disable authentication for development */ + disable_auth = <0x0>; + }; +}; diff --git a/plat/arm/board/sgm775/fdts/sgm775_tb_fw_config.dts b/plat/arm/board/sgm775/fdts/sgm775_tb_fw_config.dts deleted file mode 100644 index 95025493bb..0000000000 --- a/plat/arm/board/sgm775/fdts/sgm775_tb_fw_config.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/dts-v1/; - -/ { - /* Platform Config */ - plat_arm_bl2 { - compatible = "arm,tb_fw"; - hw_config_addr = <0x0 0x83000000>; - hw_config_max_size = <0x01000000>; - }; -}; diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk index f096ca53d3..355b9ee2ce 100644 --- a/plat/arm/board/sgm775/platform.mk +++ b/plat/arm/board/sgm775/platform.mk @@ -8,7 +8,7 @@ include plat/arm/css/sgm/sgm-common.mk SGM775_BASE= plat/arm/board/sgm775 -FDT_SOURCES += ${SGM775_BASE}/fdts/sgm775_tb_fw_config.dts +FDT_SOURCES += ${SGM775_BASE}/fdts/sgm775_fw_config.dts PLAT_INCLUDES +=-I${SGM775_BASE}/include/ diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index 9587d4859f..f32820777f 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -46,7 +46,7 @@ const mmap_region_t agilex_plat_mmap[] = { {0}, }; -boot_source_type boot_source; +boot_source_type boot_source = BOOT_SOURCE; void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, u_register_t x2, u_register_t x4) @@ -59,7 +59,6 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, if (socfpga_get_handoff(&reverse_handoff_ptr)) return; config_pinmux(&reverse_handoff_ptr); - boot_source = reverse_handoff_ptr.boot_source; config_clkmgr_handoff(&reverse_handoff_ptr); enable_nonsecure_access(); diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index b4e09210fb..6c9d81ceb1 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -12,6 +12,7 @@ /* Platform Setting */ #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX +#define BOOT_SOURCE BOOT_SOURCE_SDMMC /* Register Mapping */ #define SOCFPGA_MMC_REG_BASE 0xff808000 diff --git a/plat/intel/soc/common/include/socfpga_handoff.h b/plat/intel/soc/common/include/socfpga_handoff.h index 889d137679..ba0f7f3777 100644 --- a/plat/intel/soc/common/include/socfpga_handoff.h +++ b/plat/intel/soc/common/include/socfpga_handoff.h @@ -125,7 +125,6 @@ typedef struct handoff_t { uint32_t misc_magic; uint32_t misc_length; uint32_t _pad_0x618_0x620[2]; - uint32_t boot_source; } handoff; int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 7d183db0d7..78ca253e79 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -45,7 +45,7 @@ const mmap_region_t plat_stratix10_mmap[] = { {0}, }; -boot_source_type boot_source; +boot_source_type boot_source = BOOT_SOURCE; void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, u_register_t x2, u_register_t x4) @@ -58,7 +58,6 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, if (socfpga_get_handoff(&reverse_handoff_ptr)) return; config_pinmux(&reverse_handoff_ptr); - boot_source = reverse_handoff_ptr.boot_source; config_clkmgr_handoff(&reverse_handoff_ptr); enable_nonsecure_access(); diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h index 9dc51514cb..a2bd57b088 100644 --- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -10,7 +10,8 @@ #include <platform_def.h> /* Platform Setting */ -#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 +#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 +#define BOOT_SOURCE BOOT_SOURCE_SDMMC /* Register Mapping */ #define SOCFPGA_MMC_REG_BASE 0xff808000 diff --git a/plat/marvell/a8k/common/mss/mss_a8k.mk b/plat/marvell/a8k/common/mss/mss_a8k.mk index 58f23d8dd8..efd03c5a2f 100644 --- a/plat/marvell/a8k/common/mss/mss_a8k.mk +++ b/plat/marvell/a8k/common/mss/mss_a8k.mk @@ -8,7 +8,8 @@ PLAT_MARVELL := plat/marvell A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss -BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c +BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c \ + $(MARVELL_MOCHI_DRV) BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c diff --git a/plat/marvell/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/a8k/common/mss/mss_bl2_setup.c index 728ee54a05..09b8446fa3 100644 --- a/plat/marvell/a8k/common/mss/mss_bl2_setup.c +++ b/plat/marvell/a8k/common/mss/mss_bl2_setup.c @@ -74,6 +74,12 @@ static int bl2_plat_mmap_init(void) /* Set the default target id to PIDI */ mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID); + /* Open AMB bridge required for MG access */ + cp110_amb_init(MVEBU_CP_REGS_BASE(0)); + + if (CP_COUNT == 2) + cp110_amb_init(MVEBU_CP_REGS_BASE(1)); + return 0; } diff --git a/plat/marvell/common/mss/mss_scp_bl2_format.h b/plat/marvell/common/mss/mss_scp_bl2_format.h index 7cf8d3201d..7150f0a063 100644 --- a/plat/marvell/common/mss/mss_scp_bl2_format.h +++ b/plat/marvell/common/mss/mss_scp_bl2_format.h @@ -8,7 +8,7 @@ #ifndef MSS_SCP_BL2_FORMAT_H #define MSS_SCP_BL2_FORMAT_H -#define MAX_NR_OF_FILES 5 +#define MAX_NR_OF_FILES 8 #define FILE_MAGIC 0xddd01ff #define HEADER_VERSION 0x1 @@ -31,6 +31,7 @@ enum cm3_t { MSS_CP3, MG_CP0, MG_CP1, + MG_CP2, }; typedef struct img_header { diff --git a/plat/marvell/common/mss/mss_scp_bootloader.c b/plat/marvell/common/mss/mss_scp_bootloader.c index 7e442c6154..4473d81e13 100644 --- a/plat/marvell/common/mss/mss_scp_bootloader.c +++ b/plat/marvell/common/mss/mss_scp_bootloader.c @@ -42,6 +42,8 @@ #define MSS_HANDSHAKE_TIMEOUT 50 +#define MG_CM3_SRAM_BASE(CP) (MVEBU_CP_REGS_BASE(CP) + 0x100000) + static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl) { int timeout = MSS_HANDSHAKE_TIMEOUT; @@ -59,6 +61,28 @@ static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl) return 0; } +static int mg_image_load(uintptr_t src_addr, uint32_t size, uintptr_t mg_regs) +{ + if (size > MG_SRAM_SIZE) { + ERROR("image is too big to fit into MG CM3 memory\n"); + return 1; + } + + NOTICE("Loading MG image from address 0x%lx Size 0x%x to MG at 0x%lx\n", + src_addr, size, mg_regs); + + /* Copy image to MG CM3 SRAM */ + memcpy((void *)mg_regs, (void *)src_addr, size); + + /* + * Don't release MG CM3 from reset - it will be done by next step + * bootloader (e.g. U-Boot), when appriopriate device-tree setup (which + * has enabeld 802.3. auto-neg) will be choosen. + */ + + return 0; +} + static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs) { uint32_t i, loop_num, timeout; @@ -225,12 +249,21 @@ static int load_img_to_cm3(enum cm3_t cm3_type, } break; case MG_CP0: - /* TODO: */ - NOTICE("Load image to CP0 MG not supported\n"); - break; case MG_CP1: - /* TODO: */ - NOTICE("Load image to CP1 MG not supported\n"); + case MG_CP2: + cp_index = cm3_type - MG_CP0; + if (bl2_plat_get_cp_count(0) <= cp_index) { + NOTICE("Skipping MG CP%d related image\n", + cp_index); + break; + } + NOTICE("Load image to CP%d MG\n", cp_index); + ret = mg_image_load(single_img, image_size, + MG_CM3_SRAM_BASE(cp_index)); + if (ret != 0) { + ERROR("SCP Image load failed\n"); + return -1; + } break; default: ERROR("SCP_BL2 wrong img format (cm3_type=%d)\n", cm3_type); @@ -261,7 +294,7 @@ static int split_and_load_bl2_image(void *image) } if (file_hdr->nr_of_imgs > MAX_NR_OF_FILES) { - ERROR("SCP_BL2 concatenated image contains to many images\n"); + ERROR("SCP_BL2 concatenated image contains too many images\n"); return -1; } diff --git a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c index 4f58b683c8..091a6f7a96 100644 --- a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c +++ b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c @@ -4,16 +4,25 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <errno.h> + #include <platform_def.h> #include <common/bl_common.h> #include <lib/xlat_tables/xlat_mmu_helpers.h> +#include <plat/common/platform.h> #include "../uniphier.h" +static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN; + void tsp_early_platform_setup(void) { - uniphier_console_setup(); + uniphier_soc = uniphier_get_soc_id(); + if (uniphier_soc == UNIPHIER_SOC_UNKNOWN) + plat_error_handler(-ENOTSUP); + + uniphier_console_setup(uniphier_soc); } void tsp_platform_setup(void) @@ -22,6 +31,6 @@ void tsp_platform_setup(void) void tsp_plat_arch_setup(void) { - uniphier_mmap_setup(); + uniphier_mmap_setup(uniphier_soc); enable_mmu_el1(0); } diff --git a/plat/socionext/uniphier/uniphier.h b/plat/socionext/uniphier/uniphier.h index 729dc5caad..ee520ad23f 100644 --- a/plat/socionext/uniphier/uniphier.h +++ b/plat/socionext/uniphier/uniphier.h @@ -25,7 +25,8 @@ unsigned int uniphier_get_boot_device(unsigned int soc); #define UNIPHIER_BOOT_DEVICE_EMMC 0 #define UNIPHIER_BOOT_DEVICE_NAND 1 #define UNIPHIER_BOOT_DEVICE_NOR 2 -#define UNIPHIER_BOOT_DEVICE_USB 3 +#define UNIPHIER_BOOT_DEVICE_SD 3 +#define UNIPHIER_BOOT_DEVICE_USB 4 #define UNIPHIER_BOOT_DEVICE_RSV 0xffffffff unsigned int uniphier_get_boot_master(unsigned int soc); @@ -34,11 +35,13 @@ unsigned int uniphier_get_boot_master(unsigned int soc); #define UNIPHIER_BOOT_MASTER_SCP 1 #define UNIPHIER_BOOT_MASTER_EXT 2 -void uniphier_console_setup(void); +void uniphier_console_setup(unsigned int soc); struct io_block_dev_spec; -int uniphier_emmc_init(struct io_block_dev_spec **block_dev_spec); -int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec); +int uniphier_emmc_init(unsigned int soc, + struct io_block_dev_spec **block_dev_spec); +int uniphier_nand_init(unsigned int soc, + struct io_block_dev_spec **block_dev_spec); int uniphier_usb_init(unsigned int soc, struct io_block_dev_spec **block_dev_spec); @@ -54,7 +57,7 @@ void uniphier_scp_open_com(void); void uniphier_scp_system_off(void); void uniphier_scp_system_reset(void); -void uniphier_mmap_setup(void); +void uniphier_mmap_setup(unsigned int soc); void uniphier_cci_init(unsigned int soc); void uniphier_cci_enable(void); @@ -66,6 +69,8 @@ void uniphier_gic_cpuif_enable(void); void uniphier_gic_cpuif_disable(void); void uniphier_gic_pcpu_init(void); +void uniphier_psci_init(unsigned int soc); + unsigned int uniphier_calc_core_pos(u_register_t mpidr); #endif /* UNIPHIER_H */ diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c index 11d837cf4f..7a7f78681e 100644 --- a/plat/socionext/uniphier/uniphier_bl2_setup.c +++ b/plat/socionext/uniphier/uniphier_bl2_setup.c @@ -25,39 +25,37 @@ #define UNIPHIER_IMAGE_BUF_SIZE 0x00100000UL static uintptr_t uniphier_mem_base = UNIPHIER_MEM_BASE; +static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN; static int uniphier_bl2_kick_scp; void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, u_register_t x2, u_register_t x3) { - uniphier_console_setup(); + uniphier_soc = uniphier_get_soc_id(); + if (uniphier_soc == UNIPHIER_SOC_UNKNOWN) + plat_error_handler(-ENOTSUP); + + uniphier_console_setup(uniphier_soc); } void bl2_el3_plat_arch_setup(void) { - unsigned int soc; int skip_scp = 0; int ret; - uniphier_mmap_setup(); + uniphier_mmap_setup(uniphier_soc); enable_mmu_el3(0); /* add relocation offset (run-time-address - link-address) */ uniphier_mem_base += BL_CODE_BASE - BL2_BASE; - soc = uniphier_get_soc_id(); - if (soc == UNIPHIER_SOC_UNKNOWN) { - ERROR("unsupported SoC\n"); - plat_error_handler(-ENOTSUP); - } - - ret = uniphier_io_setup(soc, uniphier_mem_base); + ret = uniphier_io_setup(uniphier_soc, uniphier_mem_base); if (ret) { ERROR("failed to setup io devices\n"); plat_error_handler(ret); } - switch (uniphier_get_boot_master(soc)) { + switch (uniphier_get_boot_master(uniphier_soc)) { case UNIPHIER_BOOT_MASTER_THIS: INFO("Booting from this SoC\n"); skip_scp = 1; diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c index 47f2378bcd..f2f0b298a7 100644 --- a/plat/socionext/uniphier/uniphier_bl31_setup.c +++ b/plat/socionext/uniphier/uniphier_bl31_setup.c @@ -21,6 +21,7 @@ static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; +static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN; entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) { @@ -37,7 +38,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head; - uniphier_console_setup(); + uniphier_soc = uniphier_get_soc_id(); + if (uniphier_soc == UNIPHIER_SOC_UNKNOWN) + plat_error_handler(-ENOTSUP); + + uniphier_console_setup(uniphier_soc); while (bl_params) { if (bl_params->image_id == BL32_IMAGE_ID) @@ -53,32 +58,34 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, panic(); } -#define UNIPHIER_SYS_CNTCTL_BASE 0x60E00000 +static const uintptr_t uniphier_cntctl_base[] = { + [UNIPHIER_SOC_LD11] = 0x60e00000, + [UNIPHIER_SOC_LD20] = 0x60e00000, + [UNIPHIER_SOC_PXS3] = 0x60e00000, +}; void bl31_platform_setup(void) { - unsigned int soc; + uintptr_t cntctl_base; - soc = uniphier_get_soc_id(); - if (soc == UNIPHIER_SOC_UNKNOWN) { - ERROR("unsupported SoC\n"); - plat_error_handler(-ENOTSUP); - } - - uniphier_cci_init(soc); + uniphier_cci_init(uniphier_soc); uniphier_cci_enable(); /* Initialize the GIC driver, cpu and distributor interfaces */ - uniphier_gic_driver_init(soc); + uniphier_gic_driver_init(uniphier_soc); uniphier_gic_init(); + assert(uniphier_soc < ARRAY_SIZE(uniphier_cntctl_base)); + cntctl_base = uniphier_cntctl_base[uniphier_soc]; + /* Enable and initialize the System level generic timer */ - mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF, - CNTCR_FCREQ(0U) | CNTCR_EN); + mmio_write_32(cntctl_base + CNTCR_OFF, CNTCR_FCREQ(0U) | CNTCR_EN); + + uniphier_psci_init(uniphier_soc); } void bl31_plat_arch_setup(void) { - uniphier_mmap_setup(); + uniphier_mmap_setup(uniphier_soc); enable_mmu_el3(0); } diff --git a/plat/socionext/uniphier/uniphier_boot_device.c b/plat/socionext/uniphier/uniphier_boot_device.c index 462c0859ce..36a9908be9 100644 --- a/plat/socionext/uniphier/uniphier_boot_device.c +++ b/plat/socionext/uniphier/uniphier_boot_device.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,22 +13,29 @@ #include "uniphier.h" -#define UNIPHIER_PINMON0 0x5f900100 -#define UNIPHIER_PINMON2 0x5f900108 +#define UNIPHIER_PINMON0 0x0 +#define UNIPHIER_PINMON2 0x8 -static int uniphier_ld11_is_usb_boot(uint32_t pinmon) +static const uintptr_t uniphier_pinmon_base[] = { + [UNIPHIER_SOC_LD11] = 0x5f900100, + [UNIPHIER_SOC_LD20] = 0x5f900100, + [UNIPHIER_SOC_PXS3] = 0x5f900100, +}; + +static bool uniphier_ld11_is_usb_boot(uint32_t pinmon) { return !!(~pinmon & 0x00000080); } -static int uniphier_ld20_is_usb_boot(uint32_t pinmon) +static bool uniphier_ld20_is_usb_boot(uint32_t pinmon) { return !!(~pinmon & 0x00000780); } -static int uniphier_pxs3_is_usb_boot(uint32_t pinmon) +static bool uniphier_pxs3_is_usb_boot(uint32_t pinmon) { - uint32_t pinmon2 = mmio_read_32(UNIPHIER_PINMON2); + uintptr_t pinmon_base = uniphier_pinmon_base[UNIPHIER_SOC_PXS3]; + uint32_t pinmon2 = mmio_read_32(pinmon_base + UNIPHIER_PINMON2); return !!(pinmon2 & BIT(31)); } @@ -106,20 +113,25 @@ static unsigned int uniphier_pxs3_get_boot_device(uint32_t pinmon) } struct uniphier_boot_device_info { - int (*is_usb_boot)(uint32_t pinmon); + bool have_boot_swap; + bool (*is_sd_boot)(uint32_t pinmon); + bool (*is_usb_boot)(uint32_t pinmon); unsigned int (*get_boot_device)(uint32_t pinmon); }; static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { [UNIPHIER_SOC_LD11] = { + .have_boot_swap = true, .is_usb_boot = uniphier_ld11_is_usb_boot, .get_boot_device = uniphier_ld11_get_boot_device, }, [UNIPHIER_SOC_LD20] = { + .have_boot_swap = true, .is_usb_boot = uniphier_ld20_is_usb_boot, .get_boot_device = uniphier_ld11_get_boot_device, }, [UNIPHIER_SOC_PXS3] = { + .have_boot_swap = true, .is_usb_boot = uniphier_pxs3_is_usb_boot, .get_boot_device = uniphier_pxs3_get_boot_device, }, @@ -128,17 +140,24 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { unsigned int uniphier_get_boot_device(unsigned int soc) { const struct uniphier_boot_device_info *info; + uintptr_t pinmon_base; uint32_t pinmon; assert(soc < ARRAY_SIZE(uniphier_boot_device_info)); info = &uniphier_boot_device_info[soc]; - pinmon = mmio_read_32(UNIPHIER_PINMON0); + assert(soc < ARRAY_SIZE(uniphier_boot_device_info)); + pinmon_base = uniphier_pinmon_base[soc]; + + pinmon = mmio_read_32(pinmon_base + UNIPHIER_PINMON0); - if (!(pinmon & BIT(29))) + if (info->have_boot_swap && !(pinmon & BIT(29))) return UNIPHIER_BOOT_DEVICE_NOR; - if (info->is_usb_boot(pinmon)) + if (info->is_sd_boot && info->is_sd_boot(pinmon)) + return UNIPHIER_BOOT_DEVICE_SD; + + if (info->is_usb_boot && info->is_usb_boot(pinmon)) return UNIPHIER_BOOT_DEVICE_USB; return info->get_boot_device(pinmon); @@ -155,7 +174,12 @@ unsigned int uniphier_get_boot_master(unsigned int soc) assert(soc < ARRAY_SIZE(uniphier_have_onchip_scp)); if (uniphier_have_onchip_scp[soc]) { - if (mmio_read_32(UNIPHIER_PINMON0) & BIT(27)) + uintptr_t pinmon_base; + + assert(soc < ARRAY_SIZE(uniphier_boot_device_info)); + pinmon_base = uniphier_pinmon_base[soc]; + + if (mmio_read_32(pinmon_base + UNIPHIER_PINMON0) & BIT(27)) return UNIPHIER_BOOT_MASTER_THIS; else return UNIPHIER_BOOT_MASTER_SCP; diff --git a/plat/socionext/uniphier/uniphier_console_setup.c b/plat/socionext/uniphier/uniphier_console_setup.c index 64ee797148..1851e4da54 100644 --- a/plat/socionext/uniphier/uniphier_console_setup.c +++ b/plat/socionext/uniphier/uniphier_console_setup.c @@ -1,9 +1,11 @@ /* - * Copyright (c) 2019, Socionext Inc. All rights reserved. + * Copyright (c) 2019-2020, Socionext Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <assert.h> + #include <drivers/console.h> #include <errno.h> #include <lib/mmio.h> @@ -12,9 +14,8 @@ #include "uniphier.h" #include "uniphier_console.h" -#define UNIPHIER_UART_BASE 0x54006800 -#define UNIPHIER_UART_END 0x54006c00 #define UNIPHIER_UART_OFFSET 0x100 +#define UNIPHIER_UART_NR_PORTS 4 struct uniphier_console { struct console console; @@ -40,16 +41,26 @@ static struct uniphier_console uniphier_console = { }, }; +static const uintptr_t uniphier_uart_base[] = { + [UNIPHIER_SOC_LD11] = 0x54006800, + [UNIPHIER_SOC_LD20] = 0x54006800, + [UNIPHIER_SOC_PXS3] = 0x54006800, +}; + /* * There are 4 UART ports available on this platform. By default, we want to * use the same one as used in the previous firmware stage. */ -static uintptr_t uniphier_console_get_base(void) +static uintptr_t uniphier_console_get_base(unsigned int soc) { - uintptr_t base = UNIPHIER_UART_BASE; + uintptr_t base, end; uint32_t div; - while (base < UNIPHIER_UART_END) { + assert(soc < ARRAY_SIZE(uniphier_uart_base)); + base = uniphier_uart_base[soc]; + end = base + UNIPHIER_UART_OFFSET * UNIPHIER_UART_NR_PORTS; + + while (base < end) { div = mmio_read_32(base + UNIPHIER_UART_DLR); if (div) return base; @@ -66,11 +77,11 @@ static void uniphier_console_init(uintptr_t base) UNIPHIER_UART_LCR_WLEN8 << 8); } -void uniphier_console_setup(void) +void uniphier_console_setup(unsigned int soc) { uintptr_t base; - base = uniphier_console_get_base(); + base = uniphier_console_get_base(soc); if (!base) plat_error_handler(-EINVAL); diff --git a/plat/socionext/uniphier/uniphier_emmc.c b/plat/socionext/uniphier/uniphier_emmc.c index d666ba7814..b3d23cbed3 100644 --- a/plat/socionext/uniphier/uniphier_emmc.c +++ b/plat/socionext/uniphier/uniphier_emmc.c @@ -87,7 +87,12 @@ struct uniphier_mmc_cmd { unsigned int is_data; }; -static int uniphier_emmc_block_addressing; +struct uniphier_emmc_host { + uintptr_t base; + bool is_block_addressing; +}; + +static struct uniphier_emmc_host uniphier_emmc_host; static int uniphier_emmc_send_cmd(uintptr_t host_base, struct uniphier_mmc_cmd *cmd) @@ -157,7 +162,8 @@ static int uniphier_emmc_switch_part(uintptr_t host_base, int part_num) return uniphier_emmc_send_cmd(host_base, &cmd); } -static int uniphier_emmc_is_over_2gb(uintptr_t host_base) +static int uniphier_emmc_check_device_size(uintptr_t host_base, + bool *is_block_addressing) { struct uniphier_mmc_cmd cmd = {0}; uint32_t csd40, csd72; /* CSD[71:40], CSD[103:72] */ @@ -174,7 +180,10 @@ static int uniphier_emmc_is_over_2gb(uintptr_t host_base) csd40 = mmio_read_32(host_base + SDHCI_RESPONSE + 4); csd72 = mmio_read_32(host_base + SDHCI_RESPONSE + 8); - return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3); + /* C_SIZE == 0xfff && C_SIZE_MULT == 0x7 ? */ + *is_block_addressing = !(~csd40 & 0xffc00380) && !(~csd72 & 0x3); + + return 0; } static int uniphier_emmc_load_image(uintptr_t host_base, @@ -210,15 +219,15 @@ static int uniphier_emmc_load_image(uintptr_t host_base, static size_t uniphier_emmc_read(int lba, uintptr_t buf, size_t size) { - uintptr_t host_base = 0x5a000200; int ret; inv_dcache_range(buf, size); - if (!uniphier_emmc_block_addressing) + if (!uniphier_emmc_host.is_block_addressing) lba *= 512; - ret = uniphier_emmc_load_image(host_base, lba, buf, size / 512); + ret = uniphier_emmc_load_image(uniphier_emmc_host.base, + lba, buf, size / 512); inv_dcache_range(buf, size); @@ -232,10 +241,10 @@ static struct io_block_dev_spec uniphier_emmc_dev_spec = { .block_size = 512, }; -static int uniphier_emmc_hw_init(void) +static int uniphier_emmc_hw_init(struct uniphier_emmc_host *host) { - uintptr_t host_base = 0x5a000200; struct uniphier_mmc_cmd cmd = {0}; + uintptr_t host_base = uniphier_emmc_host.base; int ret; /* @@ -253,12 +262,11 @@ static int uniphier_emmc_hw_init(void) while (mmio_read_8(host_base + SDHCI_SOFTWARE_RESET)) ; - ret = uniphier_emmc_is_over_2gb(host_base); - if (ret < 0) + ret = uniphier_emmc_check_device_size(host_base, + &uniphier_emmc_host.is_block_addressing); + if (ret) return ret; - uniphier_emmc_block_addressing = ret; - cmd.cmdarg = UNIPHIER_EMMC_RCA << 16; /* select card again */ @@ -274,11 +282,23 @@ static int uniphier_emmc_hw_init(void) return 0; } -int uniphier_emmc_init(struct io_block_dev_spec **block_dev_spec) +static const uintptr_t uniphier_emmc_base[] = { + [UNIPHIER_SOC_LD11] = 0x5a000200, + [UNIPHIER_SOC_LD20] = 0x5a000200, + [UNIPHIER_SOC_PXS3] = 0x5a000200, +}; + +int uniphier_emmc_init(unsigned int soc, + struct io_block_dev_spec **block_dev_spec) { int ret; - ret = uniphier_emmc_hw_init(); + assert(soc < ARRAY_SIZE(uniphier_emmc_base)); + uniphier_emmc_host.base = uniphier_emmc_base[soc]; + if (uniphier_emmc_host.base == 0UL) + return -ENOTSUP; + + ret = uniphier_emmc_hw_init(&uniphier_emmc_host); if (ret) return ret; diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c index 89c8718b4e..96180f159a 100644 --- a/plat/socionext/uniphier/uniphier_io_storage.c +++ b/plat/socionext/uniphier/uniphier_io_storage.c @@ -249,24 +249,24 @@ static int uniphier_io_fip_setup(void) return io_dev_open(uniphier_fip_dev_con, 0, &uniphier_fip_dev_handle); } -static int uniphier_io_emmc_setup(unsigned int soc_id, size_t buffer_offset) +static int uniphier_io_emmc_setup(unsigned int soc, size_t buffer_offset) { struct io_block_dev_spec *block_dev_spec; int ret; - ret = uniphier_emmc_init(&block_dev_spec); + ret = uniphier_emmc_init(soc, &block_dev_spec); if (ret) return ret; return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset); } -static int uniphier_io_nand_setup(unsigned int soc_id, size_t buffer_offset) +static int uniphier_io_nand_setup(unsigned int soc, size_t buffer_offset) { struct io_block_dev_spec *block_dev_spec; int ret; - ret = uniphier_nand_init(&block_dev_spec); + ret = uniphier_nand_init(soc, &block_dev_spec); if (ret) return ret; diff --git a/plat/socionext/uniphier/uniphier_nand.c b/plat/socionext/uniphier/uniphier_nand.c index 3925177ede..71cb96c0a1 100644 --- a/plat/socionext/uniphier/uniphier_nand.c +++ b/plat/socionext/uniphier/uniphier_nand.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <assert.h> #include <stdint.h> #include <platform_def.h> @@ -237,8 +238,7 @@ static int uniphier_nand_hw_init(struct uniphier_nand *nand) for (i = 0; i < ARRAY_SIZE(nand->bbt); i++) nand->bbt[i] = UNIPHIER_NAND_BBT_UNKNOWN; - nand->host_base = 0x68000000; - nand->reg_base = 0x68100000; + nand->reg_base = nand->host_base + 0x100000; nand->pages_per_block = mmio_read_32(nand->reg_base + DENALI_PAGES_PER_BLOCK); @@ -255,10 +255,22 @@ static int uniphier_nand_hw_init(struct uniphier_nand *nand) return 0; } -int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec) +static const uintptr_t uniphier_nand_base[] = { + [UNIPHIER_SOC_LD11] = 0x68000000, + [UNIPHIER_SOC_LD20] = 0x68000000, + [UNIPHIER_SOC_PXS3] = 0x68000000, +}; + +int uniphier_nand_init(unsigned int soc, + struct io_block_dev_spec **block_dev_spec) { int ret; + assert(soc < ARRAY_SIZE(uniphier_nand_base)); + uniphier_nand.host_base = uniphier_nand_base[soc]; + if (!uniphier_nand.host_base) + return -ENOTSUP; + ret = uniphier_nand_hw_init(&uniphier_nand); if (ret) return ret; diff --git a/plat/socionext/uniphier/uniphier_psci.c b/plat/socionext/uniphier/uniphier_psci.c index 2acc874401..a371705b19 100644 --- a/plat/socionext/uniphier/uniphier_psci.c +++ b/plat/socionext/uniphier/uniphier_psci.c @@ -1,9 +1,11 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <assert.h> + #include <arch_helpers.h> #include <common/debug.h> #include <errno.h> @@ -12,15 +14,18 @@ #include "uniphier.h" -#define UNIPHIER_ROM_RSV0 0x59801200 +#define UNIPHIER_ROM_RSV0 0x0 -#define UNIPHIER_SLFRSTSEL 0x61843010 +#define UNIPHIER_SLFRSTSEL 0x10 #define UNIPHIER_SLFRSTSEL_MASK GENMASK(1, 0) -#define UNIPHIER_SLFRSTCTL 0x61843014 +#define UNIPHIER_SLFRSTCTL 0x14 #define UNIPHIER_SLFRSTCTL_RST BIT(0) #define MPIDR_AFFINITY_INVALID ((u_register_t)-1) +static uintptr_t uniphier_rom_rsv_base; +static uintptr_t uniphier_slfrst_base; + uintptr_t uniphier_sec_entrypoint; void uniphier_warmboot_entrypoint(void); @@ -34,7 +39,7 @@ static int uniphier_psci_pwr_domain_on(u_register_t mpidr) flush_dcache_range((uint64_t)&uniphier_holding_pen_release, sizeof(uniphier_holding_pen_release)); - mmio_write_64(UNIPHIER_ROM_RSV0, + mmio_write_64(uniphier_rom_rsv_base + UNIPHIER_ROM_RSV0, (uint64_t)&uniphier_warmboot_entrypoint); sev(); @@ -71,8 +76,10 @@ static void __dead2 uniphier_psci_pwr_domain_pwr_down_wfi( static void uniphier_self_system_reset(void) { - mmio_clrbits_32(UNIPHIER_SLFRSTSEL, UNIPHIER_SLFRSTSEL_MASK); - mmio_setbits_32(UNIPHIER_SLFRSTCTL, UNIPHIER_SLFRSTCTL_RST); + mmio_clrbits_32(uniphier_slfrst_base + UNIPHIER_SLFRSTSEL, + UNIPHIER_SLFRSTSEL_MASK); + mmio_setbits_32(uniphier_slfrst_base + UNIPHIER_SLFRSTCTL, + UNIPHIER_SLFRSTCTL_RST); } static void __dead2 uniphier_psci_system_off(void) @@ -114,13 +121,40 @@ static const struct plat_psci_ops uniphier_psci_ops = { int plat_setup_psci_ops(uintptr_t sec_entrypoint, const struct plat_psci_ops **psci_ops) { - unsigned int soc; + uniphier_sec_entrypoint = sec_entrypoint; + flush_dcache_range((uint64_t)&uniphier_sec_entrypoint, + sizeof(uniphier_sec_entrypoint)); - soc = uniphier_get_soc_id(); - if (soc == UNIPHIER_SOC_UNKNOWN) { - ERROR("unsupported SoC\n"); - return -ENOTSUP; - } + *psci_ops = &uniphier_psci_ops; + + return 0; +} + +struct uniphier_psci_ctrl_base { + uintptr_t rom_rsv_base; + uintptr_t slfrst_base; +}; + +static const struct uniphier_psci_ctrl_base uniphier_psci_ctrl_base[] = { + [UNIPHIER_SOC_LD11] = { + .rom_rsv_base = 0x59801200, + .slfrst_base = 0x61843000, + }, + [UNIPHIER_SOC_LD20] = { + .rom_rsv_base = 0x59801200, + .slfrst_base = 0x61843000, + }, + [UNIPHIER_SOC_PXS3] = { + .rom_rsv_base = 0x59801200, + .slfrst_base = 0x61843000, + }, +}; + +void uniphier_psci_init(unsigned int soc) +{ + assert(soc < ARRAY_SIZE(uniphier_psci_ctrl_base)); + uniphier_rom_rsv_base = uniphier_psci_ctrl_base[soc].rom_rsv_base; + uniphier_slfrst_base = uniphier_psci_ctrl_base[soc].slfrst_base; if (uniphier_get_boot_master(soc) == UNIPHIER_BOOT_MASTER_SCP) { uniphier_psci_scp_mode = uniphier_scp_is_running(); @@ -130,12 +164,4 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, if (uniphier_psci_scp_mode) uniphier_scp_open_com(); } - - uniphier_sec_entrypoint = sec_entrypoint; - flush_dcache_range((uint64_t)&uniphier_sec_entrypoint, - sizeof(uniphier_sec_entrypoint)); - - *psci_ops = &uniphier_psci_ops; - - return 0; } diff --git a/plat/socionext/uniphier/uniphier_xlat_setup.c b/plat/socionext/uniphier/uniphier_xlat_setup.c index 18d2f9e938..66c7834f54 100644 --- a/plat/socionext/uniphier/uniphier_xlat_setup.c +++ b/plat/socionext/uniphier/uniphier_xlat_setup.c @@ -4,15 +4,36 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <assert.h> + #include <platform_def.h> #include <common/debug.h> #include <lib/xlat_tables/xlat_tables_v2.h> -#define UNIPHIER_REG_REGION_BASE 0x50000000ULL -#define UNIPHIER_REG_REGION_SIZE 0x20000000ULL +#include "uniphier.h" + +struct uniphier_reg_region { + uintptr_t base; + size_t size; +}; + +static const struct uniphier_reg_region uniphier_reg_region[] = { + [UNIPHIER_SOC_LD11] = { + .base = 0x50000000UL, + .size = 0x20000000UL, + }, + [UNIPHIER_SOC_LD20] = { + .base = 0x50000000UL, + .size = 0x20000000UL, + }, + [UNIPHIER_SOC_PXS3] = { + .base = 0x50000000UL, + .size = 0x20000000UL, + }, +}; -void uniphier_mmap_setup(void) +void uniphier_mmap_setup(unsigned int soc) { VERBOSE("Trusted RAM seen by this BL image: %p - %p\n", (void *)BL_CODE_BASE, (void *)BL_END); @@ -35,8 +56,10 @@ void uniphier_mmap_setup(void) MT_DEVICE | MT_RW | MT_SECURE); /* register region */ - mmap_add_region(UNIPHIER_REG_REGION_BASE, UNIPHIER_REG_REGION_BASE, - UNIPHIER_REG_REGION_SIZE, + assert(soc < ARRAY_SIZE(uniphier_reg_region)); + mmap_add_region(uniphier_reg_region[soc].base, + uniphier_reg_region[soc].base, + uniphier_reg_region[soc].size, MT_DEVICE | MT_RW | MT_SECURE); init_xlat_tables(); |